CN112992773B - Alignment mark forming method for deep trench isolation and semiconductor device structure - Google Patents
Alignment mark forming method for deep trench isolation and semiconductor device structure Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 64
- 238000002955 isolation Methods 0.000 title claims abstract description 29
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 95
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 53
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 53
- 239000010703 silicon Substances 0.000 claims abstract description 53
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 30
- 238000005530 etching Methods 0.000 claims abstract description 22
- 238000005498 polishing Methods 0.000 claims abstract description 5
- 239000000126 substance Substances 0.000 claims abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 238000001259 photo etching Methods 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 238000004026 adhesive bonding Methods 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
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Abstract
The application discloses an alignment mark forming method for deep trench isolation, and relates to the field of semiconductor manufacturing. The method comprises forming an alignment dielectric layer on the surface of a substrate; forming an alignment mark pattern and a deep groove pattern on the alignment medium layer, wherein the alignment mark pattern is positioned in the alignment mark region, and the deep groove pattern is positioned in the device region; protecting the alignment mark region, and etching the substrate according to the deep groove pattern to form a deep groove; forming a silicon epitaxial layer on a substrate, and carrying out CMP (chemical mechanical polishing) treatment on the substrate; protecting the alignment mark region and removing the alignment medium layer in the device region; performing CMP treatment on the substrate, removing the silicon epitaxial layer on the device region, which is higher than the surface of the substrate, and keeping an alignment dielectric layer and the silicon epitaxial layer with preset thicknesses on the surface of the alignment mark region; the problem that the process quality is easily influenced by the alignment marks in the traditional deep groove process is solved; the effects of ensuring the surface smoothness of the substrate when a clear alignment mark is formed and improving the photoresist gluing uniformity in the subsequent process are achieved.
Description
Technical Field
The application relates to the field of semiconductor manufacturing, in particular to an alignment mark forming method for deep trench isolation and a semiconductor device structure.
Background
Deep trench isolation is widely used in the manufacture of a variety of semiconductor devices, such as: Bi-CMOS, high voltage devices, image sensors, etc. The deep trench isolation needs to use a zero alignment layer in the forming process, taking the manufacture of a CMOS device as an example, firstly, an alignment mark and a deep trench are etched on the surface of a flat silicon wafer, then, ion implantation is carried out to form a silicon epitaxial layer, and then, relevant steps of a CMOS process are carried out.
The existing deep trench isolation process has many defects, for example, the alignment mark is not clear, the alignment precision is not high, and the height difference of the alignment mark led out from the surface of the silicon wafer can cause uneven photoresist gluing in the subsequent process, which can cause device performance problems.
Disclosure of Invention
In order to solve the problems in the related art, the application provides an alignment mark forming method for deep trench isolation and a semiconductor device structure. The technical scheme is as follows:
in a first aspect, an embodiment of the present application provides a method for forming an alignment mark for deep trench isolation, the method including:
forming an alignment dielectric layer on the surface of the substrate, wherein the alignment dielectric layer is used for forming an alignment mark;
forming an alignment mark pattern and a deep groove pattern on the alignment medium layer, wherein the alignment mark pattern is positioned in the alignment mark region, and the deep groove pattern is positioned in the device region;
protecting the alignment mark region, and etching the substrate according to the deep groove pattern to form a deep groove;
forming a silicon epitaxial layer on a substrate, and carrying out CMP (chemical mechanical polishing) treatment on the substrate;
protecting the alignment mark region and removing the alignment medium layer in the device region;
and performing CMP treatment on the substrate, removing the silicon epitaxial layer on the device region, which is higher than the surface of the substrate, and keeping the alignment dielectric layer and the silicon epitaxial layer with preset thicknesses on the surface of the alignment mark region.
Optionally, the material of the alignment dielectric layer is silicon oxide or silicon nitride.
Optionally, the thickness of the alignment dielectric layer is 100nm-600 nm.
Optionally, protecting the alignment mark region, and etching the substrate according to the deep trench pattern to form a deep trench, including:
covering photoresist in the alignment mark region by a photoetching process, and exposing a device region;
etching the substrate according to the deep groove pattern of the device region to form a deep groove;
and removing the photoresist on the alignment mark area.
Optionally, forming an alignment mark pattern and a deep trench pattern on the alignment dielectric layer includes:
and forming an alignment mark pattern and a deep groove pattern on the alignment dielectric layer by photoetching and etching processes.
Optionally, forming a silicon epitaxial layer on the substrate includes:
and growing a silicon epitaxial layer, and completely filling gaps in the deep groove and the alignment dielectric layer by the silicon epitaxial layer.
Optionally, protecting the alignment mark region and removing the alignment dielectric layer in the device region, including:
covering photoresist in the alignment mark region by a photoetching process, and exposing a device region;
removing the alignment dielectric layer in the device region by an etching process;
and removing the photoresist on the surface of the alignment mark area.
In a second aspect, embodiments of the present application provide a semiconductor device structure, including a substrate, the substrate including an alignment mark region and a device region;
in the device region, a deep trench isolation is formed in the substrate;
in the alignment mark area, an alignment mark is formed on the surface of the substrate, the alignment mark is composed of an alignment medium layer and a silicon epitaxial layer, the thicknesses of the alignment medium layer and the silicon epitaxial layer are the same, and the silicon epitaxial layer fills a gap in the alignment medium layer.
Optionally, the material of the alignment dielectric layer is silicon dioxide or silicon nitride.
The technical scheme at least comprises the following advantages:
forming an alignment dielectric layer on the surface of a substrate, etching the alignment dielectric layer to form an alignment mark pattern and a deep groove pattern, protecting an alignment mark region in the process of etching the deep groove, preventing the substrate of the alignment mark pattern and the alignment mark region from being etched, forming a silicon epitaxial layer on the substrate after the deep groove in the substrate is etched, completely filling a gap between the deep groove and the alignment mark pattern, protecting the alignment mark region, removing the alignment dielectric layer of a device region, performing CMP (chemical mechanical polishing) on the substrate, removing the silicon epitaxial layer of the device region higher than the surface of the substrate, forming a deep groove isolation in the device region, and reserving the alignment dielectric layer and the silicon epitaxial layer with preset thicknesses in the alignment mark region to form an alignment mark; the problem that the process quality is easily influenced by the alignment marks in the traditional deep groove process is solved; the effects of ensuring the surface smoothness of the substrate when a clear alignment mark is formed and improving the photoresist gluing uniformity in the subsequent process are achieved.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a flow chart of a method for forming alignment marks for deep trench isolation according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of an embodiment of an alignment mark forming method for deep trench isolation according to the present disclosure;
FIG. 3 is a schematic diagram of an embodiment of an alignment mark forming method for deep trench isolation according to the present disclosure;
FIG. 4 is a schematic diagram of an embodiment of an alignment mark forming method for deep trench isolation provided in the present application;
FIG. 5 is a schematic diagram of an embodiment of an alignment mark forming method for deep trench isolation provided in the present application;
FIG. 6 is a schematic diagram of an embodiment of an alignment mark forming method for deep trench isolation provided in the present application;
fig. 7 is an implementation diagram of an alignment mark forming method for deep trench isolation according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless otherwise explicitly stated or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, a fixed connection, a detachable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 1, a flowchart of a method for forming an alignment mark for deep trench isolation according to an embodiment of the present application is shown, where the method includes at least the following steps:
Optionally, an alignment dielectric layer is deposited or grown on the surface of the substrate.
The thickness of the alignment dielectric layer is determined according to actual conditions.
As shown in fig. 2, an alignment dielectric layer 22 is formed on the surface of the substrate 21.
And 102, forming an alignment mark pattern and a deep groove pattern on the alignment dielectric layer, wherein the alignment mark pattern is positioned in the alignment mark region, and the deep groove pattern is positioned in the device region.
As shown in fig. 3, substrate 21 includes alignment mark region S1 and device region S2; alignment mark patterns 23 are formed in the alignment dielectric layer on the alignment mark region S1, and deep trench patterns 24 are formed in the alignment dielectric layer on the device region S2.
And 103, protecting the alignment mark region, and etching the substrate according to the deep groove pattern to form a deep groove.
The alignment mark pattern 23 on the surface of the alignment mark region is protected by the photoresist 20, and the substrate 21 is etched according to the deep trench pattern 24 to form a deep trench 25 in the substrate 21, as shown in fig. 4. After the deep trench is formed by etching, the photoresist on the surface of the substrate is removed, and the substrate of the alignment mark region S1 is not etched.
Growing a silicon epitaxial layer 26 on the substrate and planarizing the substrate by using a CMP process; silicon epitaxial layer 26 completely fills deep trenches 25 in device region S2, and gaps in alignment mark pattern 23 at the surface of alignment mark region S1, as shown in fig. 5.
And 105, protecting the alignment mark region and removing the alignment dielectric layer in the device region.
As shown in fig. 6, photoresist 27 is used to protect alignment mark region S1, the alignment mark pattern on the surface of alignment mark region S1 is covered by photoresist 27, device region S2 is exposed, and the alignment dielectric layer on the surface of device region S2 is removed, as shown in fig. 6; since the alignment dielectric layer on the surface of the device region S2 is removed, the silicon epitaxial layer 26 in the device region S2 is higher than the surface of the substrate 21. And after the alignment dielectric layer of the device region S2 is removed, removing the photoresist on the surface of the substrate.
And 106, performing CMP treatment on the substrate, removing the silicon epitaxial layer on the device region, which is higher than the surface of the substrate, and keeping the alignment dielectric layer and the silicon epitaxial layer with preset thicknesses on the surface of the alignment mark region.
Performing CMP processing on the substrate, flattening the device region S2, removing a silicon epitaxial layer on the device region S2 and higher than the surface of the substrate 21, and forming deep trench isolation in the substrate 21; the alignment mark region S1 is planarized to remove a portion of the alignment dielectric layer 22 and the silicon epitaxial layer 26, and a predetermined thickness of the alignment dielectric layer 22 and the silicon epitaxial layer 26 remains, as shown in fig. 7.
In the subsequent process steps, the alignment dielectric layer 22 and the silicon epitaxial layer 26 on the surface of the alignment mark region S1 are used together as an alignment mark.
The predetermined thickness is determined according to actual conditions.
To sum up, the alignment mark forming method for deep trench isolation provided by the embodiment of the present application forms an alignment dielectric layer through a substrate surface, etches the alignment dielectric layer to form an alignment mark pattern and a deep trench pattern, protects the alignment mark region during the process of etching the deep trench, prevents the substrate of the alignment mark pattern and the alignment mark region from being etched, forms a silicon epitaxial layer on the substrate after the deep trench in the substrate is etched, completely fills a gap between the deep trench and the alignment mark pattern, protects the alignment mark region again, removes the alignment dielectric layer of the device region, performs CMP processing on the substrate, removes the silicon epitaxial layer of the device region higher than the substrate surface, forms deep trench isolation in the device region, and retains the alignment dielectric layer and the silicon epitaxial layer with predetermined thickness in the alignment mark region to form an alignment mark; the problem that the process quality is easily influenced by the alignment marks in the traditional deep groove process is solved; the effects of ensuring the surface smoothness of the substrate when a clear alignment mark is formed and improving the photoresist gluing uniformity in the subsequent process are achieved.
Another embodiment of the present application provides a method for forming an alignment mark for deep trench isolation, the method at least comprising the following steps:
step 202, forming an alignment dielectric layer on the surface of the substrate, wherein the alignment dielectric layer is used for forming an alignment mark.
Optionally, an alignment dielectric layer is deposited or grown on the surface of the substrate.
Optionally, the thickness of the alignment mark layer is 100nm-600 nm.
Optionally, the material of the alignment dielectric layer is silicon oxide or silicon nitride.
As shown in fig. 2, an alignment dielectric layer 22 is formed on the surface of the substrate 21.
In step 202, an alignment mark pattern and a deep trench pattern are formed on the alignment dielectric layer by photolithography and etching processes.
Coating photoresist on the surface of the alignment dielectric layer, exposing and developing, etching the alignment dielectric layer, forming an alignment mark pattern in an alignment mark region of the substrate, and forming a deep groove pattern in a device region of the substrate. The substrate below the alignment dielectric layer is not etched.
Optionally, the etching process is dry etching or wet etching.
As shown in fig. 3, substrate 21 includes alignment mark region S1 and device region S2; alignment mark patterns 23 are formed in the alignment dielectric layer on alignment mark region S1, and deep trench patterns 24 are formed in the alignment dielectric layer on device region S2.
Step 203, covering photoresist in the alignment mark region through a photolithography process, and exposing the device region.
And coating photoresist on the substrate, exposing by using a zero alignment layer mask, and exposing the device area after developing, wherein the photoresist covers the surface of the alignment mark area.
And 204, etching the substrate according to the deep groove pattern of the device region to form a deep groove.
As shown in fig. 4, the surface of the alignment mark region S1 is covered with the photoresist 20, the substrate 21 is etched, the mark region S1 is not etched under the protection of the photoresist 20, the substrate 21 corresponding to the deep trench pattern 24 is etched in the device region S2, and the deep trench 25 is formed in the substrate 21, as shown in fig. 4.
In one example, the deep trench is 1-4 μm deep.
Step 205, removing the photoresist on the alignment mark region.
And step 206, growing a silicon epitaxial layer, wherein the gaps in the deep trench and the alignment dielectric layer are completely filled with the silicon epitaxial layer.
Optionally, a silicon epitaxial layer is grown on the substrate through an epitaxial growth process, and gaps between the deep trench of the device region and the alignment mark pattern on the surface of the alignment mark region are completely filled with the grown silicon epitaxial layer.
In one example, the grown silicon epitaxial layer has a thickness of 1 μm to 8 μm.
Step 207, a CMP process is performed on the substrate.
After the silicon epitaxial layer grows, the surface of the substrate is uneven, and the substrate is subjected to CMP treatment to grind the surface of the substrate flat. In the CMP treatment of the step, the alignment dielectric layer below the silicon epitaxial layer is not consumed.
In step 208, a photoresist is covered on the alignment mark region by a photolithography process, and the device region is exposed.
And coating photoresist on the substrate, exposing by using a zero alignment layer mask, and exposing the device area after developing, wherein the photoresist covers the surface of the alignment mark area.
Step 209, the alignment dielectric layer in the device region is removed by an etching process.
Optionally, the etching process is wet etching or dry etching.
As shown in fig. 6, the surface of alignment mark region S1 is covered by photoresist 27, and the alignment dielectric layer on the surface of device region S2 is removed. During the process of removing the alignment dielectric layer on the device region S2, the alignment mark region S1 is protected by the photoresist 27 and is not etched.
Step 210, removing the photoresist on the surface of the alignment mark region.
Step 211, performing CMP on the substrate, removing the silicon epitaxial layer on the device region, which is higher than the substrate surface, and leaving the alignment dielectric layer and the silicon epitaxial layer with predetermined thicknesses on the surface of the alignment mark region.
Optionally, the thickness of the remaining alignment dielectric layer is 50nm-300 nm.
The thickness of the alignment dielectric layer reserved on the surface of the alignment mark area is equal to that of the silicon epitaxial layer.
As shown in fig. 7, the present embodiments provide a semiconductor device structure formed during the formation of a deep trench of the device. The semiconductor device structure includes a substrate 21, and the substrate 21 includes an alignment mark region S1 and a device region S2.
In the device region S2, a deep trench isolation is formed in the substrate, the deep trench isolation being made up of a deep trench in the substrate and the silicon epitaxial layer 26 filling the deep trench.
In the alignment mark region S1, an alignment mark is formed on the substrate surface, the alignment mark is composed of the alignment dielectric layer 22 and the silicon epitaxial layer 26, the thicknesses of the alignment dielectric layer 22 and the silicon epitaxial layer 26 are the same, and the silicon epitaxial layer 26 in the alignment mark region S1 fills the gap in the alignment dielectric layer 22.
The alignment marks are located on the surface of the substrate 21. Optionally, the alignment mark is 50nm-300nm higher than the surface of the device region.
According to the semiconductor device structure provided by the embodiment of the application, the alignment mark is formed simultaneously in the deep trench isolation forming process, the alignment mark is arranged on the surface of the substrate, the height difference between the alignment mark and the surface of the substrate is reduced, the definition of the alignment mark is ensured, the flatness of the surface of the substrate is ensured, and the reliability of a photoetching gluing process in a subsequent process is improved.
Optionally, the material of the alignment dielectric layer is silicon dioxide or silicon nitride.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (8)
1. A method of forming an alignment mark for deep trench isolation, the method comprising:
forming an alignment dielectric layer on the surface of a substrate, wherein the alignment dielectric layer is used for forming an alignment mark;
forming an alignment mark pattern and a deep groove pattern on the alignment medium layer, wherein the alignment mark pattern is positioned in an alignment mark region, and the deep groove pattern is positioned in a device region;
protecting the alignment mark region, and etching the substrate according to the deep groove pattern to form a deep groove;
growing a silicon epitaxial layer, wherein gaps in the deep groove and the alignment dielectric layer are completely filled by the silicon epitaxial layer, and the substrate is subjected to CMP (chemical mechanical polishing);
protecting the alignment mark region and removing the alignment dielectric layer of the device region;
and performing CMP (chemical mechanical polishing) treatment on the substrate, removing the silicon epitaxial layer which is higher than the surface of the substrate on the device region, and reserving an alignment dielectric layer and the silicon epitaxial layer with preset thicknesses on the surface of the alignment mark region.
2. The method of claim 1, wherein the material of the alignment dielectric layer is silicon oxide or silicon nitride.
3. The method of claim 1 or 2, wherein the thickness of the alignment dielectric layer is 100nm to 600 nm.
4. The method of claim 1, wherein the protecting the alignment mark region and etching the substrate according to the deep trench pattern to form a deep trench comprises:
covering photoresist in the alignment mark region through a photoetching process, and exposing the device region;
etching the substrate according to the deep groove pattern of the device region to form a deep groove;
and removing the photoresist on the alignment mark area.
5. The method of claim 1, wherein the forming an alignment mark pattern and a deep trench pattern on the alignment dielectric layer comprises:
and forming an alignment mark pattern and a deep groove pattern on the alignment dielectric layer by photoetching and etching processes.
6. The method of claim 1, wherein the protecting the alignment mark region and removing the alignment dielectric layer of the device region comprises:
covering photoresist on the alignment mark region through a photoetching process, and exposing the device region;
removing the alignment dielectric layer of the device region through an etching process;
and removing the photoresist on the surface of the alignment mark area.
7. A semiconductor device structure is characterized by comprising a substrate, wherein the substrate comprises an alignment mark region and a device region;
in the device region, a deep trench isolation is formed in the substrate, wherein the deep trench isolation is composed of a deep trench in the substrate and a silicon epitaxial layer filling the deep trench;
in the alignment mark region, an alignment mark is formed on the surface of the substrate, the alignment mark is composed of an alignment medium layer and a silicon epitaxial layer, the thicknesses of the alignment medium layer and the silicon epitaxial layer are the same, and the silicon epitaxial layer fills gaps in the alignment medium layer.
8. The semiconductor device structure of claim 7, wherein the material of the alignment dielectric layer is silicon dioxide or silicon nitride.
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| CN114121775A (en) * | 2021-11-25 | 2022-03-01 | 华虹半导体(无锡)有限公司 | Method for manufacturing semiconductor device containing deep trench structure |
| CN115020307B (en) * | 2022-05-30 | 2025-02-07 | 上海积塔半导体有限公司 | Semiconductor structure preparation method |
| CN115347457B (en) * | 2022-08-24 | 2024-09-06 | 全磊光电股份有限公司 | Semiconductor laser and manufacturing method thereof |
| CN116072519A (en) * | 2023-01-31 | 2023-05-05 | 上海积塔半导体有限公司 | Photolithography process method |
| CN118571863B (en) * | 2024-07-30 | 2024-11-12 | 合肥晶合集成电路股份有限公司 | Alignment mark preparation method and semiconductor structure |
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| CN103035511A (en) * | 2011-10-09 | 2013-04-10 | 上海华虹Nec电子有限公司 | Method for producing zero layer photoetching marking of high-voltage device without barrier layers |
| CN104658889A (en) * | 2015-02-10 | 2015-05-27 | 上海华虹宏力半导体制造有限公司 | Manufacturing method for alignment mark of two-groove type superjunction device |
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| TW546698B (en) * | 2000-11-02 | 2003-08-11 | Macronix Int Co Ltd | Alignment method of photolithography process |
| US7611961B2 (en) * | 2006-12-20 | 2009-11-03 | Macronix International Co., Ltd. | Method for fabricating semiconductor wafer with enhanced alignment performance |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103035511A (en) * | 2011-10-09 | 2013-04-10 | 上海华虹Nec电子有限公司 | Method for producing zero layer photoetching marking of high-voltage device without barrier layers |
| CN104658889A (en) * | 2015-02-10 | 2015-05-27 | 上海华虹宏力半导体制造有限公司 | Manufacturing method for alignment mark of two-groove type superjunction device |
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