CN112992221B - SRAM (static random Access memory) storage unit based on back gate structure, SRAM memory and power-on method - Google Patents

Abstract

The invention discloses an SRAM memory cell based on a back gate structure, an SRAM memory and a power-on method, and belongs to the field of semiconductors. The technical problem that when a certain storage unit stores fixed data for a long time, BT I aging effects of different degrees occur on two symmetrical transistors to generate permanent threshold voltage mismatch, and therefore an SRAM storage unit is powered on, and a power-on initial value opposite to an original storage value is read out with a certain probability is solved. The SRAM storage unit based on the back gate structure comprises a first inverter and a second inverter; the transistors in the first inverter and the second inverter are both back gate transistors; the back gate of the transistor in the first inverter has a first connection mode, the back gate of the transistor in the second inverter has a second connection mode, and when the SRAM storage unit based on the back gate structure is powered on, the threshold voltage of the transistor in the first inverter is different from the threshold voltage of the transistor in the second inverter.

Description

A kind of SRAM storage unit based on back gate structure, SRAM memory and power-on method

technical field

The invention relates to the technical field of semiconductors, in particular to an SRAM storage unit based on a back gate structure, an SRAM memory and a power-on method.

Background technique

SRAM (Random-Access Memory, static random access memory) is a kind of memory with static access function, which can save the data stored in it without refreshing the circuit. When SRAM is used in a chip, when the chip system detects unauthorized access, the chip system can cut off the power supply of the SRAM to prevent attackers from stealing data. However, SRAM has the problem of information residue, and the information stored before power failure can be partially restored by aging imprint extraction. Among them, aging imprint extraction means that when a memory cell stores fixed data for a long time, two symmetrical transistors will experience different degrees of BTI (Bias Temperature Instability, bias temperature instability) aging effect, resulting in a permanent threshold voltage The mismatch causes the SRAM storage unit to have a certain probability (about 10% to 20%) to read the power-on initial value opposite to the original stored value after power-on.

Contents of the invention

Based on this, the object of the present invention is to provide a back gate structure based SRAM storage unit, SRAM memory and power-on method, to solve the problem that when the SRAM storage unit stores fixed data for a long time, the two symmetrical transistors will have different degrees of BTI The aging effect produces a permanent threshold voltage mismatch, which leads to a technical problem that the SRAM memory unit has a certain probability of reading the power-on initial value opposite to the original stored value after power-on.

In a first aspect, the present invention provides an SRAM memory cell based on a back gate structure, including a cross-coupled first inverter and a second inverter. The transistors in the first inverter and the second inverter are both back-gate transistors;

The back gate of the transistor in the first inverter has a first connection mode, and the back gate of the transistor in the second inverter has a second connection mode. When the SRAM memory cell based on the back gate structure is powered on, the first inverter The transistors in the first inverter and the transistors in the second inverter have different threshold voltages.

Compared with the prior art, the first inverter and the second inverter included in the SRAM storage unit based on the back gate structure provided by the present invention are both back gate transistors, and the back gate of the transistor in the first inverter It has a first connection mode, and the back gate of the transistor in the second inverter has a second connection mode. When the SRAM memory cell based on the back gate structure is powered on, the threshold voltage of the transistor in the first inverter is the same as that of the second The transistors in an inverter have different threshold voltages. In practical applications, when the SRAM storage unit is powered on, the threshold voltages of the transistors in the first inverter and the transistors in the second inverter are different, so that the transistors in the first inverter and the second inverter have different threshold voltages. The transistors in an inverter are turned on at different times. Based on this, the power-on potential of one of the two storage nodes in the SRAM memory unit tends to be “0”, and the power-on potential of the other storage node tends to be “1”. At this time, the two storage nodes in the SRAM storage unit have a fixed power-on potential, which solves the problem that when the SRAM storage unit stores fixed data for a long time, the two symmetrical transistors will have different degrees of BTI aging effect, resulting in a permanent threshold The voltage mismatch causes the technical problem that the SRAM storage unit has a certain probability of reading the power-on initial value opposite to the original stored value after power-on.

In the second aspect, the present invention also discloses an SRAM memory, including the above-mentioned SRAM memory unit based on the back gate structure.

In the third aspect, the present invention also discloses a power-on method, including:

Connecting the back gate of the transistor in the first inverter by using the first connection method, and connecting the back gate of the transistor in the second inverter by using the second connection method;

Controlling the power-on of the SRAM memory cell based on the back gate structure, the threshold voltage of the transistor in the first inverter is greater than or lower than the threshold voltage of the transistor in the second inverter.

The beneficial effects of the second aspect and the third aspect of the present invention are the same as those of the first aspect, and will not be repeated here.

Description of drawings

The accompanying drawings described here are used to provide a further understanding of the present invention, and constitute a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention, and do not constitute improper limitations to the present invention. In the attached picture:

FIG. 1 shows a schematic structural diagram of a main circuit in an SRAM storage unit provided by an embodiment of the present invention;

FIG. 2 shows a schematic diagram of a circuit structure of a SRAM memory cell based on a back gate structure provided by an embodiment of the present invention;

FIG. 3 shows a schematic circuit structure diagram of another SRAM memory cell based on a back gate structure provided by an embodiment of the present invention;

FIG. 4 shows a schematic circuit structure diagram of another SRAM memory cell based on a back gate structure provided by an embodiment of the present invention;

FIG. 5 shows a schematic circuit structure diagram of another SRAM memory cell based on a back gate structure provided by an embodiment of the present invention;

FIG. 6 shows a timing diagram for reading and writing of an SRAM memory cell based on a back gate structure provided by an embodiment of the present invention;

FIG. 7 shows a static noise margin mismatch diagram of a SRAM cell structure based on a back gate structure provided by an embodiment of the present invention;

FIG. 8 shows a static noise margin mismatch diagram of another SRAM cell structure based on a back gate structure provided by an embodiment of the present invention.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention.

Various schematic views of embodiments of the invention are shown in the drawings, which are not drawn to scale. Therein, certain details have been exaggerated and certain details may have been omitted for the sake of clarity. The shapes of the various regions and layers shown in the figure, as well as their relative sizes and positional relationships are only exemplary, and may deviate due to manufacturing tolerances or technical limitations in practice, and those skilled in the art will Regions/layers with different shapes, sizes, and relative positions can be additionally designed as needed.

Hereinafter, the terms "first", "second", etc. are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as "first", "second", etc. may expressly or implicitly include one or more of that feature. In the description of the present application, unless otherwise specified, "plurality" means two or more.

In the present invention, unless otherwise specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral body; it can be a direct connection, or It can be connected indirectly through an intermediary.

SRAM (Random-Access Memory, static random access memory) is a kind of memory with static access function, which can save the data stored in it without refreshing the circuit. When SRAM is used in a chip, when the chip system detects unauthorized access, the chip system can cut off the power supply of the SRAM to prevent attackers from stealing data. However, SRAM has the problem of information residue, and the information stored before power failure can be partially restored by aging imprint extraction. Among them, aging imprint extraction means that when a memory cell stores fixed data for a long time, two symmetrical transistors will have different degrees of BTI aging effect, resulting in a permanent threshold voltage mismatch, resulting in a certain SRAM memory cell after power-on. Probability (about 10% to 20%) reads the power-on initial value opposite to the original stored value.

In the related art, referring to FIG. 1 , the SRAM storage unit includes a cross-coupled first inverter 11 and a second inverter 12; after the first inverter 11 and the second inverter 12 are cross-coupled, a second inverter is formed. A storage node Q and a second storage node QB. Wherein, the first storage node Q and the second storage node QB are used to store one bit of binary information 0 or 1.

Exemplarily, the SRAM storage unit provided in the embodiment of the present invention may be a six-pipe SRAM storage unit. The six-tube SRAM storage element is a flip-flop formed by cross-coupling two MOS inverters, and one storage element stores a binary number. The six-tube SRAM storage element has two stable states, and the storage information of the first storage node and the second storage node of the six-tube SRAM storage element are always opposite to each other. For example, the storage information of the first storage node represents 0, and the storage information of the second storage node represents 1. For another example, if the storage information of the first storage node indicates 1, then the storage information of the second storage node indicates 0.

Specifically, referring to FIG. 1 , the circuit structures of the first inverter 11 and the second inverter 12 are axisymmetric along the central axis of the memory cell.

Wherein, the first inverter 11 includes a first P-type transistor P1 and a first N-type transistor N1; the source of the first P-type transistor P1 is electrically connected to the power supply terminal VDD, and the drain of the first P-type transistor P1 is connected to the first N-type transistor P1. The drain of an N-type transistor N1 is electrically connected to the first storage node Q, the source of the first N-type transistor N1 is grounded (electrically connected to the ground terminal GND), the gate of the first P-type transistor P1 is connected to the first N-type The gate of the transistor N1 is electrically connected to the second storage node QB.

The second inverter includes 12 second P-type transistor P2 and second N-type transistor N2; the source of the second P-type transistor P2 is electrically connected to the power supply terminal VDD, and the drain of the second P-type transistor P2 is connected to the second N-type transistor. The drain of the P-type transistor N2 is electrically connected to the second storage node QB, the source of the second N-type transistor N2 is grounded (electrically connected to the ground terminal GND), the gate of the second P-type transistor P2 and the second N-type transistor N2 The gate of is electrically connected to the first storage node Q.

Referring to FIG. 1, the storage element further includes a third N-type transistor N3 and a fourth N-type transistor N4; the source of the third N-type transistor N3 is electrically connected to the first storage node, the drain is connected to the bit line BLB, and the gate electrically connected to the word line. The source of the fourth N-type transistor N4 is electrically connected to the second storage node, the drain is connected to the bit line BL, and the gate is electrically connected to the word line.

The P-type transistors and N-type transistors used in the above memory cells are metal-oxide-semiconductor field-effect transistors. Since metal-oxide-semiconductor field-effect transistors have a very high input impedance, they are convenient for direct coupling in the circuit, and are easy to make a large-scale integrated circuit, so the first inverter and the second inverter in the embodiment of the present invention The metal-oxide-semiconductor field-effect transistor is applied in the application, and it is easy to form an integrated circuit in the follow-up.

Based on this, in the related art, it is assumed that the data stored in the storage node in the first inverter is at a high level, and the data stored in the storage node in the second inverter is at a low level. At this time, the first P-type transistor P1 and the first N-type transistor N1 in the first inverter are respectively in the negative bias and positive bias states. If they are in this state for a long time, the first P-type transistor P1 and the first N-type transistor The first N-type transistor N1 is prone to BTI effect. Afterwards, if the SRAM storage unit performs restart operation, since the first P-type transistor P1 and the first N-type transistor N1 in the first inverter are compared with the second P-type transistor P2 and the second transistor in the second inverter The N-type transistor N2 is more difficult to turn on, then the power supply voltage first charges the storage node in the second inverter, and the storage node in the first inverter is discharged through the second transistor, forming a steady state, the first inverter The data stored in the storage node in the inverter and the storage node in the second inverter have a high probability of "0" and "1". Therefore, the SRAM storage unit has non-volatility due to the BTI aging effect, and the power-on data has a certain correlation with the previously stored data, and the security is greatly reduced.

Based on this, an embodiment of the present invention discloses an SRAM memory cell based on a back gate structure, which includes a first inverter and a second inverter coupled cross-coupled. The transistors in the first inverter and the second inverter are both back-gate transistors. The back gate of the transistor in the first inverter has a first connection mode, and the back gate of the transistor in the second inverter has a second connection mode. When the SRAM memory cell based on the back gate structure is powered on, the first inverter The transistors in the first inverter and the transistors in the second inverter have different threshold voltages.

It can be understood that, after the first inverter and the second inverter are cross-coupled, a first storage node and a second storage node are formed. In practical applications, when the SRAM storage unit is powered on, the threshold voltages of the transistors in the first inverter and the transistors in the second inverter are different, so that the transistors in the first inverter and the second inverter have different threshold voltages. The transistors in an inverter are turned on at different times. Based on this, the power-on potential of one of the two storage nodes in the SRAM memory unit tends to be “0”, and the power-on potential of the other storage node tends to be “1”. At this time, the two storage nodes in the SRAM storage unit have a fixed power-on potential, which solves the problem that when the SRAM storage unit stores fixed data for a long time, the two symmetrical transistors will have different degrees of BTI aging effect, resulting in a permanent threshold The voltage mismatch causes the technical problem that the SRAM storage unit has a certain probability of reading the power-on initial value opposite to the original stored value after power-on.

In some embodiments, the back gate of the transistor in the first inverter is electrically connected to the first potential end, and the back gate of the transistor in the second inverter is electrically connected to the second potential end; wherein, the first potential end The electric potential is different from the electric potential of the second electric potential terminal. It can be understood that the difference between the potential of the first potential terminal and the potential of the second potential terminal includes: the potential of the first potential terminal is greater than that of the second potential terminal, or the potential of the first potential terminal is lower than the potential of the second potential terminal.

When the potential of the first potential terminal is greater than that of the second potential terminal, the first potential terminal may be a power supply terminal, and the second potential terminal may be a ground terminal.

FIG. 2 shows a circuit structure diagram of the SRAM memory cell based on the back gate structure in the above case. Referring to FIG. 2 , the back gates of the P-type back-gate MOS transistor P1 and the N-type back-gate MOS transistor N1 in the first inverter are both electrically connected to the power supply terminal VDD. Both the back gates of the P-type back-gate MOS transistor P2 and the N-type back-gate MOS transistor N2 in the second inverter are electrically connected to the ground terminal GND.

It can be understood that for N-type MOS transistors and P-type MOS transistors with back gates, when a positive voltage is applied to the back gates, the threshold voltage of the N-type MOS transistors becomes smaller, and the threshold voltage of the P-type MOS transistors becomes larger.

Referring to Figure 2, when the back gates of the P1 transistor and the N1 transistor are connected to the power supply, the threshold voltage of the P1 transistor is greater than that of the P2 transistor, and the threshold voltage of the N1 transistor is smaller than that of the N2 transistor, so that when the SRAM memory cell based on the back gate structure is powered on, The P1 transistor is more difficult to turn on. The power supply first charges the storage node QB through the P2 transistor, making it the first to reach a high level and establish a balance. After power-on, the storage node Q is more inclined to "0", and the storage node QB is more inclined to "1". ".

When the potential of the first potential terminal is greater than the potential of the second potential terminal, and the SRAM memory cell based on the back gate structure is powered on, and the word line is at a high potential, the first potential terminal can be the word line terminal, and the second potential terminal can be the ground terminal . FIG. 3 shows a circuit structure diagram of the SRAM memory cell based on the back gate structure in the above case.

Referring to FIG. 3 , the back gates of the P-type back-gate MOS transistor P1 and the N-type back-gate MOS transistor N1 in the first inverter are both electrically connected to the word line WL. Both the back gates of the P-type back-gate MOS transistor P2 and the N-type back-gate MOS transistor N2 in the second inverter are electrically connected to the ground terminal GND. When the back gates of the P1 transistor and the N1 transistor are connected to the word line WL, the threshold voltage of the P1 transistor is greater than that of the P2 transistor, and the threshold voltage of the N1 transistor is smaller than that of the N2 transistor, so that when the SRAM memory cell based on the back gate structure is powered on, the P1 transistor It is more difficult to turn on. The power supply first charges the storage node QB through the P2 transistor, making it the first to reach a high level and establish a balance. After power-on, the storage node Q is more inclined to "0", and the storage node QB is more inclined to "1". Compared with connecting the back gates of the P1 transistor and the N1 transistor to the power supply, connecting the back gates of the P1 transistor and the N1 transistor to the word line WL can ensure that the back gate bias of the P1 transistor and the N1 transistor is only valid when the word line WL is activated. , to maintain the stability of the SRAM memory cell during the storage phase.

When the potential of the first potential terminal is lower than that of the second potential terminal, the first potential terminal may be a ground terminal, and the second potential terminal may be a power supply terminal.

FIG. 4 shows a circuit structure diagram of the SRAM memory cell based on the back gate structure in the above situation. Referring to FIG. 4 , the back gates of the P-type back-gate MOS transistor P1 and the N-type back-gate MOS transistor N1 in the first inverter are both electrically connected to the ground terminal GND. Both the back gates of the P-type back-gate MOS transistor P2 and the N-type back-gate MOS transistor N2 in the second inverter are electrically connected to the power supply terminal VDD.

It can be understood that for N-type MOS transistors and P-type MOS transistors with back gates, when a positive voltage is applied to the back gates, the threshold voltage of the N-type MOS transistors becomes smaller, and the threshold voltage of the P-type MOS transistors becomes larger.

Referring to Figure 4, when the back gates of the P1 transistor and the N1 transistor are connected to the ground terminal, the threshold voltage of the P1 transistor is smaller than that of the P2 transistor, and the threshold voltage of the N1 transistor is greater than that of the N2 transistor, so that when the SRAM memory cell based on the back gate structure is powered on , the P1 transistor is easier to turn on, the power supply first charges the storage node Q through the P1 transistor, making it the first to reach a high level and establish a balance, so that after power-on, the storage node Q is more inclined to "1", and the storage node QB is more inclined to "1". 0".

When the potential of the first potential terminal is lower than the potential of the second potential terminal, and the SRAM memory cell based on the back gate structure is powered on, and the word line is at a high potential, the first potential terminal can be a ground terminal, and the second potential terminal can be a word line terminal . FIG. 5 shows a circuit structure diagram of the SRAM memory cell based on the back gate structure in the above case.

Referring to FIG. 5 , the back gates of the P-type back-gate MOS transistor P1 and the N-type back-gate MOS transistor N1 in the first inverter are both electrically connected to the ground terminal GND. Both the back gates of the P-type back-gate MOS transistor P2 and the N-type back-gate MOS transistor N2 in the second inverter are electrically connected to the word line WL. When the back gates of the P2 transistor and the N2 transistor are connected to the word line WL, the threshold voltage of the P1 transistor is smaller than that of the P2 transistor, and the threshold voltage of the N1 transistor is greater than that of the N2 transistor, so that when the SRAM memory cell based on the back gate structure is powered on, the P1 transistor It is easier to turn on. The power supply first charges the storage node Q through the P1 transistor, making it the first to reach a high level and establish a balance. After power-on, the storage node Q is more inclined to "1", and the storage node QB is more inclined to "0". Compared with connecting the back gates of the P2 transistor and the N2 transistor to the power supply, connecting the back gates of the P2 transistor and the N2 transistor to the word line WL can ensure that the back gate bias of the P2 transistor and the N2 transistor is only valid when the word line WL is activated. , to maintain the stability of the SRAM memory cell during the storage phase.

FIG. 6 shows the read and write timing waveform diagram of the SRAM storage unit provided by the embodiment of the present invention. The write 1, read 1, write 0 and read 0 functions of the SRAM storage unit circuit of the present invention are all normal. The basic timing is the same as that of the traditional SRAM storage unit. When WL is high, BL is high, and BLB is low, the write 1 operation is performed, the level of Q point rises, and the write 1 is successful. When WL is high level, BL and BLB are both high level, the read operation is performed, the BLB line discharges through the QB point, the potential drops, and reading 1 is successful; when WL is high level, BLB is high level, and BL is low When the level is high, the write 0 operation is performed, the level of QB point rises, and the write 0 is successful; when WL is high, BL and BLB are both high, the read operation is performed, the BL line discharges through the Q point, the potential drops, and the read 0 success.

Under any of the above conditions, when the SRAM memory cell based on the back gate structure is powered on, the first storage node is biased towards '0' or '1', which is manifested as a mismatch in its static noise margin.

Fig. 7 shows a static noise tolerance mismatch diagram of a SRAM unit. Referring to Fig. 7, curves 1 to 4 are the input and output characteristic curves of one of the two inverters constituting the SRAM, wherein the horizontal line of the curve 3 The coordinates and the ordinate are respectively the output voltage and input voltage of one of the inverters in the SRAM storage unit in the prior art. The abscissa and ordinate of curve 4 are respectively the input voltage and output voltage of one of the inverters in the case of the SRAM memory unit in the prior art. The abscissa and ordinate of curve 1 are respectively the output voltage and input voltage of one inverter when the SRAM memory cell based on the back gate structure in the embodiment of the present invention is used. The abscissa and ordinate of curve 2 are respectively the input voltage and output voltage of one inverter when the SRAM memory cell based on the back gate structure in the embodiment of the present invention is used.

Referring to FIG. 7 , the ranges of the left and right graphs synthesized by curve 3 and curve 4 are the same, that is to say, in the prior art, when power is turned on, the power-on initial value of the inverter in the SRAM memory unit is 0 or 1 with equal probability.

Referring to FIG. 7 , the ranges of the left and right graphs synthesized by curve 1 and curve 2 are different. Specifically: the area of the figure on the left is smaller than the area of the figure on the right. Among them, the area of the left figure is used to represent the probability that the power-on initial value of the inverter in the SRAM storage unit is 0 when the power is turned on, and the area of the left figure is used to represent the inverter in the SRAM memory unit when the power is turned on. The probability that the power-on initial value of the phase device is 1. That is to say, in the SRAM memory cell based on the back gate structure, the probability of the power-on initial value of the inverter in the SRAM memory cell based on the back gate structure being 1 is greater than the probability of the power-on initial value. Based on this, the probability of using the SRAM memory cell based on the back gate structure provided by the embodiment of the present invention to power on the initial value '1' is obviously greater than the probability of powering on the initial value '0', so that it will be fixed at '0' with a high probability when powering on. 1', which can alleviate the data security threat caused by aging imprinting. Wherein, curves 1 and 2 in FIG. 7 correspond to the input-output characteristic curves of the SRAM memory cell based on the back gate structure in FIG. 4 and FIG. 5 .

Fig. 8 shows another kind of SRAM unit static noise tolerance mismatch diagram, with reference to Fig. 8, curve 5 to curve 8 are the input-output characteristic curves of one of them in the two inverters that constitute SRAM, wherein, curve 5 The abscissa and ordinate are respectively the output voltage and input voltage of one of the inverters in the SRAM memory cell in the prior art. The abscissa and ordinate of curve 6 are respectively the input voltage and output voltage of another inverter in the SRAM memory cell in the prior art. The abscissa and ordinate of curve 7 are respectively the output voltage and input voltage of one inverter when the SRAM memory cell based on the back gate structure in the embodiment of the present invention is used. The abscissa and ordinate of curve 8 are respectively the input voltage and output voltage of another inverter when the SRAM memory cell based on the back gate structure in the embodiment of the present invention is used.

Referring to Fig. 8, the ranges of the left and right graphs formed by curve 5 and curve 6 are the same, that is to say, in the SRAM storage unit of the prior art, when the power is turned on, the power-up of the inverter in the SRAM storage unit The initial value is 0 or 1 with equal probability.

Referring to FIG. 8 , the ranges of the left and right graphs synthesized by the curve 7 and the curve 8 are different. Specifically: the area of the figure on the left is greater than the area of the figure on the right. Among them, the area of the graph on the left is used to represent the probability that the initial power-on value of the inverter in the SRAM memory cell based on the back gate structure is 0 when the power is turned on, and the area of the graph on the right is used to represent the probability that the initial value of the inverter in the SRAM memory cell based on the back gate structure is 0 when the power is turned on. The probability that the power-on initial value of the inverter in the SRAM memory cell of the back gate structure is 1. That is to say, in the SRAM storage unit based on the back gate structure, at power-on, the probability of the power-on initial value of the inverter in the SRAM storage unit based on the back-gate structure being 1 is less than that of the power-on initial value being 0. probability. Based on this, the probability of using the SRAM storage unit based on the back gate structure provided by the embodiment of the present invention is obviously higher than the probability of the initial value of '0' when the power is turned on, so that it will be fixed to '1' with a high probability when powered on. 0', which can alleviate the data security threat caused by aging imprinting. Wherein, curves 7 and 8 in FIG. 8 correspond to the input-output characteristic curves of the SRAM memory cell based on the back gate structure in FIG. 2 and FIG. 3 .

It should be noted that the power-on initial value of the SRAM memory cell based on the back gate structure mentioned in the embodiment of the present invention refers to the power-on initial value of Q in the SRAM memory cell based on the back gate structure.

The embodiment of the present invention also discloses an SRAM memory, which includes the above-mentioned SRAM storage unit based on the back gate structure.

The SRAM memory has the same technical effect as that of the SRAM memory unit based on the back gate structure provided by the embodiment of the present invention, which will not be repeated here.

The invention also discloses a power-on method, which includes:

Connecting the back gate of the transistor in the first inverter by using the first connection method, and connecting the back gate of the transistor in the second inverter by using the second connection method;

Controlling the power-on of the SRAM memory cell based on the back gate structure, the threshold voltage of the transistor in the first inverter is greater than or lower than the threshold voltage of the transistor in the second inverter.

The power-on method provided by the embodiment of the present invention has the same technical effect as that of the SRAM storage unit provided by the embodiment of the present invention, and details are not described here.

Each embodiment in this specification is described in a progressive manner, the same and similar parts of each embodiment can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and for relevant parts, please refer to part of the description of the method embodiment.

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present invention, and should cover all Within the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims (7)

1. An SRAM memory cell based on a back gate structure is characterized by comprising a first inverter and a second inverter which are cross-coupled; the transistors in the first inverter and the second inverter are both back gate transistors;

the back gate of the transistor in the first inverter has a first connection mode, the back gate of the transistor in the second inverter has a second connection mode, and when the SRAM storage unit based on the back gate structure is powered on, the threshold voltage of the transistor in the first inverter is different from the threshold voltage of the transistor in the second inverter;

a back gate of the transistor in the first inverter is electrically connected to a first potential terminal, and a back gate of the transistor in the second inverter is electrically connected to a second potential terminal; wherein the first potential terminal and the second potential terminal have different potentials;

the first potential end is a high potential end, and the second potential end is a low potential end;

or, the first potential end is a low potential end, and the second potential end is a high potential end; the high potential end is a power supply end or a word line end, and the low potential end is a ground end.

2. The back-gate structure based SRAM memory cell of claim 1, wherein said first potential terminal is said power supply terminal and said second potential terminal is said ground terminal.

3. The back-gate structure based SRAM memory cell of claim 1, wherein when the back-gate structure based SRAM memory cell is powered on and the word line is at a high potential, the first potential terminal is the word line terminal, and the second potential terminal is the ground terminal.

4. The back-gate structure-based SRAM memory cell of claim 1, wherein the first potential terminal is the ground terminal and the second potential terminal is the power supply terminal.

5. The back-gate structure based SRAM memory cell of claim 1, wherein when the back-gate structure based SRAM memory cell is powered on and a word line is at a high potential, the first potential terminal is the ground terminal and the second potential terminal is the word line terminal.

6. An SRAM memory comprising the back gate structure based SRAM memory cell of any one of claims 1-5.

7. A power-up method applied to the back gate structure based SRAM memory cell according to any one of claims 1 to 5, the power-up method comprising:

connecting the back gate of the transistor in the first inverter by adopting a first connection mode, and connecting the back gate of the transistor in the second inverter by adopting a second connection mode;

controlling the SRAM storage unit based on the back gate structure to be powered on, wherein the threshold voltage of the transistor in the first inverter is larger than or smaller than the threshold voltage of the transistor in the second inverter.

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