CN112802510A - Asymmetric SRAM memory cell and SRAM memory - Google Patents
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Abstract
本发明公开一种非对称SRAM存储单元和SRAM存储器，属于半导体领域。以解决由于主从结构的引入增加了较多的晶体管和增加了较多的控制信号，会增大芯片面积，增加功耗的技术问题。包括存储元，存储元包括：第一反相器以及第二反相器；第一反相器和第二反相器交叉耦合后，形成有第一存储节点和第二存储节点；第一反相器包括第一P型晶体管和第一N型晶体管；第二反相器包括第二P型晶体管和第二N型晶体管；第一P型晶体管的尺寸参数与第二P型晶体管的尺寸参数不同；和/或，第一N型晶体管的尺寸参数与第二N型晶体管的尺寸参数不同；非对称SRAM存储单元在上电时，第一存储节点具有第一上电电位，第二存储节点具有与第一存储节点相反的第二上电电位。
The invention discloses an asymmetric SRAM storage unit and an SRAM memory, belonging to the field of semiconductors. In order to solve the technical problem of increasing the chip area and increasing the power consumption due to the introduction of the master-slave structure, more transistors and more control signals are added. It includes a storage element, and the storage element includes: a first inverter and a second inverter; after the first inverter and the second inverter are cross-coupled, a first storage node and a second storage node are formed; The inverter includes a first P-type transistor and a first N-type transistor; the second inverter includes a second P-type transistor and a second N-type transistor; the size parameters of the first P-type transistor and the size parameters of the second P-type transistor and/or, the size parameter of the first N-type transistor is different from that of the second N-type transistor; when the asymmetric SRAM memory cell is powered on, the first storage node has a first power-on potential, and the second storage node has a first power-on potential. has a second power-up potential opposite to the first storage node.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an asymmetric SRAM memory cell and an SRAM memory.
Background
An SRAM (static-Random-Access Memory) is a Memory having a static Access function, and can store data stored therein without a refresh circuit. When SRAM is used in a chip, the system-on-chip may power off the SRAM to prevent an attacker from stealing data when the system-on-chip detects unauthorized access. However, the SRAM has a problem of information remaining, and the information stored before the power failure can be partially restored by the method of aging stamp extraction. The aging imprint extraction means that when a certain memory cell stores fixed data for a long time, different degrees of BTI (Bias Temperature Instability) aging effect occur in two symmetrical transistors, and permanent threshold voltage mismatch is generated, so that a certain probability (about 10% -20%) of reading a power-on potential opposite to an original stored value after the SRAM cell is powered on is obtained.
At present, the stored data is continuously exchanged between two nodes through the SRAM unit with a master-slave structure so as to balance the aging problem and eliminate the mismatch of threshold voltage. However, due to the introduction of the master-slave structure, more transistors and more control signals are added, so that the chip area and the power consumption are increased.
Disclosure of Invention
Based on this, the present invention provides an asymmetric SRAM memory cell and an SRAM memory, so as to solve the technical problems that the chip area is increased and the power consumption is increased due to the introduction of a master-slave structure and the addition of more transistors and more control signals.
In a first aspect, the present invention provides an asymmetric SRAM memory cell, where the asymmetric SRAM memory cell includes a memory cell, and the memory cell includes: a first inverter and a second inverter coupled to each other. The parameters of the first inverter are different from the parameters of the second directioner. When the asymmetric SRAM storage unit is powered on, the first storage node has a first power-on potential, and the second storage node has a second power-on potential opposite to the first storage node.
Compared with the prior art, the memory cell in the asymmetric SRAM memory unit provided by the invention comprises the first inverter and the second inverter. After the first inverter and the second inverter are cross-coupled, a first storage node and a second storage node are formed. Since the parameters of the first inverter are different from the parameters of the second inverter in the present invention. Therefore, the driving capability of the first inverter is different from that of the second inverter in the present invention. At this time, when the asymmetric SRAM memory cell is powered on, the first storage node has a fixed first power-on potential due to a difference between the driving capability of the first inverter and the driving capability of the second inverter, and the second storage node has a fixed second power-on potential opposite to the first storage node. Therefore, the first storage node and the second storage node in the asymmetric SRAM storage unit provided by the invention have fixed power-on potentials, the data security of the asymmetric SRAM storage unit is improved, and the technical problem that when the SRAM unit stores fixed data for a long time in the prior art, two symmetrical transistors generate different degrees of BTI aging effect to generate permanent threshold voltage mismatch, so that the power-on potential opposite to the original storage value is read out with a certain probability after the unit is powered on is solved. Compared with the prior art, due to the introduction of a master-slave structure, the asymmetric SRAM storage unit provided by the invention does not increase control signals and transistors, and can reduce the chip area and power consumption.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 shows a schematic diagram of a prior art SRAM cell in a master-slave configuration;
FIG. 2 is a schematic diagram illustrating an asymmetric SRAM memory cell according to an embodiment of the present invention;
FIG. 3 is a static noise margin mismatch diagram for an asymmetric SRAM memory cell according to an embodiment of the present invention;
FIG. 4 is a static noise margin mismatch diagram for an asymmetric SRAM memory cell according to an embodiment of the present invention;
fig. 5 shows a read/write timing diagram of an asymmetric SRAM memory cell according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
Various schematic diagrams of embodiments of the invention are shown in the drawings, which are not drawn to scale. Wherein certain details are exaggerated and possibly omitted for clarity of understanding. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the following, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless otherwise specified.
In the present invention, unless expressly stated or limited otherwise, the term "coupled" is to be interpreted broadly, e.g., "coupled" may be fixedly coupled, detachably coupled, or integrally formed; may be directly connected or indirectly connected through an intermediate.
An SRAM (static-Random-Access Memory) is a Memory having a static Access function, and can store data stored therein without a refresh circuit. When SRAM is used in a chip, the system-on-chip may power off the SRAM to prevent an attacker from stealing data when the system-on-chip detects unauthorized access. However, the SRAM has a problem of information remaining, and the information stored before the power failure can be partially restored by the method of aging stamp extraction. The aging imprint extraction means that when a certain storage unit stores fixed data for a long time, two symmetrical transistors generate different degrees of BTI aging effect to generate permanent threshold voltage mismatch, so that a power-on potential opposite to an original storage value is read out with a certain probability (about 10% -20%) after the SRAM unit is powered on.
At present, the stored data is continuously exchanged between two nodes by adopting the SRAM unit with a master-slave structure so as to balance the aging problem and eliminate the mismatch of threshold voltage. Fig. 1 shows an SRAM cell of a master-slave architecture provided in the prior art. It can be seen that due to the introduction of the master-slave structure, the control signals ST _ CLK, MT _ CLK, and T _ RST are added, and a plurality of transistors are also added. Based on this, the SRAM cell in the master-slave structure in fig. 1 increases the chip area, thereby increasing the power consumption of the chip.
Based on this, referring to fig. 2, an embodiment of the invention discloses an asymmetric SRAM memory cell. An asymmetric SRAM memory cell includes a memory cell. The memory element includes: a first inverter 11 and a second inverter 12; the first inverter 11 and the second inverter 12 are cross-coupled to form a first storage node Q and a second storage node QB. The memory element is the base and core of the memory, and is used to store one bit of binary information 0 or 1.
In addition, the memory cell provided by the embodiment of the invention comprises a first inverter with different parameters from those of the second inverter. Therefore, the driving capability of the first inverter is different from that of the second inverter in the present invention. At this time, when the asymmetric SRAM memory cell is powered on, the first storage node has a fixed first power-on potential due to a difference between the driving capability of the first inverter and the driving capability of the second inverter, and the second storage node has a fixed second power-on potential opposite to the first storage node. Therefore, the first storage node and the second storage node in the asymmetric SRAM storage unit provided by the invention have fixed power-on potentials, the data security of the asymmetric SRAM storage unit is improved, and the technical problem that when the SRAM unit stores fixed data for a long time in the prior art, two symmetrical transistors generate different degrees of BTI aging effect to generate permanent threshold voltage mismatch, so that the power-on potential opposite to the original storage value is read out with a certain probability after the unit is powered on is solved. Compared with the prior art, due to the introduction of a master-slave structure, the asymmetric SRAM storage unit provided by the invention does not increase control signals and transistors, and can reduce the chip area and power consumption.
Illustratively, the memory cell provided by the embodiment of the invention is a six-pipe SRAM memory cell. The six-transistor SRAM memory cell is a flip-flop formed by cross-coupling two MOS (metal oxide semiconductor field effect transistor) transistor inverters, and one memory cell stores one-bit binary number. The six-transistor SRAM cell has two stable states, and the potentials of the first storage node and the second storage node of the six-transistor SRAM cell are always opposite to each other. For example, the potential of the first storage node represents 0, and the potential of the second storage node represents 1. For another example, if the potential of the first storage node represents 1, the potential of the second storage node represents 0.
Specifically, referring to fig. 2, the circuit structures of the first inverter 11 and the second inverter 12 are axisymmetric along the central axis of the memory cell.
Wherein the first inverter 11 includes a first P-type transistor P1 and a first N-type transistor N1; the source of the first P-type transistor P1 is electrically connected to the power source terminal VDD, the drain of the first P-type transistor P1 and the drain of the first N-type transistor N1 are electrically connected to the first storage node Q, the source of the first N-type transistor N1 is grounded (electrically connected to the ground terminal GND), and the gate of the first P-type transistor P1 and the gate of the first N-type transistor N1 are electrically connected to the second storage node QB.
The second inverter includes 12 second P-type transistors P2 and a second N-type transistor N2; the source of the second P-type transistor P2 is electrically connected to the power source terminal VDD, the drain of the second P-type transistor P2 and the drain of the second N-type transistor N2 are electrically connected to the second storage node QB, the source of the second N-type transistor N2 is grounded (electrically connected to the ground terminal GND), and the gate of the second P-type transistor P2 and the gate of the second N-type transistor N2 are electrically connected to the first storage node Q.
Referring to fig. 2, the memory cell further includes a third N-type transistor N3 and a fourth N-type transistor N4; the source of the third N-type transistor N3 is electrically connected to the first storage node, the drain is connected to the bit line BLB, and the gate is electrically connected to the word line. The source of the fourth N-type transistor N4 is electrically connected to the second storage node, the drain is connected to the bit line BL, and the gate is electrically connected to the word line.
The P-type transistor and the N-type transistor applied in the memory cell are both metal oxide semiconductor field effect transistors. Since the mosfet has a high input impedance, direct coupling is facilitated in the circuit, and a large-scale integrated circuit can be easily manufactured, the mosfet is applied to the first inverter and the second inverter in the embodiment of the present invention, and the integrated circuit can be easily formed in the subsequent process.
In the embodiment of the invention, the parameters of the first inverter are the size parameter of the first P-type transistor and the size parameter of the first N-type transistor. The parameters of the second inverter are the size parameter of the second P-type transistor and the size parameter of the second N-type transistor.
For example, the parameter of the first inverter may be different from the parameter of the second inverter: the size parameter of the first P-type transistor is different from that of the second P-type transistor; and/or the size parameter of the second N-type transistor is different from the size parameter of the second N-type transistor.
Based on the above, the size parameters of the first P-type transistor and the second P-type transistor are different, and/or the size parameters of the second N-type transistor and the second N-type transistor are different. Therefore, in the present invention, the driving capability of the first P-type transistor is different from that of the second P-type transistor, and the driving capability of the second N-type transistor is different from that of the second N-type transistor. At this time, when the asymmetric SRAM memory cell is powered on, the first storage node has a first power-on potential and the second storage node has a second power-on potential opposite to the first storage node due to the difference in driving capability of each transistor. Therefore, the first storage node and the second storage node in the asymmetric SRAM storage unit provided by the invention have fixed power-on potentials, the data safety of the SRAM unit structure is improved, and the technical problem that the power-on potentials opposite to the original storage values are read out with a certain probability after the unit is powered on due to the fact that the two symmetrical transistors generate different degrees of BTI aging effects and generate permanent threshold voltage mismatch when the SRAM unit stores fixed data for a long time is solved. Compared with the prior art, due to the introduction of a master-slave structure, the asymmetric SRAM storage unit provided by the invention does not increase control signals and transistors, and can reduce the chip area and power consumption.
Specifically, the dimension parameter is a channel length. Namely, the dimension parameter of the first P-type transistor is the channel length of the first P-type transistor. The dimension parameter of the second P-type transistor is the channel length of the first P-type transistor. The dimension parameter of the first N-type transistor is the channel length of the first N-type transistor. The second N-type transistor is the channel length of the second N-type transistor.
The size parameter of the first P-type transistor is different from the size parameter of the second P-type transistor, and/or the size parameter of the second N-type transistor is different from the size parameter of the second N-type transistor, which can be classified into the following cases:
1) the channel length of the first P-type transistor is greater than the channel length of the second P-type transistor, and the channel length of the first N-type transistor is equal to the channel length of the second N-type transistor. At this time, since the driving capability of the first P-type transistor is greater than that of the second P-type transistor, the driving capability of the first N-type transistor is equal to that of the second N-type transistor. Therefore, when the asymmetric SRAM storage unit is powered on, the power-on potential of the first storage node is represented as 1, and the second power-on potential of the first storage node is represented as 0.
2) The channel length of the first P-type transistor is smaller than that of the second P-type transistor, and the channel length of the first N-type transistor is equal to that of the second N-type transistor. At this time, since the driving capability of the first P-type transistor is smaller than that of the second P-type transistor, the driving capability of the first N-type transistor is equal to that of the second N-type transistor. Therefore, when the asymmetric SRAM storage unit is powered on, the power-on potential of the first storage node is represented as 0, and the second power-on potential of the first storage node is represented as 1.
3) The channel length of the first P-type transistor is larger than that of the second P-type transistor, and the channel length of the first N-type transistor is smaller than that of the second N-type transistor. At this time, the driving capability of the first P-type transistor is greater than that of the second P-type transistor, and the driving capability of the first N-type transistor is less than that of the second N-type transistor. Therefore, when the asymmetric SRAM memory cell is powered on, the power-on potential of the first storage node can be represented as 1 with a higher probability, and the second power-on potential of the first storage node can be represented as 0 with a higher probability.
4) The channel length of the first P-type transistor is smaller than that of the second P-type transistor, and the channel length of the first N-type transistor is larger than that of the second N-type transistor. At this time, the driving capability of the first P-type transistor is smaller than that of the second P-type transistor, and the driving capability of the first N-type transistor is larger than that of the second N-type transistor. Therefore, when the asymmetric SRAM memory cell is powered on, the power-on potential of the first storage node can be represented as 0 with a higher probability, and the second power-on potential of the first storage node can be represented as 1 with a higher probability.
5) The channel length of the first P-type transistor is equal to the channel length of the second P-type transistor, and the channel length of the first N-type transistor is greater than the channel length of the second N-type transistor. At this time, since the driving capability of the first P-type transistor is equal to that of the second P-type transistor, the driving capability of the first N-type transistor is greater than that of the second N-type transistor. Therefore, when the asymmetric SRAM storage unit is powered on, the power-on potential of the first storage node is represented as 0, and the second power-on potential of the first storage node is represented as 1.
6) The channel length of the first P-type transistor is equal to the channel length of the second P-type transistor, and the channel length of the first N-type transistor is smaller than the channel length of the second N-type transistor. At this time, since the driving capability of the first P-type transistor is equal to that of the second P-type transistor, the driving capability of the first N-type transistor is smaller than that of the second N-type transistor. Therefore, when the asymmetric SRAM storage unit is powered on, the power-on potential of the first storage node is represented as 1, and the second power-on potential of the first storage node is represented as 0.
Fig. 3 shows a static noise margin mismatch diagram of an asymmetric SRAM memory cell, and referring to fig. 3, curves 1-4 are input/output characteristic curves of one of two inverters in the SRAM memory cell, wherein the abscissa and ordinate of curve 2 are the output voltage and the input voltage of one inverter in the prior art symmetric SRAM cell structure, respectively. The abscissa and ordinate of curve 3 are the output voltage and the input voltage, respectively, of another inverter of a prior art symmetric SRAM memory cell structure. The abscissa and ordinate of curve 1 are the output voltage and the input voltage of one inverter respectively in the asymmetric SRAM memory cell in the embodiment of the present invention. The abscissa and ordinate of curve 4 are the output voltage and the input voltage of another inverter respectively when the asymmetric SRAM memory cell is implemented in the embodiment of the present invention.
It can be seen that the ranges of the left and right patterns enclosed by the curves 2 and 3 are the same, that is, in the prior art, in the symmetric SRAM memory cell, the probability that the power-on potential of the inverter in the symmetric SRAM memory cell is 0 or 1 is equal when the power is turned on.
The ranges of the left and right patterns enclosed by the curves 1 and 4 are different. The area of the left graph represents the probability that the power-on potential of the first storage node is approximately fixed to 1 or 0 when the SRAM cell structure is powered on. The area of the graph on the left represents the probability that the power-on potential of the second storage node is fixed to 1 or 0 with a high probability when the SRAM cell structure is powered on. Referring to fig. 3, the area of the left figure is larger than that of the right figure in the left and right figures enclosed by the curves 1 and 4. Therefore, the power-on potential of the first storage node is more likely to be 1, and the power-on potential of the second storage node is more likely to be 0. That is to say, since the SRAM memory cell provided in the embodiment of the present invention is an asymmetric SRAM memory cell, when the SRAM memory cell is powered on, the probability that the power-on potential of the first storage node in the asymmetric SRAM memory cell is 1 is greater than the probability that the power-on potential is 0. Based on this, the two storage nodes in the asymmetric SRAM storage unit provided by the embodiment of the invention have fixed power-on potentials, so that the threat of data security brought by aging imprinting can be relieved. Wherein curves 2 and 3 of fig. 3 correspond to the input-output characteristic curves of the two inverters of the asymmetric SRAM memory cell having the structures 1), 3), 6) described above.
Fig. 4 shows another SRAM cell static noise margin mismatch diagram, and referring to fig. 4, curves 5-8 are input-output characteristic curves of one of two inverters constituting an SRAM, wherein the abscissa and ordinate of the curve 5 are the output voltage and the input voltage of one of the inverters, respectively, of the SRAM cell structure in the related art. The abscissa and ordinate of curve 8 are the input voltage and the output voltage, respectively, of the prior art SRAM cell structure, the further inverter. The abscissa and ordinate of curve 6 are the output voltage and the input voltage, respectively, of the asymmetric SRAM memory cell in the embodiment of the present invention, in which one inverter is provided. The abscissa and ordinate of curve 7 are the output voltage and the input voltage of the asymmetric SRAM memory cell, the other inverter, respectively, in the embodiment of the present invention.
It can be seen that the ranges of the left and right patterns enclosed by the curves 5 and 8 are the same, that is, in the prior art, in the symmetric SRAM memory cell, the probability that the power-on potential of the inverter in the symmetric SRAM memory cell is 0 or 1 is equal when the power is turned on.
The ranges of the left and right patterns enclosed by the curves 6 and 7 are different. The area of the left graph represents the probability that the power-on potential of the first storage node is approximately fixed to 1 or 0 when the SRAM cell structure is powered on. The area of the graph on the left represents the probability that the power-on potential of the second storage node is fixed to 1 or 0 with a high probability when the SRAM cell structure is powered on. Referring to fig. 4, the area of the left figure is smaller than that of the right figure in the left and right figures enclosed by the curves 6 and 7. Therefore, the power-on potential of the first storage node is more likely to be 0, and the power-on potential of the second storage node is more likely to be 1. That is to say, since the SRAM memory cell provided in the embodiment of the present invention is an asymmetric SRAM memory cell, when the SRAM memory cell is powered on, the probability that the power-on potential of the first storage node in the asymmetric SRAM memory cell is represented as 0 is greater than the probability that the power-on potential is represented as 1. Based on the above, the two storage nodes of the asymmetric SRAM provided by the embodiment of the invention have fixed power-on potentials, so that the data security threat brought by aging imprinting can be relieved. Wherein curves 2 and 3 of fig. 4 correspond to the input-output characteristic curves of the two inverters of the asymmetric SRAM memory cell having the structures of 2), 4), 5) described above.
Referring to fig. 5, the basic timing sequence of the asymmetric SRAM memory cell provided in the embodiment of the present invention is the same as the timing sequence of the conventional SRAM cell structure, when the word line WL is at a high level, the bit line BL is at a high level, and the BLB is at a low level, the write 1 operation is performed, the Q-point level is raised, and the write 1 operation is successful; when the word line WL is at a high level, the bit lines BL and BLB are both at a high level, reading operation is carried out, the BLB line discharges through a QB point, the potential drops, and reading 1 succeeds; when the word line WL is at a high level, the BLB is at a high level, and the bit line BL is at a low level, 0 writing is carried out, the QB point level is raised, and 0 writing is successful; when the word line WL is at high level and the bit lines BL and BLB are both at high level, the read operation is performed, the bit line BL discharges through the point Q, the potential drops, and the read of 0 succeeds.
The embodiment of the invention also discloses an SRAM memory, and the SRAM memory has the same technical effects as the asymmetric SRAM memory unit provided by the embodiment of the invention, and the details are not repeated herein.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the apparatus embodiment, since it is substantially similar to the method embodiment, it is relatively simple to describe, and reference may be made to some descriptions of the method embodiment for relevant points.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070242497A1 (en) * | 2006-04-12 | 2007-10-18 | International Business Machines Corporation | Dynamic control of back gate bias in a FinFET SRAM cell |
| US20090003051A1 (en) * | 2007-06-29 | 2009-01-01 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor Memory Device and Semiconductor Device |
| US20090086528A1 (en) * | 2007-09-27 | 2009-04-02 | Micron Technology, Inc. | Back gated sram cell |
| US20140063920A1 (en) * | 2012-08-28 | 2014-03-06 | United States Government, As Represented By The Secretary Of The Navy | Static random access memory that initializes to pre-determined state |
| CN105552078A (en) * | 2014-10-22 | 2016-05-04 | 瑞萨电子株式会社 | Semiconductor device |
| CN106486156A (en) * | 2016-09-21 | 2017-03-08 | 宁波大学 | A kind of memory element based on FinFET |
-
2021
- 2021-01-27 CN CN202110114509.9A patent/CN112802510A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070242497A1 (en) * | 2006-04-12 | 2007-10-18 | International Business Machines Corporation | Dynamic control of back gate bias in a FinFET SRAM cell |
| US20090003051A1 (en) * | 2007-06-29 | 2009-01-01 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor Memory Device and Semiconductor Device |
| US20090086528A1 (en) * | 2007-09-27 | 2009-04-02 | Micron Technology, Inc. | Back gated sram cell |
| US20140063920A1 (en) * | 2012-08-28 | 2014-03-06 | United States Government, As Represented By The Secretary Of The Navy | Static random access memory that initializes to pre-determined state |
| CN105552078A (en) * | 2014-10-22 | 2016-05-04 | 瑞萨电子株式会社 | Semiconductor device |
| CN106486156A (en) * | 2016-09-21 | 2017-03-08 | 宁波大学 | A kind of memory element based on FinFET |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114142846A (en) * | 2021-12-01 | 2022-03-04 | 海光信息技术股份有限公司 | A kind of aging tracking circuit, electronic device and electronic equipment |
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