CN112953498B - A CMOS Hybrid SR Memristive Latch Circuit with Asynchronous Set-Reset - Google Patents

Abstract

The invention discloses a CMOS mixed type SR memristor latch circuit with asynchronous setting and resetting, which comprises two modules: the SR memristor latch module comprises an SR memristor latch module and a memristor asynchronous setting and resetting function module. The SR memristor module comprises a first MOS transistor T₁A second MOS transistor T₂And a third MOS transistor T₃And a fourth MOS transistor T₄A fifth MOS transistor T₅Sixth MOS transistor T₆First memristor M₁A first inverter N₁And a second inverter N₂And a first resistor R₁(ii) a The memristor asynchronous setting and resetting functional module comprises a second memristor M₂The third memristor M₃The fourth memristor M₄The fifth memristor M₅And a third inverter N₃(ii) a The SR memristor latch module is formed by mixing a memristor and a CMOS, and the circuit is nonvolatile. The memristor asynchronous setting and resetting functional module is formed by constructing an AND gate and an OR gate formed by memristors, and the number of components is reduced by utilizing a memristor logic gate circuit to maximally simplify the circuit structure.

Description

A CMOS Hybrid SR Memristive Latch Circuit with Asynchronous Set-Reset

technical field

The invention belongs to the technical field of circuit design, and relates to a fully functional SR memristive latch circuit, in particular to a CMOS hybrid SR memristive latch circuit with asynchronous reset reset, which realizes level triggering and has non- Volatile features and an asynchronous set-to-reset function.

Background technique

Memristors were first proposed in 1971 and have gained more and more attention as a new type of device. Memristors have the characteristics of non-volatility and hysteresis, which can be used in chaotic circuits, neural networks, digital logic circuits and other fields, especially memory circuits. The application has great advantages, and has also achieved a series of results, such as basic flip-flops for digital circuits. However, the current design of memristors in flip-flop circuits is mostly based on traditional memory circuits. Although memristors are used, the number of devices in the entire circuit has not been greatly reduced. Memristors can make the circuit structure Simpler characteristics are not reflected, and problems such as excessive power consumption caused by circuit complexity still exist. Therefore, the present invention makes full use of the characteristics of memristors, combines with CMOS transistors, and adopts a new structure to design a hybrid memristive memory circuit. , to expand the application of memristors in memory circuits, and guide the way for the design of memristors in digital logic circuits.

SUMMARY OF THE INVENTION

In view of the problems existing in the current technology and research cost, the present invention provides a CMOS hybrid SR memristive latch circuit with asynchronous set reset, which is composed of CMOS and memristor, wherein the memristor adopts Biolek threshold value The memristor model can be designed with key parameters such as the maximum resistance value R _off , the minimum resistance value R _on , the parameter β (used to control the resistance change rate of the memristor model), and the threshold voltage V _t . Make direct adjustments.

The technical scheme adopted by the present invention to solve the technical problem is as follows:

A CMOS hybrid SR memristive latch circuit with asynchronous set and reset includes an SR memristive latch module and a memristive asynchronous set and reset function module. The SR memristive latch module includes a first MOS transistor T ₁ , a second MOS transistor T ₂ , a third MOS transistor T ₃ , a fourth MOS transistor T ₄ , a fifth MOS transistor T ₅ , and a sixth MOS transistor T _6. A first memristor M ₁ , a first inverter N ₁ and a second N ₂ , and a first resistor R ₁ ; the memristor asynchronous reset function module includes a second memristor M ₂ , a third memristor M ₃ , the fourth memristor M ₄ , the fifth memristor M ₅ and the third inverter N ₃ , wherein T ₁ , T ₂ , T ₃ , T ₄ and T ₆ are NMOS transistors, and T ₅ is PMOS transistors, M ₁ , M ₂ , M ₃ , M ₄ , and M ₅ are all Biolek threshold memristor models. In the SR memristive latch module, the gates of the first MOS transistor T ₁ , the third MOS transistor T ₃ , the fifth MOS transistor T ₅ , and the sixth MOS transistor T ₆ are connected to the control terminal of the SR memristive latch module CP; the drain of the _first MOS transistor T1 is connected to the input terminal S, the source of the _first MOS transistor T1 is connected to the gate of the _second MOS transistor T2 _; the drain _of the second MOS transistor T2 is connected to the DC voltage V1 , the source of the _second MOS transistor T2 is connected to the drain of the _fourth MOS transistor T4, the negative end of the first memristor M1, _one end of the _first resistor R1, and the input end of the _first inverter N1 And the output end of the second inverter _N2 ; the drain of the _third MOS transistor T3 is connected to the input end R, the source of the _third MOS transistor T3 is connected to the gate of the _fourth MOS transistor T4; the fourth MOS transistor _The source of T4 is connected to the ground terminal _; the source of the _fifth MOS transistor T5 is connected to the DC voltage V2, and the drain of the _fifth MOS transistor T5 is connected to the positive terminal of the _first memristor M1 and the sixth MOS transistor The source of _T6 ; the drain of the _sixth MOS transistor T6 is connected to the output end of the _first inverter N1 and the input end of the second inverter _{N2 ;} the output end of the second inverter N2 is used as SR The output terminal Q1 _of the memristive latch module is connected to the subsequent circuit. In the memristor asynchronous reset function module, the negative terminal of the second memristor M ₂ is connected to the output terminal Q ₁ (the output terminal of the second inverter N ₂ ) of the SR memristive latch module, and the second memristor M 2 The positive terminal of the device _M2 is connected to the positive terminal of the _third memristor M3 and the positive terminal of the _fourth memristor M4; the negative terminal of the _third memristor M3 is connected to the asynchronous set terminal SET; the fifth memristor The positive terminal of the device M5 is connected to the output terminal of the _third inverter N3, and the negative terminal of the _fifth memristor _M5 is connected to the negative terminal of the _fourth memristor M4 as the output terminal Q of the whole circuit; _The input terminal of the phase device N3 is connected to the asynchronous reset terminal RESET.

Further, the voltages V ₁ and V ₂ are DC voltages, the value of the DC voltage V ₁ is the same as the high level value of the input terminals S and R of the SR latch, and the value of the DC voltage V ₂ is slightly smaller than the value of V ₁ .

Further, the resistance value of the first resistor R ₁ needs to satisfy: R _on <<R ₁ <<R _off (R _on is the low resistance value of the memristor M ₁ , and R _off is the high resistance value of the memristor M ₁ value).

Furthermore, the input terminals S and R of the SR latch and the asynchronous set terminal SET and the asynchronous reset terminal RESET cannot be at a high level at the same time, and the above ports are all active at a high level in the circuit.

Further, the second memristor M ₂ and the third memristor M ₃ form a memristor OR gate, the fourth memristor M ₄ and the fifth memristor M ₅ form a memristive AND gate, and M ₁ and M _2. The initial resistance values of M ₃ , M ₄ and M ₅ are set between the minimum resistance value R _on and the maximum resistance value R _off , and the subsequent resistance values are converted according to the voltage applied across the memristor.

Further, the function of the sixth MOS transistor T ₆ is that when CP is logic 1, it will affect the voltage across the memristor, so that the resistance value of the memristor changes. When CP is logic 0, the sixth MOS transistor T ₆ off, has no effect on the memristor state.

Further, the advantage of the invention is that the circuit expands the application of the memristor in the digital logic circuit, adopts a circuit structure that is completely different from the traditional SR latch, has a simple structure, requires fewer components, and compares For the same type of memristor-based digital logic circuit design, the present invention uses the memristor logic gate circuit to add additional logic functions (asynchronous set, reset) to it on the basis of realizing the basic functions, further expanding the application scenarios of the invention , to guide the way for subsequent hardware design.

Compared with the prior art, the present invention proposes a CMOS hybrid SR memristive latch with asynchronous reset reset. The design idea is to combine a level SR memristive latch module and a memristive asynchronous latch. The set-reset module constitutes an SR memristive latch circuit. The SR memristive latch module is composed of a mixture of memristor and CMOS, and the circuit is non-volatile, so that the circuit has the function of power-off storage. The memristive asynchronous reset module is composed of an AND gate, an OR gate and an inverter composed of a memristor. The circuit structure is simple. This module enables the SR memristive latch to have the functions of asynchronous set and reset. The present invention adopts the Biolek threshold memristor model, and uses the threshold memristor and CMOS to realize a hybrid SR memristor latch with an asynchronous reset function. The circuit is non-volatile and has asynchronous set and reset. reset function. Different from the existing similar designs, the invention has the advantages that the circuit structure is greatly simplified, can be applied to other circuits, and has an additional asynchronous reset function on the basis of realizing the basic function.

Description of drawings

FIG. 1 is a block diagram of the circuit structure of the present invention.

Fig. 2 is the circuit symbol of the memristor used in the present invention.

FIG. 3 is a current-voltage curve diagram of a threshold-type memristor model adopted in the present invention.

FIG. 4 is a specific circuit structure diagram of the present invention.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described below with reference to the accompanying drawings and examples of the invention.

Figure 1 is a block diagram of the circuit structure of the present invention. The entire circuit includes an SR memristive latch module and a memristive asynchronous reset module. The SR memristive latch module is composed of a mixture of memristors and CMOS transistors. The circuit structure is simple and the device Compared with the traditional SR latch, the number of pieces is greatly reduced and the function is complete. The memristor asynchronous set and reset module is composed of an AND gate and an OR gate composed of a memristor to realize the asynchronous set and reset functions of the circuit. The entire circuit uses a small number of devices, is fully functional, and is non-volatile

FIG. 2 is a circuit symbol of the present invention using the threshold-type memristor model proposed by Biolek. It is assumed that one end of a black line segment is a negative end and the other end is a positive end. Figure 3 shows the current-voltage waveform of the Biolek threshold memristor under the addition of a sinusoidal excitation signal. As can be seen from Figure 3, the memristor model has hysteresis characteristics and threshold characteristics, and each has a threshold value under positive and negative voltages: +V _t and -V _t . When the forward excitation voltage applied to the memristor is greater than the forward threshold +V _t , the memristor switches to high resistance; when the reverse excitation voltage is greater than the negative threshold -V _t , the memristor switches to low resistance, and After the above changes, if the voltage does not change or the variation range is smaller than the threshold voltage, the memristor will maintain the previous resistance value until the excitation voltage difference between the two ends of the memristor is greater than the threshold value. In the present invention, the SR memristor latches The memristor in the memory module utilizes the properties described above to achieve non-volatile properties.

FIG. 4 is a specific circuit diagram of the CMOS hybrid SR memristive latch with asynchronous reset function of the present invention, wherein V ₁ and V ₂ are DC working power supplies. As shown in FIG. 4 , the hybrid SR memristor latch includes a first memristor M ₁ , a second memristor M ₂ , a third memristor M ₃ , a fourth memristor M ₄ , and a fifth memristor M 4 . Memristor M ₅ ; 5 NMOS transistors: first MOS transistor T ₁ , second MOS transistor T ₂ , third MOS transistor T ₃ , fourth MOS transistor T ₄ , sixth MOS transistor T ₆ ; 1 PMOS transistor : the fifth MOS transistor T ₅ ; M ₁ , M ₂ , M ₃ , M ₄ , and M ₅ are all Biolek threshold memristors. The gates of the first MOS transistor T ₁ , the third MOS transistor T ₃ , the fifth MOS transistor T ₅ , and the sixth MOS transistor T ₆ are connected to the control terminal CP, and CP is the control terminal of the entire circuit; the input terminal S is connected to the first MOS transistor _The drain of the transistor T1 is connected, the source of the _first MOS transistor T1 is connected to the gate of the _second MOS transistor T2 _; the drain _of the _second MOS transistor T2 is connected to the DC voltage V1, and the The source is connected to the drain of the _fourth MOS transistor T4, the negative end of the first memristor M1, _one end of the _first resistor R1, the input end of the _first inverter N1 and the second inverter _N2 The input end R is connected to the drain of the _third MOS transistor T3, the source of the _third MOS transistor T3 is connected to the gate of the _fourth MOS transistor T4 _; the source of the fourth MOS transistor T4 is connected to ground _; the source of the _fifth MOS transistor T5 is connected to the DC voltage V2, the drain of the _fifth MOS transistor T5 is connected to the positive end of the _first memristor M1 and the source of the _sixth MOS transistor T6; The drain of the _six MOS transistor T6 is connected to the output end of the _first inverter N1 and the input end of the second inverter _N2 ; the negative end of the second memristor _M2 is connected to the output end of the second inverter _N2 Output terminal, the positive terminal of the second memristor _M2 is connected to the positive terminal of the _third memristor M3 and the positive terminal of the _fourth memristor M4; the negative terminal of the _third memristor M3 is connected to the asynchronous set Terminal SET, the positive terminal of the _fifth memristor M5 is connected to the output terminal of the _third inverter N3, the negative terminal of the _fifth memristor M5 is connected to the negative terminal of the _fourth memristor M4, and the output is as The output end Q of the whole circuit; the asynchronous reset end RESET of the whole circuit is connected with the input end of the _third inverter N3. Combined with the circuit structure, the working principle of the SR memristive latch of the present invention is analyzed:

1. When the asynchronous reset terminal SET and RESET are both low level, that is, logic 0, and CP is high level:

(1) If the SR latch S=1 and R=0, CP=1 makes the first MOS transistor T ₁ , the second MOS transistor T ₂ , the third MOS transistor T ₃ , and the sixth MOS transistor T ₆ conduct , the fourth MOS transistor T ₄ and the fifth MOS transistor T ₅ are turned off, and the DC voltage V ₁ is applied to the negative end of the first memristor M ₁ and the input end of the first inverter N ₁ through the second MOS transistor T ₂ , the negative terminal of the first memristor M ₁ is at a high level and the size is approximately V ₁ , the voltage is converted to a low level through the first inverter N ₁ , and is added to the first level through the sixth MOS transistor T _{6 The} positive terminal of the memristor M1, due to the characteristics of the threshold-type memristor, the voltage difference between the negative terminal and the positive terminal is greater than the absolute value of the threshold, resulting in a change in the resistance value of the _first memristor M1, from the initial The resistance value becomes a low resistance value R _on and maintains the current resistance value, the high level of the input terminal of the first inverter N ₁ is input to the output terminal Q ₁ through the first inverter N ₁ and the second inverter N ₂ , At this time, the output of the SR memristive latch module Q ₁ =1. The second memristor M ₂ and the third memristor M ₃ form a memristor OR gate, and the fourth memristor M ₄ and the fifth memristor M ₅ form a memristive AND gate. logic 0, so the final output

(2) When S=0 and R=1, CP=1 makes the first MOS transistor T ₁ , the third MOS transistor T ₃ , the fourth MOS transistor T ₄ , and the sixth MOS transistor T ₆ conduct, and the second MOS transistor T 1 is turned on. The transistor T ₂ and the fifth MOS transistor T ₅ are turned off. Since the _second MOS transistor T2 is turned off and the _fourth MOS transistor T4 is turned on, the negative terminal of the _first memristor M1 and the input terminal of the _first inverter N1 are grounded through the _fourth MOS transistor T4. The terminal is a low level, and this level is converted to a high level under the action of the _first inverter N1 and is added to the positive terminal of the _first memristor M1 through the _sixth MOS transistor T6. At this time, the memristor The resistance value changes, becomes a high resistance value R _off and maintains the current resistance value, the low level of the input terminal of the first inverter N ₁ is input to Q ₁ through the first inverter N ₁ and the second inverter N ₂ At this time, the output Q ₁ = 0 of the SR memristive latch module, and because the asynchronous reset terminal SET/RESET is both logic 0, the final output

(3) When S=0 and R=0, CP=1 makes the first MOS transistor T ₁ , the third MOS transistor T ₃ , and the sixth MOS transistor T ₆ conduct, and the second MOS transistor T ₂ and the fourth MOS transistor T 2 are turned on. The transistor T ₄ and the fifth MOS transistor T ₅ are turned off, because the second MOS transistor T ₂ and the fourth MOS transistor T ₄ are off and the input end of the first inverter N ₁ and the output end of the second inverter N ₂ Q1 is connected together to form _a latching loop, resulting in no change in the voltage of the negative terminal of the _first memristor M1 and the input terminal of the _first inverter N1, so the output terminal Q1 outputs the previous state, the _{first A} memristor M1 also changes the corresponding resistance value according to the latched state (if S and R change to S=0, the output of Q1 at the moment before R=0 is logic ₁ , then the output terminal Q1 outputs logic ₁ at this time. And the resistance value change of the first memristor M ₁ is the same as (1), and becomes R _on ; if the output at the moment before the change is logic 0, then the output is at this time. The output end Q ₁ outputs logic 0 and the first memristor M ₁ The change of resistance value is the same as (2), it becomes R _off ), because the asynchronous reset terminals are all logic 0, so the final output

The above three cases (1), (2) and (3) respectively realize the function of setting 1, setting 0, and holding the SR latch. It is different from other similar inventions in that: the memory and threshold characteristics of the memristor are used to store the corresponding resistance value, the circuit working steps are simplified, the power consumption is reduced, the output is stable, and when the system is powered off, the resistance stored in the memristor is stored. The value remains unchanged so as to have the ability to keep the power off.

2. When the asynchronous reset terminal SET/RESET is logic 0, and CP is low level:

(1) If CP changes from 1 to 0, the output terminal Q ₁ outputs a high level:

该电压通过第一反相器N₁及第二反相器N₂至输出端Q₁输出高电平，又由于异步置位复位端SET/RESET均为逻辑0，所以最终输出

CP=0 causes the first MOS transistor T ₁ , the second MOS transistor T ₂ , the third MOS transistor T ₃ , the fourth MOS transistor T ₄ , and the sixth MOS transistor T ₆ to be turned off, and the fifth MOS transistor T ₅ to be turned on. Since the voltage of V ₂ is slightly less than the value of V ₁ , and it is assumed that V ₂ is also slightly less than the threshold voltage of the memristor, the voltage of V ₂ cannot change the resistance value of the first memristor M ₁ at this time, and because the output at the previous moment The terminal Q ₁ outputs a high level, so that the negative terminal of the first memristor M ₁ is a high level, and the positive terminal is a low level, which satisfies the transition condition of the resistance value of the memristor, and the resistance value changes to R _on . At this time, according to the principle of voltage division The voltage at the negative terminal of the memristor is:

The voltage passes through the _first inverter N1 and the second inverter _N2 to the output terminal Q1 to output _a high level, and because the asynchronous reset terminal SET/RESET is both logic 0, the final output

(2) If CP changes from 1 to 0, the output terminal Q ₁ outputs a low level:

该电压通过第一反相器N₁及第二反相器N₂至输出端Q₁输出低电平，又由于异步置位复位端SET/RESET均为逻辑0，所以最终输出

CP=0 causes the first MOS transistor T ₁ , the second MOS transistor T ₂ , the third MOS transistor T ₃ , the fourth MOS transistor T ₄ , and the sixth MOS transistor T ₆ to be turned off, and the fifth MOS transistor T ₅ to be turned on. Since the voltage of V ₂ is slightly less than the value of V ₁ , and it is assumed that V ₂ is also slightly less than the threshold voltage of the memristor, the voltage of V ₂ cannot change the resistance value of the first memristor M ₁ at this time, and because the output at the previous moment The terminal Q1 outputs _a low level, so that the negative terminal of the _first memristor M1 is a low level, and the positive terminal is a high level, which satisfies the transition condition of the resistance value of the memristor, and the resistance value changes to R _off . At this time, according to the principle of voltage division The voltage at the negative terminal of the memristor is:

The voltage passes through the _first inverter N1 and the second inverter _N2 to the output terminal Q1 to output _a low level, and because the asynchronous reset terminal SET/RESET is both logic 0, the final output

The above two cases realize that when CP is logic 0, the output terminal maintains the corresponding state according to the previous output state. Using this method to maximize the simplification of the circuit structure, the working principle is not complicated, and it is easy to simulate and adjust

3. When the reset terminal SET is set asynchronously to logic 1 and RESET is logic 0:

上述情况实现了异步置1的功能。As long as SET=1, no matter what the value of the output Q ₁ of the SR latch module is, the output of the OR gate formed by the second memristor M ₂ and the third memristor M ₃ is logic 1. At this time, the output of the entire circuit is

The above situation realizes the function of asynchronously set to 1.

4. When the asynchronous reset terminal SET is logic 0 and RESET is logic 1:

上述情况实现了异步置0的功能。As long as RESET= ₁ , the AND gate formed by the _fourth memristor M4 and the non-memristor M5 is not affected by the previous circuit, and the output is logic 0, that is, the final output

The above situation realizes the function of asynchronous setting to 0.

In the present invention, the voltages V ₁ and V ₂ are DC voltages, and the magnitude of the DC voltage V ₁ is the maximum voltage of the input terminals S and R of the SR latch; the value of the DC voltage V ₂ is slightly smaller than the value of V ₁ .

In the present invention, the resistance value of the first resistor R ₁ needs to satisfy: R _on <<R ₁ <<R _off (R _on is the low resistance value of the memristor M ₁ , and R _off is the high resistance value of the memristor M ₁ resistance).

In the present invention, the set terminal S and reset terminal R and the asynchronous set terminal SET and the asynchronous reset terminal RESET cannot be high level at the same time, and the above ports are all active high level in the circuit.

In the present invention, the second memristor M ₂ and the third memristor M ₃ constitute a memristor OR gate, the fourth memristor M ₄ and the fifth memristor M ₅ constitute a memristor AND gate, and the memristor M 5 constitutes a memristor AND gate. The initial resistance values of M ₁ , M ₂ , M ₃ , M ₄ and M ₅ need to be set between the minimum resistance value R _on and the maximum resistance value R _off of the memristor. The resistance value thereafter changes according to the magnitude of the voltage difference across the memristor.

In the present invention, the function of the _sixth MOS transistor T6 is that when CP is logic 1, it will affect the voltage across the memristor, so that the resistance value of the memristor changes. When CP is logic 0, the sixth MOS The transistor _T6 is turned off and has no effect on the memristor state.

In the present invention, compared with other similar inventions, its advantages are:

①The structure is novel and simple, the required components are few and some problems such as high power consumption are solved;

② On the basis of the present invention, other digital logic circuits (edge triggers, counters, etc.) can be further designed;

③Under the premise of realizing basic logic functions, it can realize additional logic functions that traditional SR latches do not have (asynchronous set reset);

The CMOS hybrid SR memristive latch with asynchronous reset function provided by the invention has stable circuit performance, non-volatility, asynchronous set and reset functions, and good circuit simulation test effect. The actual sample can be produced according to the specific circuit diagram of the present invention.

Those skilled in the art can easily understand that the above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, substitutions and improvements made within the spirit and principles of the present invention, etc., All should be included in the protection scope of the present invention.

Claims (6)

1. a CMOS hybrid SR memristive latch circuit with asynchronous reset, is characterized in that, comprises SR memristive latch module and memristive asynchronous reset function module; Wherein, SR memristive latch The device module includes a first MOS transistor T ₁ , a second MOS transistor T ₂ , a third MOS transistor T ₃ , a fourth MOS transistor T ₄ , a fifth MOS transistor T ₅ , a sixth MOS transistor T ₆ , and a first memristor M ₁ , a first inverter N ₁ and a second inverter N ₂ and a first resistor R ₁ ; the memristor asynchronous reset function module includes a second memristor M ₂ , a third memristor M ₃ , The fourth memristor M ₄ , the fifth memristor M ₅ and the third inverter N ₃ , wherein T ₁ , T ₂ , T ₃ , T ₄ and T ₆ are NMOS transistors, T ₅ is a PMOS transistor, M ₁ , M ₂ , M ₃ , M ₄ , and M ₅ are all Biolek threshold memristor models; in the SR memristive latch module, the first MOS transistor T ₁ , the third MOS transistor T ₃ , and the fifth MOS transistor _The gates of T5 and the _sixth MOS transistor T6 are connected to the control terminal CP of the SR memristive latch module; the drain of the _first MOS transistor T1 is connected to the input terminal S, and the source of the _first MOS transistor T1 is connected to the first MOS transistor T1 The gate of the _second MOS transistor T2 _; the drain of the second MOS transistor T2 is connected to the DC voltage V1, the source _of the _second MOS transistor T2 is connected to the drain of the _fourth MOS transistor T4, and the first memristor M The negative end of ₁ , _one end of the first resistor R1, the input end of the _first inverter N1, and the output end of the second inverter _N2 ; the drain of the _third MOS transistor T3 is connected to the input end R, and the first The source of the _three MOS transistor T3 is connected to the gate of T4 _; the source of the _fourth MOS transistor T4 is connected to the ground _; the source of the _fifth MOS transistor T5 is connected to the DC voltage V2, and the _fifth MOS transistor T5 The drain of the _first memristor M1 is connected to the positive terminal of the first memristor M1 and the source of the _sixth MOS transistor T6 _; the drain of the sixth MOS transistor T6 is connected to the output terminal of the _first inverter N1 and the second inverter The input terminal of the inverter N ₂ ; the output terminal of the second inverter N ₂ is used as the output terminal Q ₁ of the SR memristive latch module, and is connected to the subsequent circuit; in the memristive asynchronous reset function module, the second memristive The negative terminal of the inverter M ₂ is connected to the output terminal Q ₁ of the SR memristive latch module, that is, the output terminal of the second inverter N ₂ , and the positive terminal of the second memristor M ₂ is connected to the third memristor M The positive terminal of ₃ and the positive terminal of the _fourth memristor M4 _; the negative terminal of the third memristor M3 is connected to the asynchronous set terminal SET; the positive terminal of the _fifth memristor M5 is connected to the third inverter N The output terminal of ₃ , the negative terminal of the _fifth memristor M5 is connected to the negative terminal of the _fourth memristor M4 as the output terminal Q of the whole circuit; the input terminal of the _third inverter N3 is connected to the asynchronous reset terminal RESET. 2 . The CMOS hybrid SR memristive latch circuit with asynchronous reset according to claim 1 , wherein the voltages V ₁ and V ₂ are DC voltages, and the value of the DC voltage V ₁ is latched with the SR. 3 . The high level values of the input terminals S and R are the same, and the value of the DC voltage V2 is slightly smaller _than the value _of V1. 3. The CMOS hybrid SR memristive latch circuit with asynchronous reset according to claim 1, wherein the resistance value of the first resistor R ₁ needs to satisfy: R _on <<R ₁ <<R _off , where R _on is the low resistance value of the memristor M ₁ , and R _off is the high resistance value of the memristor M ₁ . 4. The CMOS hybrid SR memristive latch circuit with asynchronous reset according to claim 1, characterized in that the input terminals S and R of the SR latch and the asynchronous reset terminal SET and the asynchronous reset terminal RESET cannot be high at the same time, and the above ports are all active high in the circuit. 5 . The CMOS hybrid SR memristive latch circuit with asynchronous reset according to claim 1 , wherein the second memristor M ₂ and the third memristor M ₃ form a memristive OR gate. 6 . , the fourth memristor M ₄ and the fifth memristor M ₅ form a memristive AND gate, and the initial resistance values of M ₁ , M ₂ , M ₃ , M ₄ and M ₅ are set at the minimum resistance value R _on and Between the maximum resistance value R _off . 6 . The CMOS hybrid SR memristive latch circuit with asynchronous reset according to claim 1 , wherein the function of the sixth MOS transistor T ₆ is to affect the memory when CP is logic 1. 7 . The voltage across the resistor changes the resistance value of the memristor. When CP is logic 0, the _sixth MOS transistor T6 is turned off, which has no effect on the state of the memristor.

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