CN112332813B - CMOS hybrid type edge memristor D trigger circuit with asynchronous setting and resetting - Google Patents

Abstract

The invention discloses a CMOS mixed edge memristor D trigger circuit with asynchronous setting and resetting, which has the characteristic of non-volatile and has an asynchronous setting and resetting function. The whole circuit comprises three modules: the device comprises a front-stage memristor D latch module, a rear-stage memristor D latch module and an asynchronous memristor set reset module. The front-stage memristor D latch module comprises a MOS tube T ₁ 、T ₂ 、T ₃ 、T ₄ And T ₅ Memristor M ₁ Resistance R ₁ 2 CMOS inverters N ₁ And N ₂ The method comprises the steps of carrying out a first treatment on the surface of the The later-stage memristor D latch module comprises a MOS tube T ₆ 、T ₇ 、T ₈ 、T ₉ And T ₁₀ Memristor M ₂ Resistor R ₂ 2 CMOS inverters N ₅ And N ₆ The method comprises the steps of carrying out a first treatment on the surface of the The asynchronous memristor setting and resetting module comprises a memristor M ₃ 、M ₄ 、M ₅ 、M ₆ 、M ₇ 、M ₈ And M ₉ And 2 inverters N ₇ And N ₈ The method comprises the steps of carrying out a first treatment on the surface of the There are also 2 CMOS inverters N for clock input ₃ And N ₄ . The circuit utilizes the Biolek threshold type memristor, the model has threshold characteristics and memory characteristics, and the whole circuit is simple in structure and high in response speed by utilizing the memristor model.

Description

A CMOS Hybrid Edge Memristor D Flip-Flop Circuit with Asynchronous Set-Reset

technical field

The invention belongs to the technical field of circuit design, and relates to a memristor D flip-flop circuit, in particular to a CMOS hybrid edge memristor D flip-flop circuit with asynchronous reset, which realizes rising edge triggering and has non-volatile features and an asynchronous set-reset function.

Background technique

The memristor was first proposed in 1971 and has been widely studied as a new type of device. Aiming at the characteristics of non-volatility and hysteresis of the memristor, the memristor is applied to the neural network, memory, digital logic circuit and other fields. The research has been relatively comprehensive. However, due to the difficulties in manufacturing and high cost of nanotechnology, memristors have not yet entered the market as a commercial product. At present, various equivalent circuit models and mathematical models of memristors are mainly used to design circuits. The model can make memristors work in high and low resistance states, and has characteristics similar to switches. It is very suitable for digital logic circuits, such as memristive logic operation units such as AND, OR, XOR, and memristive combinations such as adders and multipliers. Logic circuits, but there is still less research on memristive sequential logic circuits, especially flip-flop circuits.

Contents of the invention

Aiming at the problems existing in current technology and research cost, the present invention provides a CMOS hybrid edge memristor D flip-flop circuit with asynchronous reset, wherein the memristor adopts Biolek threshold type memristor, which can control Key parameters such as the maximum resistance value R _off , the minimum resistance value R _on , the parameter β (used to control the resistance change rate of the memristor model, generally 10 ¹³ ), and the threshold voltage V _t of the model are directly adjusted.

The technical solution adopted by the present invention to solve the technical problems is as follows:

A CMOS hybrid edge memristor D flip-flop circuit with an asynchronous set-reset comprises a front-stage memristive D-latch module, an asynchronous memristive set-reset module and a subsequent-stage memristive D-latch module. Among them, the front-stage memristor D latch module includes MOS transistors T ₁ , T ₂ , T ₃ , T ₄ and T ₅ , memristor M ₁ , resistor R ₁ and CMOS inverters N ₁ and N ₂ ; The stage memristor D latch module includes MOS transistors T ₆ , T ₇ , T ₈ , T ₉ and T ₁₀ , memristor M ₂ , resistor R ₂ and CMOS inverters N ₅ and N ₆ ; the asynchronous memristor Bit reset module includes memristors M ₃ , M ₄ , M ₅ , M ₆ , M ₇ , M ₈ and M ₉ and inverters N ₇ and N ₈ ; CMOS inverters N ₃ and N for clock input ₄ ; wherein MOS transistors _T2 , _T4 , _T5 , _T6 , _T8 and _T10 are NMOS transistors, _T1 , _T3 , _T7 and _T9 are PMOS transistors, _M1 , _M2 , _M3 , M ₄ , M ₅ , M ₆ , M ₇ , M ₈ and M ₉ are all Biolek threshold memristors. In the previous-stage memristive D-latch module, the gates of T ₁ , T ₂ , T ₃ , T ₄ and T ₅ are connected to the output terminal of inverter N ₃ and the input terminal of N ₄ as the previous-stage memory The clock input port of the resistive D latch module; the source of _T2 is used as the signal input terminal of the previous memristive D latch module, that is, the input terminal D of the entire edge memristive D flip-flop, and the drain of _T2 is connected The drains of _T1 and _T4 ; the source of _T1 is connected to DC voltage _V2 ; the source of _T4 is connected to one end of resistor _R1 , the negative end of memristor _M1 and the input end of inverter _N1 ; The source of T ₃ is connected to the DC voltage V ₁ , the drain is connected to the positive terminal of the memristor M ₁ and the source of T ₅ ; the drain of T ₅ is connected to the output of the inverter N ₁ and the output of the inverter N ₂ input terminal; the other end of the resistor R ₁ is connected to the ground; the output terminal of the inverter N ₂ is used as the output terminal Q ₁ of the previous-stage memristor D-latch module; in the subsequent-stage memristor D-latch module, T _6. The gates of T ₇ , T ₈ , T ₉ and T ₁₀ are connected to the output terminal of the inverter N ₄ as the clock input port of the memristive D latch module of the subsequent stage; the source of the MOS transistor T ₆ is used as the subsequent stage The signal input port of the memristive D-latch module is connected to the output terminal Q ₁ of the preceding memristive D-latch (the output terminal of the inverter N ₂ ), and the drain of T ₆ is connected to the drains of T ₇ and T ₈ ; The source of the MOS transistor _T7 is connected to the DC voltage _V3 ; the source of the MOS transistor _T8 is connected to one end of the resistor _R2 , the negative end of the memristor _M2 and the input end of the inverter _N5 ; the MOS transistor _T9 The source of the MOS transistor _T10 is connected to the positive terminal of the memristor _M2 and the source of the MOS transistor _T10 ; the drain of the MOS transistor _T10 is connected to the output terminal of the inverter _N5 and the inverter N5 ₆ ; the other end of the resistor R ₂ is connected to the ground; the output of the inverter N ₆ is used as the signal output terminal Q ₂ of the subsequent memristive D-latch module. The asynchronous memristor set reset module is used as an additional circuit of the D flip-flop, and its connection is as follows: the input terminal of the inverter _N7 is connected with the positive terminal of the memristor _M3 as the input terminal of the set signal S, and the _N7 The output end of N8 is connected to the positive end of memristor _M5 ; the input end of inverter _N8 is used as the input end of reset signal R, and the output end of _N8 is connected to the positive end of memristor _M6 and _M4 ; the memristor The positive terminal of M ₇ is connected to the output terminal Q ₂ (the output terminal of the inverter N ₆ ) of the subsequent memristor D latch module; the negative terminals of the memristors M ₃ and M ₄ are connected to the memristor M ₈ Negative terminal; the negative terminal of memristor _M5 , _M6 and _M6 is connected to the negative terminal of memristor _M9 ; the negative terminal of memristor _M8 and _M9 is connected as the final output of the entire edge memristor D flip-flop Terminal Q.

Furthermore, the resistance value of the resistor _R1 needs to be much larger than the minimum resistance value set by the memristor _M1 and much smaller than the maximum resistance value set; the resistance value of the resistor _R2 needs to be much larger than the memristor M ₂ The lowest resistance value set and far less than the highest resistance value set.

Furthermore, the voltages V ₁ , V ₂ , V ₃ and V ₄ are DC voltages, V ₂ and V ₃ are set to a high level, and the voltages of the DC voltages V ₁ and V ₄ are smaller than those set by the memristors M ₁ and M ₄ set the threshold voltage.

Furthermore, the set signal S and the reset signal R cannot be 1 at the same time.

Compared with the prior art, the present invention proposes a CMOS hybrid edge memristor D flip-flop with an asynchronous reset, and its design idea is to combine two memristor D latches composed of CMOS and memristor Memristors are cascaded, and an asynchronous set-reset circuit composed of memristors is added. The circuit structure is simple, the functions are complete, and the system integration is high. The front-stage memristor D-latch module and the subsequent-stage memristor D-latch module are composed of a mixture of memristor and CMOS, and the circuit is non-volatile. The asynchronous memristor set-reset module is constructed by an AND gate and an OR gate composed of memristors, and this module enables the D flip-flop to have asynchronous set and reset functions. The present invention adopts the Biolek threshold type memristor model, utilizes the threshold type memristor and CMOS to realize the hybrid edge memristor D flip-flop circuit with asynchronous set and reset has non-volatility, and has asynchronous set and reset Function.

Description of drawings

Fig. 1 is a block diagram of the circuit structure of the present invention.

Fig. 2 is a circuit symbol of the memristor used in the present invention.

Fig. 3 is a current-voltage curve diagram of a threshold-type memristor model used in the present invention.

Fig. 4 is a specific circuit structure diagram of the present invention.

Fig. 5 is a simulation waveform diagram of the present invention.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention will be further described below in conjunction with the accompanying drawings and examples of the invention.

Fig. 1 is a block diagram of the circuit structure of the present invention. In the present invention, the front-stage memristive D latch, the subsequent memristive D-latch and the memristive asynchronous reset circuit are each taken as a module, and these three modules are connected in sequence Construction of a CMOS hybrid edge memristive D flip-flop with asynchronous set-reset. As shown in Figure 1, the way to construct the edge memristive D flip-flop is to form the front-stage memristive D-latch module and the rear-stage D-latch module by cascading, and the present invention is also to make the entire D flip-flop With the addition of an asynchronous set-reset circuit composed entirely of memristors, the number of devices used in the entire D flip-flop is greatly reduced, and the circuit structure is simple, which can greatly increase the speed and reduce power consumption.

Fig. 2 is the circuit symbol of the threshold type memristor model proposed by Biolek in the present invention, and Fig. 3 is the current-voltage waveform of the memristor under the external sinusoidal excitation signal, wherein the relevant parameters of the memristor are set as: β = 10 ^13. R _off = 100kΩ, R _on = 800Ω, V _t = 4.5V; the parameters related to the external sinusoidal voltage excitation are set as: the amplitude is 6V, and the frequency is 100Hz. It can be seen from Fig. 2 that the memristor model has hysteresis characteristics and threshold characteristics, and each has a threshold value, +V _t and -V _t , under positive and negative voltages. When the positive excitation voltage applied to the memristor is greater than the positive threshold +V _t , the memristor will be in a high resistance state; when the reverse excitation voltage is greater than the negative threshold -V _t , the memristor will be transformed into a low resistance state, And after the above change, if the voltage remains unchanged or the variation range is smaller than the threshold voltage, the memristor will maintain the previous resistance state until the excitation voltage difference applied to both ends of the memristor is greater than the threshold value. In the present invention, both the memristor models in the front-stage memristive D-latch module and the subsequent-stage memristive D-latch module play the role of memory storage. The asynchronous memristor set reset module uses memristors to form AND gates and OR gates to realize asynchronous set and reset functions.

FIG. 4 is a specific circuit diagram of the present invention based on a CMOS hybrid edge memristive D flip-flop with asynchronous reset. The voltage parameters are set as: V ₂ =V ₃ =8V, V ₁ =V ₄ =3.4V; the memristor parameters are set as: M ₁ and M ₂ : β=10 ¹³ , R _off =100kΩ, R _on = 800Ω, V _t = 3.5V; M ₃ , M ₄ , M ₅ , M ₆ , M ₇ , M ₈ and M ₉ : β = 10 ¹³ , R _off = 100kΩ, R _on = 800Ω, V _t = 0.5V; Other related parameters are set as: R ₁ =R ₂ =10kΩ. As shown in Figure 3, the edge memristor D flip-flop includes nine memristors M ₁ , M ₂ , M ₃ , M ₄ , M ₅ , M ₆ , M ₇ , M ₈ and M ₉ fixed value resistor R ₁ , R ₂ (R _on <<R ₁ , R ₂ <<R _off , where R _on and R _off are the lowest resistance value and the highest resistance value set by the memristor respectively), MOS transistors T ₂ , T ₄ , T _5. T ₆ , T ₈ and T ₁₀ are NMOS transistors, T ₁ , T ₃ , T ₇ and T ₉ are PMOS transistors, M ₁ , M ₂ , M ₃ , M ₄ , M ₅ , M ₆ , M ₇ , Both M ₈ and M ₉ are Biolek threshold memristors. The gates of T ₁ , T ₂ , T ₃ , T ₄ and T ₅ are connected to the output terminal of inverter N ₃ and the input terminal of N ₄ ; the source of T ₂ is used as the input terminal D of the entire edge memristive D flip-flop , the drain of T ₂ is connected to the drains of T ₁ and T ₄ ; the source of T ₁ is connected to the DC voltage V ₂ ; the source of T ₄ is connected to one end of resistor R ₁ , the negative end of memristor M ₁ and the reverse phase The input terminal of the device _N1 ; the source of _T3 is connected to the DC voltage _V1 , the drain is connected to the positive terminal of the memristor _M1 and the source of _T5 ; the drain of _T5 is connected to the output terminal of the inverter _N1 and the input terminal of inverter _N2 ; the other end of resistor _R1 is connected to ground; the output terminal of inverter _N2 is connected to the source of MOS transistor _T6 ; _T6 , _T7 , _T8 , _T9 and _T10 The gate of the MOS transistor T6 is connected to the output terminal of the inverter _N4 ; the source of the MOS transistor _T6 is connected to the output terminal of the inverter _N2 , and the drain of _T6 is connected to the drains of _T7 and _T8 ; the drain of the MOS transistor _T7 The source is connected to the DC voltage _V3 ; the source of the MOS transistor _T8 is connected to one end of the resistor _R2 , the negative terminal of the memristor _M2 and the input terminal of the inverter _N5 ; the source of the MOS transistor _T9 is connected to the DC voltage V ₄ , the drain is connected to the positive terminal of the memristor _M2 and the source of the MOS transistor _T10 ; the drain of the MOS transistor _T10 is connected to the output terminal of the inverter _N5 and the input terminal of the inverter _N6 ; the resistor The other end of R ₂ is connected to the ground; the output end of the inverter N ₆ is connected to the positive end of the memristor M ₇ . The input terminal of the inverter _N7 is connected to the set signal S, and the output terminal is connected to the positive terminal of the memristor _M5 ; the input terminal of the inverter _N8 is connected to the reset terminal R, and the output terminal is connected to the memristors _M6 and _M4 The positive terminal of the memristor _M3 is connected to the set signal S; the positive terminal of the memristor _M7 is connected to the output terminal of the inverter _N6 ; the negative terminals of the memristor _M3 and _M4 are connected to the memory The negative terminal of resistor _M8 ; the negative terminal of memristor _M5 , _M6 and _M6 is connected to the negative terminal of memristor _M9 ; the negative terminal of memristor _M8 and _M9 is connected as the whole edge memristor The final output terminal Q of the D flip-flop;

The working principle of the hybrid edge memristive D flip-flop with asynchronous reset of the present invention will be explained in detail below with reference to the PSPICE simulation waveform shown in FIG. 5 . The input signal D, the clock input signal CLK, the set signal S and the reset signal R are all square waves. The working principle of the edge memristive D flip-flop of the present invention is: when CLK=0, MOS transistors T ₂ , T ₄ and T ₅ are in the on state, and MOS transistors T ₁ and T ₃ are in the off state, at this time the input signal D Output from the _Q1 terminal, due to the existence of the inverter _N1 , the voltage difference between the two ends of the memristor _M1 is greater than the threshold voltage of the memristor, and at this time, the memristor _M1 will store the corresponding state according to the state of the input signal D ( If D=1, then M ₁ is in a low-impedance state (R _on ); if D=0, the memristor is in a high-impedance state (R _off ), when CLK changes from 0 to 1, MOS transistors T ₂ and T ₄ and _T5 are in the off state, MOS transistors _T1 and _T3 are in the open state, and since the voltage _V1 is less than the threshold voltage set by the memristor, the previously stored data of the memristor _M1 can be read through _V1 ( If M ₁ is in a high-impedance state, read 0, and if M ₁ is in a low-impedance state, read 1), and then output from Q ₂ through inverters N ₁ and N ₂ . The above is the working principle of the front-stage memristor D-latch, and the working principle of the subsequent-stage memristor D-latch is the same as that of the previous stage. Cascading these two latches can form a rising-edge triggered D flip-flop. The principle is: when CLK=0, the input terminal of the previous-stage memristive D-latch turns on the memristor to store the current transition state. At this time, Q ₁ =D, the input terminal of the subsequent memristive D latch is closed, the MOS transistors T ₇ and T ₈ are opened, and the previously stored state is read out through the voltage V ₄ and output through the Q ₂ terminal. When the rising edge arrives, the input terminal of the memristive D-latch of the previous stage is closed (T ₂ , T ₄ and T ₅ are closed), and the input terminal of the subsequent memristive D-latch is open (T ₆ , T ₈ and T ₁₀ are open) , the state stored in _M1 is read from the voltage _V1 , and then input from the _Q1 terminal to the subsequent memristor D latch and output from the _Q2 terminal, that is, _Q2 =D. The working principle of the memristor asynchronous set-reset circuit is: memristors _M3 and _M4 form a two-input AND gate, memristors _M5 , _M6 and _M7 form a three-input AND gate, memristors _M8 and _M9 constitutes a two-input OR gate, so the logic output expression of the entire memristor asynchronous reset circuit is (S and R can not be 1 simultaneously), when S=1, R=0, the two-input AND gate output that is formed by memristor _M3 and _M4 is 1 (the negative terminal of _M3 and _M4 ), by Memristors M ₈ and M ₉ constitute a two-input OR gate and one end (the negative end of M ₈ ) is 1. At this time, no matter whether the rising edge arrives, the output Q=1, which plays the function of asynchronous setting; when S=0 , when R=1, the output of the two-input AND gate composed of memristors M ₃ and M ₄ is 0, and the output of the three-input AND gate composed of memristors M ₅ , M ₆ and M ₇ is 0. At this time, the memristor Devices _M8 and _M9 form a two-input OR gate, and both ends of the gate (the negative terminal of _M8 and the negative terminal of _M9 ) are simultaneously 0; at this time, no matter whether the rising edge comes or not, the output terminal Q=0 serves as an asynchronous reset function. In Figure 5, the set signal S is 1 within 0-6us, and the reset signal R is 1 within 12.5-14us. It can be seen from Figure 5 that the output terminal Q is always 1 during 0-6us without changing with the input signal and the impact of the rising edge; when the output terminal Q arrives at the rising edge of CLK at 6-12.5us, the output signal Q is consistent with the input signal D, which conforms to the definition of D flip-flop; at 12.5-14us, the output terminal Q is always 0, instead of Affected by the change of the input signal D and the arrival of the rising edge, the circuit has the function of setting and resetting asynchronously.

In the present invention, it should be noted that the resistance value of the resistor _R1 needs to be much larger than the minimum resistance value set by the memristor _M1 and far smaller than the set maximum resistance value; the resistance value of the resistor _R2 needs to be much larger The minimum resistance value set for the memristor _M2 is much smaller than the maximum resistance value set.

In the present invention, it should also be noted that the voltages V ₁ , V ₂ , V ₃ , V ₄ , V ₅ and V ₆ are DC voltages, the voltages V ₂ and V ₅ are high level, and the voltages V ₁ , V ₃ and _V4 is less than the threshold voltage set by the memristor.

In the present invention, it should be noted that the set signal S and the reset signal R cannot be 1 at the same time

The CMOS hybrid edge memristor D flip-flop with asynchronous setting and reset provided by the present invention has stable circuit performance and non-volatility, the circuit has asynchronous setting and resetting functions, and the circuit simulation test effect is good. The production of actual samples can be carried out according to the specific circuit diagram of the present invention.

Those skilled in the art can easily understand that the above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, substitutions and improvements made within the spirit and principles of the present invention, etc., All should be included in the protection scope of the present invention.

Claims (4)

1. A CMOS hybrid edge memristor D flip-flop circuit with an asynchronous reset, characterized in that the entire circuit includes a front-stage memristor D latch module, an asynchronous memristor reset module and a post-stage memristor D A latch module, wherein the pre-memristor D latch module includes MOS transistors T ₁ , T ₂ , T ₃ , T ₄ and T ₅ , a memristor M ₁ , a resistor R ₁ and a CMOS inverter N ₁ and N ₂ ; the subsequent memristive D latch module includes MOS transistors T ₆ , T ₇ , T ₈ , T ₉ and T ₁₀ , memristor M ₂ , resistor R ₂ and CMOS inverters N ₅ and N ₆ ; Asynchronous memristor set reset module includes memristors M ₃ , M ₄ , M ₅ , M ₆ , M ₇ , M ₈ and M ₉ and inverters N ₇ and N ₈ ; CMOS inversion for clock input Devices N ₃ and N ₄ ; where MOS transistors T ₂ , T ₄ , T ₅ , T ₆ , T ₈ and T ₁₀ are NMOS transistors, T ₁ , T ₃ , T ₇ and T ₉ are PMOS transistors, M ₁ , M ₂ , M ₃ , M ₄ , M ₅ , M ₆ , M ₇ , M ₈ and M ₉ are all Biolek threshold type memristors; in the previous stage memristive D-latch module, T ₁ , T ₂ , T _3. The gates of _T4 and _T5 are connected to the output terminal of inverter _N3 and the input terminal of _N4 as the clock input port of the previous-stage memristor D-latch module; the source of _T2 is used as the previous-stage memristor The signal input terminal of the D latch module is also the input terminal D of the entire edge memristive D flip-flop. The drain of _T2 is connected to the drains of _T1 and _T4 ; the source of _T1 is connected to the DC voltage _V2 ; T The source of _T3 is connected to one end of resistor _R1 , the negative end of memristor _M1 and the input end of inverter _N1 ; the source of _T3 is connected to DC voltage _V1 , and the drain is connected to the positive end of memristor _M1 terminal and the source of _T5 ; the drain of _T5 is connected to the output terminal of inverter _N1 and the input terminal of inverter _N2 ; the other end of resistor _R1 is connected to ground; the output terminal of inverter _N2 is used as The output terminal Q ₁ of the memristor D latch module of the previous stage; in the memristor D latch module of the subsequent stage, the gates of T ₆ , T ₇ , T ₈ , T ₉ and T ₁₀ are connected to the inverter N The output terminal of ₄ is used as the clock input port of the memristor D latch module of the subsequent stage; the source of the MOS transistor _T6 is used as the signal input port of the memristor D latch module of the latter stage and connected to the The output terminal _Q1 is the output terminal of the inverter _N2 , the drain of _T6 is connected to the drains of _T7 and _T8 ; the source of the MOS transistor _T7 is connected to the DC voltage _V3 ; the source of the MOS transistor _T8 Connect one end of the resistor _R2 , the negative end of the memristor _M2 and the input end of the inverter _N5 ; the source of the MOS transistor _T9 is connected to the DC voltage _V4 , and the drain is connected to the positive end of the memristor _M2 and The source of the MOS transistor _T10 ; the drain of the MOS transistor _T10 is connected to the output terminal of the inverter _N5 and the input terminal of the inverter _N6 ; the other end of the resistor _R2 is connected to the ground; the output of the inverter _N6 terminal as the signal output terminal _Q2 of the subsequent memristor D latch module; the connection of the asynchronous memristor reset module is as follows: the input terminal of the inverter _N7 is connected with the positive terminal of the memristor _M3 as The input terminal of the setting signal S, the output terminal of _N7 is connected to the positive terminal of the memristor _M5 ; the input terminal of the inverter _N8 is used as the input terminal of the reset signal R, and the output terminal of _N8 is connected to the memristor _M6 and the positive terminal of _M4 ; the positive terminal of memristor _M7 is connected to the output terminal _Q2 of the subsequent memristor D latch module, that is, the output terminal of inverter _N6 ; the positive terminal of memristor _M3 and _M4 The negative terminal is connected to the negative terminal of the memristor _M8 ; the negative terminal of the memristor _M5 , _M6 and _M6 is connected to the negative terminal of the memristor _M9 ; the negative terminal of the memristor _M8 and _M9 is connected As the final output terminal Q of the entire edge memristive D flip-flop. 2. The CMOS hybrid edge memristor D flip-flop circuit with asynchronous reset according to claim 1, wherein the resistance value of resistor _R1 needs to be far greater than the minimum resistance set by memristor _M1 value and far less than the set maximum resistance value; the resistance value of the resistor _R2 needs to be much greater than the set minimum resistance value of the memristor _M2 and far less than the set maximum resistance value. 3. The CMOS hybrid edge memristor D flip-flop circuit with asynchronous set reset according to claim 1, characterized in that, voltages V ₁ , V ₂ , V ₃ and V ₄ are DC voltages, and V ₂ and V ₃ is a high level, and the voltages of the DC voltages V ₁ and V ₄ are smaller than the threshold voltage set by the memristor. 4. The CMOS hybrid edge memristor D flip-flop circuit with asynchronous set and reset according to claim 1, the set terminal S and the reset terminal R cannot be 1 at the same time.