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CN112953420A - Dynamic operational amplifier circuit with input tube in linear region - Google Patents

Dynamic operational amplifier circuit with input tube in linear region Download PDF

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Publication number
CN112953420A
CN112953420A CN202110302325.5A CN202110302325A CN112953420A CN 112953420 A CN112953420 A CN 112953420A CN 202110302325 A CN202110302325 A CN 202110302325A CN 112953420 A CN112953420 A CN 112953420A
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switching device
tube
input
control module
switch control
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CN112953420B (en
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唐鹤
曹启富
赵瑞扬
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University of Electronic Science and Technology of China
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers

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Abstract

一种输入管处于线性区的动态运算放大器电路，属于模拟集成电路技术领域。本发明通过令输入管处于线性区，增大了动态运算放大器的输入范围；同时引入了cascode的管子来稳定输入管的漏端电压，使得处于线性区的输入管输入栅源电压到漏源电流有良好的线性关系，输入管跨导随输入、输出信号变化小，保证了动态运算放大器的增益精度；此外采用cascode的管子，减小了输出端反馈到输入端的回踢噪声。本发明分别给出了NMOS管作为输入管和PMOS管作为输入管时的动态运算放大器结构，适用范围更广。

Figure 202110302325

A dynamic operational amplifier circuit with an input tube in a linear region belongs to the technical field of analog integrated circuits. The invention increases the input range of the dynamic operational amplifier by making the input tube in the linear region; at the same time, the cascode tube is introduced to stabilize the drain voltage of the input tube, so that the input tube in the linear region inputs the gate-source voltage to the drain-source current It has a good linear relationship, and the transconductance of the input tube changes little with the input and output signals, which ensures the gain accuracy of the dynamic operational amplifier; in addition, the use of cascode tubes reduces the kickback noise from the output end to the input end. The present invention respectively provides the dynamic operational amplifier structure when the NMOS tube is used as the input tube and the PMOS tube is used as the input tube, and the scope of application is wider.

Figure 202110302325

Description

Dynamic operational amplifier circuit with input tube in linear region
Technical Field
The invention belongs to the technical field of analog integrated circuits, and relates to a dynamic operational amplifier structure with large input-output swing amplitude and high linearity of an input tube in a linear region, which can be applied to a pipeline-successive approximation-type analog-to-digital converter (P-SAR ADC).
Background
Analog-to-digital converters are a constant topic in analog circuit design. In a high-speed and high-precision application scenario, a pipeline-successive approximation architecture is a highly desirable analog-to-digital converter (ADC). The front end of the structure is a high-precision successive approximation-register analog-to-digital converter (SAR ADC) which is used for carrying out first quantization on an analog signal; the middle part is a dynamic operational amplifier which is used for amplifying the redundant analog signals obtained by the first quantization; the back end is a SAR ADC used for quantizing the amplified redundant analog signals again. The digital coding combination obtained by the two quantization steps obtains the digital signal corresponding to the analog signal of the input end. The gain precision of the dynamic operational amplifier directly affects the precision of the whole ADC, and the output swing amplitude of the dynamic operational amplifier can affect the quantization precision of the next-stage SAR ADC so as to indirectly affect the precision of the whole ADC.
Fig. 1 shows a conventional dynamic operational amplifier structure, and fig. 2 shows a corresponding timing diagram.
When the clock signal CLK is low, the dynamic operational amplifier is in a reset state, M5, M6, M7 are turned on, M1 is turned off to turn off M2, M3, M4, and the node V is connected to the power supplyP、VN、VOCMIs reset to the supply voltage VDD, node VOCMThe voltage is converted into SW signal through two inverters, the SW signal is high level, the SW signal controls the switches SW1 and SW2 to be closed (when the SW is high level, the SW1 and the SW2 are closed, and when the SW is low level, the SW1 and the SW2 are opened), the load capacitor CLUpper output node VOP、VONIs charged to the power supply voltage VDD.
When the clock signal CLK is high, the dynamic operational amplifier starts to work in an amplifying state, M5, M6 and M7 are disconnected, M1, M2, M3 and M4 are connected, SW1 and SW2 continue to be in a closing state of a reset stage, and the load capacitor C is connected with the load capacitor CLUpper output node VOP、VONThe voltage drops from the supply voltage VDD at different rates (depending on the input differential magnitude) until the sampling capacitor CSSampled output common mode level VOCMFalls to the inversion threshold voltage of the inverter, the SW signal changes to low level, the switches SW1 and SW2 are turned off, and the output node V is turned offOP、VONThe voltage is kept unchanged, M2 is disconnected, then M3 and M4 are cut off, and the output node VOP、VONThe maintained voltage difference is used as the output differential voltage of the amplifier. Output differential voltage divided by inputThe differential voltage is used to obtain the gain of the amplifier.
The gain of such an integrating dynamic operational amplifier can be expressed as
Figure BDA0002986755470000011
Wherein VOP、VONIs the output node voltage, Δ VIN＝VIP-VINIs an input differential signal, gmIs the transconductance of input transistors M3 and M4, ID0Is the common mode leakage current, i.e. the average of the currents flowing through M3 and M4, VDD is the supply voltage, VTHIs the inverter flip threshold voltage. Due to gm/ID0、VDD-VTHThe value of (c) is limited and thus the dynamic op amp gain for this architecture is small, typically only 4-5 times. The input swing of this architecture is large, since a large output swing is beneficial for the quantization of the next stage SAR ADC.
In the schematic diagram of the conventional dynamic operational amplifier circuit shown in fig. 1, since the input transistors M3 and M4 operate in the saturation region, the drain currents flowing through M3 and M4 are proportional to the square of the gate-source voltage, and only in the case of very small input differential signals, the drain current and the gate-source voltage of the input transistors can be approximately linear (i.e., transconductance g)mConstant). As the input difference increases, the linearity of the drain current and the gate-source voltage of the input tube is worse and worse (namely transconductance g)mLarge variations) resulting in increasingly less gain accuracy of the overall amplifier. As shown in FIG. 2, the output node V is just the difference between the linearity of the drain-terminal current and the gate-source voltage of the input tube in the structureOP、VONThe voltage drops in an arc, resulting in poor amplification accuracy of the dynamic operational amplifier. In addition, the change of the voltage at the output end is fed back to the input end through the grid-drain parasitic capacitance of the input tube, and the introduced kickback noise also causes the linearity to be poor. When the input swing of the dynamic operational amplifier with the traditional structure is 40mV, the effective digit is only 7 bits.
Disclosure of Invention
Aiming at the problem that the input tube in the traditional dynamic operational amplifier is in a saturation region, so that the linearity of the drain-end current and the gate-source voltage of the input tube is poorer and poorer along with the increase of the input difference, and the gain precision of the amplifier is low, the invention provides a dynamic operational amplifier structure, wherein the input tube is in a linear region, and a cascode tube is introduced to stabilize the drain-end voltage of the input tube, so that the drain-source voltage of the input tube in the linear region is constant, and the good linear relation between the input gate-source voltage and the drain-source current is realized, therefore, the transconductance of the input tube of the dynamic operational amplifier structure provided by the invention is small along with the change of input and output signals, and the gain precision is higher.
The input tube of the dynamic operational amplifier structure can be realized by an NMOS tube or a PMOS tube, and when the input tube of the dynamic operational amplifier structure is realized by the NMOS tube, the technical scheme of the invention is as follows:
a dynamic operational amplifier circuit with an input tube in a linear region comprises a first switch device, a second switch device, a third switch device, a fourth switch device, a fifth switch device, a sixth switch device, a seventh switch device, a first load capacitor, a second load capacitor, a first sampling capacitor, a second sampling capacitor, a switch control module, a first input tube and a second input tube, wherein the capacitance values of the first load capacitor and the second load capacitor are equal, the capacitance values of the first sampling capacitor and the second sampling capacitor are equal, the first input tube is a first NMOS tube, and the second input tube is a second NMOS tube;
the first connection end of the first switching device is used as a first differential output end of the dynamic operational amplifier circuit and is grounded after passing through the first load capacitor, and the second connection end of the first switching device is connected with the first connection end of the first sampling capacitor and is used as a first middle node;
the first connecting end of the second switching element is used as a second differential output end of the dynamic operational amplifier circuit and is grounded after passing through a second load capacitor, and the second connecting end of the second switching element is connected with the first connecting end of a second sampling capacitor and is used as a second intermediate node;
the second connecting end of the first sampling capacitor is connected with the second connecting end of the second sampling capacitor and the input end of the switch control module and is connected with the power supply voltage after passing through a third switch device;
a fourth switching device coupled between the first intermediate node and the supply voltage and a fifth switching device coupled between the second intermediate node and the supply voltage;
the first connecting end of the sixth switching device is connected with the first connecting end of the seventh switching device, and the second connecting end of the sixth switching device is grounded;
a second connecting end of the seventh switching device is connected with a source electrode of the first NMOS tube and a source electrode of the second NMOS tube, a grid electrode of the first NMOS tube is used as a first differential input end of the dynamic operational amplifier circuit, and a grid electrode of the second NMOS end is used as a second differential input end of the dynamic operational amplifier circuit;
the third switching device, the fourth switching device, the fifth switching device and the sixth switching device are controlled by a clock signal, and when the clock signal is in a first state, the third switching device, the fourth switching device and the fifth switching device are controlled to be switched on, and the sixth switching device is controlled to be switched off; when the clock signal is in a second state, the third switching device, the fourth switching device and the fifth switching device are controlled to be switched off, and the sixth switching device is controlled to be switched on;
the first switch device, the second switch device and the seventh switch device are controlled by an output signal of the switch control module, the switch control module is used for comparing a voltage value of an input end of the switch control module with a turnover threshold voltage, and when the voltage value of the input end of the switch control module is not lower than the turnover threshold voltage, the output signal of the switch control module controls the first switch device, the second switch device and the seventh switch device to be conducted; when the voltage value of the input end of the switch control module is lower than the overturning threshold voltage, the output signal of the switch control module controls the first switch device, the second switch device and the seventh switch device to be switched off;
the dynamic operational amplifier circuit further comprises a third NMOS tube and a fourth NMOS tube;
the grid electrode of the third NMOS tube is connected with bias voltage, the source electrode of the third NMOS tube is connected with the drain electrode of the first NMOS tube, and the drain electrode of the third NMOS tube is connected with the first intermediate node;
the grid electrode of the fourth NMOS tube is connected with the bias voltage, the source electrode of the fourth NMOS tube is connected with the drain electrode of the second NMOS tube, and the drain electrode of the fourth NMOS tube is connected with the second intermediate node;
the first NMOS tube and the second NMOS tube work in a linear region, and the third NMOS tube and the fourth NMOS tube work in a saturation region.
Specifically, the switch control module comprises a first inverter and a second inverter, wherein the input end of the first inverter is connected with the input end of the switch control module, and the output end of the first inverter is connected with the input end of the second inverter; and the output end of the second inverter outputs the output signal of the switch control module.
Specifically, the seventh switching device is a fifth NMOS transistor, a gate of the fifth NMOS transistor is connected to the output signal of the switch control module, a source thereof is used as the first connection terminal of the seventh switching device, and a drain thereof is used as the second connection terminal of the seventh switching device.
Specifically, the third switching device is a first PMOS transistor, the fourth switching device is a second PMOS transistor, the fifth switching device is a third PMOS transistor, and the sixth switching device is a sixth NMOS transistor;
the grid electrodes of the first PMOS tube, the second PMOS tube and the third PMOS tube are all connected with the clock signal, the source electrodes of the first PMOS tube, the second PMOS tube and the third PMOS tube are all connected with the power supply voltage, the drain electrode of the first PMOS tube is connected with the input end of the switch control module, the drain electrode of the second PMOS tube is connected with the first intermediate node, and the drain electrode of the third PMOS tube is connected with the second intermediate node;
the grid electrode of the sixth NMOS tube is connected with the clock signal, the drain electrode of the sixth NMOS tube is used as the first connecting end of the sixth switching device, and the source electrode of the sixth NMOS tube is used as the second connecting end of the sixth switching device.
When the input tube of the dynamic operational amplifier structure is realized by a PMOS tube, the technical scheme of the invention is as follows:
a dynamic operational amplifier circuit with an input tube in a linear region comprises a first switch device, a second switch device, a third switch device, a fourth switch device, a fifth switch device, a sixth switch device, a seventh switch device, a first load capacitor, a second load capacitor, a first sampling capacitor, a second sampling capacitor, a switch control module, a first input tube and a second input tube, wherein the capacitance values of the first load capacitor and the second load capacitor are equal, the capacitance values of the first sampling capacitor and the second sampling capacitor are equal, the first input tube is a fourth PMOS tube, and the second input tube is a fifth PMOS tube;
the first connection end of the first switching device is used as a first differential output end of the dynamic operational amplifier circuit and is grounded after passing through the first load capacitor, and the second connection end of the first switching device is connected with the first connection end of the first sampling capacitor and is used as a first middle node;
the first connecting end of the second switching element is used as a second differential output end of the dynamic operational amplifier circuit and is grounded after passing through a second load capacitor, and the second connecting end of the second switching element is connected with the first connecting end of a second sampling capacitor and is used as a second intermediate node;
the second connecting end of the first sampling capacitor is connected with the second connecting end of the second sampling capacitor and the input end of the switch control module and is grounded after passing through a third switch device;
a fourth switching device is connected between the first intermediate node and ground, and a fifth switching device is connected between the second intermediate node and ground;
the first connecting end of the sixth switching device is connected with the first connecting end of the seventh switching device, and the second connecting end of the sixth switching device is connected with power supply voltage;
a second connecting end of the seventh switching device is connected with a source electrode of a fourth PMOS tube and a source electrode of a fifth PMOS tube, a grid electrode of the fourth PMOS tube is used as a first differential input end of the dynamic operational amplifier circuit, and a grid electrode of a second PMOS end is used as a second differential input end of the dynamic operational amplifier circuit;
the third switching device, the fourth switching device, the fifth switching device and the sixth switching device are controlled by a clock signal, and when the clock signal is in a first state, the third switching device, the fourth switching device and the fifth switching device are controlled to be switched on, and the sixth switching device is controlled to be switched off; when the clock signal is in a second state, the third switching device, the fourth switching device and the fifth switching device are controlled to be switched off, and the sixth switching device is controlled to be switched on;
the first switch device, the second switch device and the seventh switch device are controlled by an output signal of the switch control module, the switch control module is used for comparing a voltage value of an input end of the switch control module with a turnover threshold voltage, and when the voltage value of the input end of the switch control module is not lower than the turnover threshold voltage, the output signal of the switch control module controls the first switch device, the second switch device and the seventh switch device to be conducted; when the voltage value of the input end of the switch control module is lower than the overturning threshold voltage, the output signal of the switch control module controls the first switch device, the second switch device and the seventh switch device to be switched off;
the dynamic operational amplifier circuit further comprises a sixth PMOS tube and a seventh PMOS tube;
the grid electrode of the sixth PMOS tube is connected with bias voltage, the source electrode of the sixth PMOS tube is connected with the drain electrode of the fourth PMOS tube, and the drain electrode of the sixth PMOS tube is connected with the first intermediate node;
the grid electrode of the seventh PMOS tube is connected with the bias voltage, the source electrode of the seventh PMOS tube is connected with the drain electrode of the fifth PMOS tube, and the drain electrode of the seventh PMOS tube is connected with the second intermediate node;
the fourth PMOS tube and the fifth PMOS tube work in a linear region, and the sixth PMOS tube and the seventh PMOS tube work in a saturation region.
Specifically, the switch control module comprises a first inverter and a second inverter, wherein the input end of the first inverter is connected with the input end of the switch control module, and the output end of the first inverter is connected with the input end of the second inverter; and the output end of the second inverter outputs the output signal of the switch control module.
Specifically, the seventh switching device is an eighth PMOS transistor, a gate of the eighth PMOS transistor is connected to the output signal of the switch control module, a source of the eighth PMOS transistor is used as the first connection end of the seventh switching device, and a drain of the eighth PMOS transistor is used as the second connection end of the seventh switching device.
Specifically, the third switching device is a seventh NMOS transistor, the fourth switching device is an eighth NMOS transistor, the fifth switching device is a ninth NMOS transistor, and the sixth switching device is a ninth PMOS transistor;
the grid electrodes of the seventh NMOS tube, the eighth NMOS tube and the ninth NMOS tube are all connected with the clock signal, the source electrodes of the seventh NMOS tube, the eighth NMOS tube and the ninth NMOS tube are all grounded, the drain electrode of the seventh NMOS tube is connected with the input end of the switch control module, the drain electrode of the eighth NMOS tube is connected with the first intermediate node, and the drain electrode of the ninth NMOS tube is connected with the second intermediate node;
the gate of the ninth PMOS transistor is connected to the clock signal, the drain of the ninth PMOS transistor is used as the first connection terminal of the sixth switching device, and the source of the ninth PMOS transistor is used as the second connection terminal of the sixth switching device.
The invention has the beneficial effects that: the dynamic operational amplifier provided by the invention obtains stable input transconductance, very small kickback noise and larger input and output swing amplitude through the cascode structure of the input tube in the linear region, and compared with the traditional dynamic operational amplifier, the dynamic operational amplifier provided by the invention has higher gain precision and larger input and output swing amplitude.
Drawings
The following description of various embodiments of the invention may be better understood with reference to the following drawings, which schematically illustrate major features of some embodiments of the invention. These figures and examples provide some embodiments of the invention in a non-limiting, non-exhaustive manner. For purposes of clarity, the same reference numbers will be used in different drawings to identify the same or similar elements or structures having the same function.
Fig. 1 is a circuit schematic of a conventional dynamic operational amplifier.
Fig. 2 is a timing diagram of a conventional dynamic operational amplifier.
Fig. 3 is a circuit diagram of a dynamic operational amplifier circuit with an input transistor in a linear region according to the present invention, when the input transistor is implemented by an NMOS transistor.
FIG. 4 is a timing diagram of a dynamic operational amplifier circuit with an input transistor in a linear region, when the input transistor is implemented by an NMOS transistor.
Fig. 5 is a result of FFT analysis of a conventional dynamic operational amplifier.
Fig. 6 is a FFT analysis result of a dynamic operational amplifier circuit with an input transistor in a linear region according to the present invention, when the input transistor is implemented by an NMOS transistor.
Fig. 7 is a circuit diagram of a dynamic operational amplifier circuit with an input transistor in a linear region according to the present invention, when the input transistor is implemented by a PMOS transistor.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in detail with reference to the accompanying drawings. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It is to be noted that, in the present invention, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The current is not well controlled because the drain-source voltage of a transistor operating in the linear region varies and directly affects the current. The transistor operating in the saturation region is generally used as an input transistor because the drain voltage variation of the transistor has little influence on the current and the current is easily controlled by the gate voltage. However, the linearity of the input tube in the saturation region is considered to be better when the input signal is small, but as the input signal increases, the gain accuracy of the amplifier is reduced when the input tube in the dynamic operational amplifier is in the saturation region. Therefore, the invention breaks through the traditional method that the input tube usually adopts a transistor working in a saturation region, provides that the input tube of the dynamic operational amplifier is in a linear region, and simultaneously introduces a cascode transistor to stabilize the drain-end voltage of the input tube, so that the input gate-source voltage to the drain-source current of the input tube in the linear region has a good linear relation, and the input range of the invention is greatly enlarged compared with the input range of the traditional structure under the same amplification precision.
As shown in fig. 3, the dynamic operational amplifier circuit with an NMOS input tube in a linear region includes a first switch device SW1, a second switch device SW2, a third switch device, a fourth switch device, a fifth switch device, a sixth switch device, a seventh switch device, a first load capacitor, a second load capacitor, a first sampling capacitor, a second sampling capacitor, a switch control module, a first input tube and a second input tube, wherein capacitance values of the first load capacitor and the second load capacitor are equal and are both CLThe capacitance values of the first sampling capacitor and the second sampling capacitor are equal and are both CSThe first input tube is a first NMOS tube MN1, and the second input tube is a second NMOS tube MN 2; the grid electrode of the first NMOS transistor MN1 is used as a first differential input end of the dynamic operational amplifier circuit, and the grid electrode of the second NMOS terminal is used as a second differential input end of the dynamic operational amplifier circuit; the first connection end of the first switching device SW1 is used as the first differential output end of the dynamic operational amplifier circuit and is grounded after passing through the first load capacitor, and the second connection end of the first switching device SW1 is connected with the first connection end of the first sampling capacitor and is used as the first middle node VP(ii) a The first connection end of the second switching device SW2 is used as the second differential output end of the dynamic operational amplifier circuit and is grounded after passing through the second load capacitor, and the second connection end is connected with the first connection end of the second sampling capacitor and is used as the second middle node VN(ii) a If the first differential input terminal of the dynamic operational amplifier circuit is a negative input terminal VINThe second differential input terminal of the dynamic operational amplifier circuit is a positive input terminal VIPThe first differential output terminal of the dynamic operational amplifier circuit is a positive output terminal VOPThe second differential output end of the dynamic operational amplifier circuit is a negative output end VON. Of course, the input tube structure of the dynamic operational amplifier is symmetrical, and the positive and negative input ends and the positive and negative output ends can be interchanged.
When the input tube is an NMOS tube, the invention introduces a third NMOS tube MN3 and a fourth NMOS tube to form a cascode structure with a first NMOS tube MN1 and a second NMOS tube MN2, and the grid electrode of the third NMOS tube MN3 is connected with a biasSet voltage VBA source connected to the drain of the first NMOS transistor MN1, and a drain connected to the first intermediate node VP(ii) a The grid electrode of the fourth NMOS tube is connected with a bias voltage VBA source connected to the drain of the second NMOS transistor MN2, and a drain connected to the second intermediate node VN(ii) a The first NMOS transistor MN1 and the second NMOS transistor MN2 are input paired transistors and work in a linear region, the third NMOS transistor MN3 and the fourth NMOS transistor are cascode transistors and work in a saturation region, and the structure has high linearity in an integral circuit.
The second connecting end of the first sampling capacitor is connected with the second connecting end of the second sampling capacitor and the input end of the switch control module and is connected with the power supply voltage VDD through a third switch device; the fourth switching device is connected between the first intermediate node and the power supply voltage VDD, and the fifth switching device is connected between the second intermediate node and the power supply voltage VDD; the first connecting end of the sixth switching device is connected with the first connecting end of the seventh switching device, and the second connecting end of the sixth switching device is grounded; the second connection terminal of the seventh switching device is connected to the source electrode of the first NMOS transistor MN1 and the source electrode of the second NMOS transistor MN 2.
The third switching device, the fourth switching device, the fifth switching device and the sixth switching device are controlled by a clock signal CLK, and when the clock signal CLK is in a first state, the third switching device, the fourth switching device and the fifth switching device are controlled to be switched on, and the sixth switching device is controlled to be switched off; and when the clock signal CLK is in a second state, the third switching device, the fourth switching device and the fifth switching device are controlled to be switched off, and the sixth switching device is controlled to be switched on. The first switching device SW1, the second switching device SW2 and the seventh switching device are controlled by an output signal of a switch control module, and the switch control module is used for controlling the voltage value V at the input end of the switch control moduleOCMComparing with the turning threshold voltage, and when the voltage value V of the input end of the switch control moduleOCMWhen the turning threshold voltage is not lower than the turning threshold voltage, the output signal of the switch control module controls the first switch device SW1, the second switch device SW2 and the seventh switch device to be conducted; when the voltage value V of the input end of the switch control moduleOCMWhen the voltage is lower than the turnover threshold voltage, the output signal of the switch control module controls the first switch device SW1 and the second switch device SW1The switching device SW2 and the seventh switching device are open.
In some embodiments, the third to fifth switching devices are implemented by PMOS transistors, and the sixth and seventh switching devices are implemented by NMOS transistors, as shown in fig. 3, the seventh switching device is a fifth NMOS transistor MN5, a gate of the fifth NMOS transistor MN5 is connected to the output signal SW of the switch control module, a source thereof is used as the first connection terminal of the seventh switching device, and a drain thereof is used as the second connection terminal of the seventh switching device. The third switching device is a first PMOS transistor MP1, the fourth switching device is a second PMOS transistor MP2, the fifth switching device is a third PMOS transistor MP3, and the sixth switching device is a sixth NMOS transistor MN 6; the gates of the first PMOS transistor MP1, the second PMOS transistor MP2 and the third PMOS transistor MP3 are all connected to a clock signal CLK, the sources thereof are all connected to a power supply voltage VDD, the drain of the first PMOS transistor MP1 is connected to the input terminal of the switch control module, the drain of the second PMOS transistor MP2 is connected to the first intermediate node, and the drain of the third PMOS transistor MP3 is connected to the second intermediate node; the gate of the sixth NMOS transistor MN6 is connected to the clock signal CLK, the drain thereof serves as the first connection terminal of the sixth switching device, and the source thereof serves as the second connection terminal of the sixth switching device.
The switch control module is used for converting the voltage value V of the input end of the switch control moduleOCMThe comparison with the flipping threshold voltage can be implemented by an inverter, or implemented by a comparator, as shown in fig. 3, a structure of a switch control module implemented by an inverter is provided, in this embodiment, the switch control module includes a first inverter INV1 and a second inverter INV2, an input end of the first inverter INV1 is connected to the signal V input from an input end of the switch control moduleOCMThe output end of the inverter is connected with the input end of the second inverter INV 2; an output end of the second inverter INV2 outputs the output signal SW of the switch control module.
The operation and the operation principle of the present embodiment will be described in detail below.
When the input tube is realized by adopting an NMOS tube in the embodiment, when the input tube MN1 and the input tube MN2 are in a linear region, the drain-end voltage of the input tube is stabilized by adding the cascode tube MN3 and the cascode tube MN4 in the design, and the charge coupled to the input from the output end is also reduced by adding the cascode tube, so that the kickback noise is greatly reduced. Therefore, the input end gate voltage and the output end drain current in the structure provided by the invention have good linear relation, the input tube transconductance changes little along with input and output signals, and the provided amplifier has higher gain precision.
When the clock signal CLK is at a low level, the dynamic operational amplifier is in a reset state, the third, fourth and fifth switching devices (i.e., the first, second and third PMOS transistors MP1, MP2 and MP3) are turned on, the sixth switching device (i.e., the sixth NMOS transistor MN6) is turned off, which causes the first, second, fourth and seventh NMOS transistors MN1, MN2, MN3, MN4 and MN5 to be turned off, and the first node V is connected to the first node VPAnd a second node VNAnd the input end potential V of the switch control moduleOCMIs reset to the power supply voltage VDD, and the input end potential V of the switch control moduleOCMThe output signal of the switch control module, namely the switch control signal SW, is obtained after passing through the two inverters of the switch control module, at the moment, the switch control signal SW is in a high level, the switch control signal SW controls the first switch device SW1 and the second switch device SW2 to be closed (when the SW is in the high level, the SW1 and the SW2 are closed, and when the SW is in the low level, the SW1 and the SW2 are opened), and the two load capacitors CLUpper output node VOP、VONIs charged to the power supply voltage VDD.
When the clock signal CLK is at a high level, the dynamic operational amplifier starts to operate in an amplifying state, the third, fourth and fifth switching devices (i.e., the first, second and third PMOS transistors MP1, MP2 and MP3) are turned off, the first, second and seventh NMOS transistors MN1, MN2, MN3, MN4, sixth switching devices (i.e., the sixth and fifth NMOS transistors MN6 and MN5) are turned on, the first and second switching devices SW1 and SW2 are initially maintained in a closed state, and the output node V of the two load capacitors CL is connected to the output node VOP、VONThe voltage drops from the supply voltage VDD at different rates (depending on the input differential magnitude) until the sampling capacitor CSSampled output common mode level VOCMDown to the flip threshold voltage V of the inverterTHWhen the switch control signal SW changes to the low level, the first switching device SW1 and the second switching device SW2 are turned off, and the node V is outputtedOP、VONThe voltage is kept unchanged, the seventh switching device (i.e. the fifth NMOS transistor MN5) is turned off, and then the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are turned off, and the output node V is connected to the output node VOP、VONThe maintained voltage difference is used as the differential output of the amplifier. The output differential voltage is divided by the input differential signal to obtain the gain of the amplifier.
As shown in fig. 3, when the input transistor is an NMOS transistor, the first NMOS transistor MN1 and the second NMOS transistor MN2 of the input transistor in this embodiment operate in a linear region, so that the transconductance of the input transistor is not related to the magnitude of the input differential signal, and is proportional to the voltage value at the drain terminal of the input transistor, and thus the structure has a large input swing. Since the added cascode transistors (the third NMOS transistor MN3 and the fourth NMOS transistor MN4) have shielding effect on the voltage variation at the output end, the drain end voltage of the input transistor is basically stable and unchanged, and thus the input voltage to the output current has high linearity. In addition, the added cascode tubes (the third NMOS tube MN3 and the fourth NMOS tube MN4) have the function of shielding the voltage change at the output end, so that the voltage change fed back to the input end by the voltage change at the output end is very small, and the linearity from the input voltage to the output current of the amplifier is also improved. When viewed in conjunction with the waveform diagram shown in fig. 4, the output node V is just due to the good linear relationship between the drain current of the input tube and the gate-source voltage in the structure of this embodimentOP、VONThe voltage drops linearly.
In order to embody specific performance, the conventional structure circuit and the structure circuit of the embodiment shown in fig. 3 are simulated, fig. 5 is an FFT analysis result of an output signal of the conventional dynamic operational amplifier, fig. 6 is an FFT analysis result of an output signal of the dynamic operational amplifier in the embodiment, and it can be seen that under the condition that the input swing of the dynamic operational amplifier with the conventional structure is 40mV, The Harmonic Distortion (THD) of the present invention is 53.29dB, the significant digit (Enob) is 8.56bit, The Harmonic Distortion (THD) of the conventional structure is 43.78dB, and the significant digit is only 6.98 bit. The structure provided by the invention obviously reduces harmonic distortion, improves amplification precision, and can meet the requirements of a higher-performance pipeline-successive approximation type analog-to-digital converter on the performance of an amplifier.
In the embodiment shown in fig. 3, the input transistor and the introduced cascode transistor are both NMOS transistors, and may also all adopt PMOS transistors correspondingly, so that the high linearity of the implemented dynamic operational amplifier is still achieved, and the working principle and effect are the same. As shown in fig. 7, when the input tube and the introduced cascode tube are implemented by PMOS tubes, the dynamic operational amplifier circuit includes a first switch device SW1, a second switch device SW2, a third switch device, a fourth switch device, a fifth switch device, a sixth switch device, a seventh switch device, a first load capacitor, a second load capacitor, a first sampling capacitor, a second sampling capacitor, a switch control module, a first input tube, a second input tube, and introduced cascode tubes (a sixth PMOS tube MP6 and a seventh PMOS tube MP7), where capacitance values of the first load capacitor and the second load capacitor are equal, capacitance values of the first sampling capacitor and the second sampling capacitor are equal, the first input tube is the fourth PMOS tube MP4, and the second input tube is the fifth PMOS tube MP 5; the first connecting end of the first switching device SW1 is used as a first differential output end of the dynamic operational amplifier circuit and is grounded after passing through the first load capacitor, and the second connecting end of the first switching device SW1 is connected with the first connecting end of the first sampling capacitor and is used as a first middle node; the first connecting end of the second switching device SW2 is used as a second differential output end of the dynamic operational amplifier circuit and is grounded after passing through a second load capacitor, and the second connecting end of the second switching device SW2 is connected with the first connecting end of the second sampling capacitor and is used as a second intermediate node; the second connecting end of the first sampling capacitor is connected with the second connecting end of the second sampling capacitor and the input end of the switch control module and is grounded after passing through the third switching device; the fourth switching device is connected between the first intermediate node and the ground, and the fifth switching device is connected between the second intermediate node and the ground; the first connecting end of the sixth switching device is connected with the first connecting end of the seventh switching device, and the second connecting end of the sixth switching device is connected with the power supply voltage VDD; a second connection end of the seventh switch device is connected with a source electrode of the fourth PMOS transistor MP4 and a source electrode of the fifth PMOS transistor MP5, a gate electrode of the fourth PMOS transistor MP4 serves as a first differential input end of the dynamic operational amplifier circuit, and a gate electrode of the second PMOS terminal serves as a second differential input end of the dynamic operational amplifier circuit; the third switching device, the fourth switching device, the fifth switching device and the sixth switching device are controlled by a clock signal CLK, and when the clock signal CLK is in a first state, the third switching device, the fourth switching device and the fifth switching device are controlled to be switched on, and the sixth switching device is controlled to be switched off; when the clock signal CLK is in a second state, the third switching device, the fourth switching device and the fifth switching device are controlled to be switched off, and the sixth switching device is controlled to be switched on; the first switch device SW1, the second switch device SW2 and the seventh switch device are controlled by an output signal of a switch control module, the switch control module is used for comparing a voltage value of an input end of the switch control module with a turnover threshold voltage, and when the voltage value of the input end of the switch control module is not lower than the turnover threshold voltage, the output signal of the switch control module controls the first switch device SW1, the second switch device SW2 and the seventh switch device to be conducted; when the voltage value of the input end of the switch control module is lower than the overturning threshold voltage, the output signal of the switch control module controls the first switch device SW1, the second switch device SW2 and the seventh switch device to be switched off; the gate of the sixth PMOS transistor MP6 is connected to the bias voltage, the source thereof is connected to the drain of the fourth PMOS transistor MP4, and the drain thereof is connected to the first intermediate node; the gate of the seventh PMOS transistor MP7 is connected to the bias voltage, the source thereof is connected to the drain of the fifth PMOS transistor MP5, and the drain thereof is connected to the second intermediate node; the fourth PMOS transistor MP4 and the fifth PMOS transistor MP5 operate in a linear region, and the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 operate in a saturation region.
In some embodiments, the third to fifth switching devices are implemented by NMOS transistors, and the sixth and seventh switching devices are implemented by PMOS transistors, as shown in fig. 7, the seventh switching device is an eighth PMOS transistor MP8, a gate of the eighth PMOS transistor MP8 is connected to the output signal of the switch control module, a source thereof is used as the first connection terminal of the seventh switching device, and a drain thereof is used as the second connection terminal of the seventh switching device. The third switching device is a seventh NMOS transistor MN7, the fourth switching device is an eighth NMOS transistor MN8, the fifth switching device is a ninth NMOS transistor MN9, and the sixth switching device is a ninth PMOS transistor MP 9; the gates of the seventh NMOS transistor MN7, the eighth NMOS transistor MN8 and the ninth NMOS transistor MN9 are all connected to the clock signal CLK, the sources thereof are all grounded, the drain of the seventh NMOS transistor MN7 is connected to the input terminal of the switch control module, the drain of the eighth NMOS transistor MN8 is connected to the first intermediate node, and the drain of the ninth NMOS transistor MN9 is connected to the second intermediate node; the ninth PMOS transistor MP9 has a gate connected to the clock signal CLK, a drain serving as the first connection terminal of the sixth switching device, and a source serving as the second connection terminal of the sixth switching device.
In the embodiment shown in FIG. 7, the signal VIP、VINThe level of the positive input terminal (i.e. the second input terminal of the dynamic operational amplifier) and the level of the negative input terminal (i.e. the first input terminal of the dynamic operational amplifier) of the dynamic operational amplifier, respectively, and a node VOP、VONPositive output terminal (i.e. first output terminal of dynamic operational amplifier) and negative output terminal (i.e. second output terminal of dynamic operational amplifier), respectively, nodes VDD and GND are power voltage and ground voltage, respectively, signal CLK is input-controlled clock signal, and signal V is input-controlled clock signalBFor the bias voltage, the signal SW is a digital signal generated by the switch control module to control the operation states of the first switching device SW1, the second switching device SW2 and the seventh switching device (MP 8). The working principle and the working process of the dynamic operational amplifier circuit for realizing the input tube by the PMOS tube shown in fig. 7 and the input tube by the NMOS tube shown in fig. 3 are similar, and are not described again here.
According to the dynamic operational amplifier circuit with the input tube in the linear region, the input range of the dynamic operational amplifier is enlarged by enabling the input tube to be in the linear region; meanwhile, a cascode tube is introduced to stabilize the drain-end voltage of the input tube, so that a good linear relation between the gate-source voltage and the drain-source current of the input tube is realized, and the gain precision of the dynamic operational amplifier is ensured. While the embodiments have been described with respect to the selection of particular switch types and the selection of signal states, those skilled in the art, having benefit of this disclosure, will appreciate that many other variations and combinations can be made which do not depart from the spirit of the invention as disclosed herein, which still fall within the scope of the invention.

Claims (8)

1.一种输入管处于线性区的动态运算放大器电路，包括第一开关器件、第二开关器件、第三开关器件、第四开关器件、第五开关器件、第六开关器件、第七开关器件、第一负载电容、第二负载电容、第一采样电容、第二采样电容、开关控制模块、第一输入管和第二输入管，其中第一负载电容和第二负载电容的电容值相等，第一采样电容和第二采样电容的电容值相等，第一输入管为第一NMOS管，第二输入管为第二NMOS管；1. A dynamic operational amplifier circuit with an input tube in a linear region, comprising a first switching device, a second switching device, a third switching device, a fourth switching device, a fifth switching device, a sixth switching device, and a seventh switching device , a first load capacitor, a second load capacitor, a first sampling capacitor, a second sampling capacitor, a switch control module, a first input tube and a second input tube, wherein the capacitance values of the first load capacitor and the second load capacitor are equal, The capacitance values of the first sampling capacitor and the second sampling capacitor are equal, the first input tube is a first NMOS tube, and the second input tube is a second NMOS tube; 第一开关器件的第一连接端作为所述动态运算放大器电路的第一差分输出端并通过第一负载电容后接地，其第二连接端连接第一采样电容的第一连接端并作为第一中间节点；The first connection end of the first switching device is used as the first differential output end of the dynamic operational amplifier circuit and is grounded after passing through the first load capacitor, and the second connection end thereof is connected to the first connection end of the first sampling capacitor and serves as the first connection end of the first sampling capacitor. intermediate node; 第二开关器件的第一连接端作为所述动态运算放大器电路的第二差分输出端并通过第二负载电容后接地，其第二连接端连接第二采样电容的第一连接端并作为第二中间节点；The first connection end of the second switching device is used as the second differential output end of the dynamic operational amplifier circuit and is grounded after passing through the second load capacitor, and the second connection end of the second switching device is connected to the first connection end of the second sampling capacitor and serves as the second intermediate node; 第一采样电容的第二连接端连接第二采样电容的第二连接端和所述开关控制模块的输入端并通过第三开关器件后连接电源电压；The second connection end of the first sampling capacitor is connected to the second connection end of the second sampling capacitor and the input end of the switch control module, and is connected to the power supply voltage after passing through the third switch device; 第四开关器件接在所述第一中间节点和所述电源电压之间，第五开关器件接在所述第二中间节点和所述电源电压之间；a fourth switching device is connected between the first intermediate node and the power supply voltage, and a fifth switching device is connected between the second intermediate node and the power supply voltage; 第六开关器件的第一连接端连接第七开关器件的第一连接端，其第二连接端接地；The first connection end of the sixth switch device is connected to the first connection end of the seventh switch device, and the second connection end thereof is grounded; 第七开关器件的第二连接端连接第一NMOS管的源极和第二NMOS管的源极，第一NMOS管的栅极作为所述动态运算放大器电路的第一差分输入端，第二NMOS端的栅极作为所述动态运算放大器电路的第二差分输入端；The second connection terminal of the seventh switching device is connected to the source of the first NMOS transistor and the source of the second NMOS transistor, the gate of the first NMOS transistor is used as the first differential input terminal of the dynamic operational amplifier circuit, and the second NMOS transistor is used as the first differential input terminal of the dynamic operational amplifier circuit. The gate of the terminal is used as the second differential input terminal of the dynamic operational amplifier circuit; 所述第三开关器件、第四开关器件、第五开关器件和第六开关器件由时钟信号控制，当所述时钟信号为第一状态时，控制第三开关器件、第四开关器件和第五开关器件导通，控制第六开关器件断开；当所述时钟信号为第二状态时，控制第三开关器件、第四开关器件和第五开关器件断开，控制第六开关器件导通；The third switching device, the fourth switching device, the fifth switching device and the sixth switching device are controlled by a clock signal, and when the clock signal is in the first state, the third switching device, the fourth switching device and the fifth switching device are controlled The switching device is turned on, and the sixth switching device is controlled to be turned off; when the clock signal is in the second state, the third switching device, the fourth switching device and the fifth switching device are controlled to be turned off, and the sixth switching device is controlled to be turned on; 所述第一开关器件、第二开关器件和第七开关器件由所述开关控制模块的输出信号控制，所述开关控制模块用于将所述开关控制模块输入端的电压值与翻转阈值电压进行比较，当所述开关控制模块输入端的电压值不低于所述翻转阈值电压时，所述开关控制模块的输出信号控制第一开关器件、第二开关器件和第七开关器件导通；当所述开关控制模块输入端的电压值低于所述翻转阈值电压时，所述开关控制模块的输出信号控制第一开关器件、第二开关器件和第七开关器件断开；The first switching device, the second switching device and the seventh switching device are controlled by the output signal of the switch control module, and the switch control module is configured to compare the voltage value of the input terminal of the switch control module with the inversion threshold voltage , when the voltage value of the input terminal of the switch control module is not lower than the inversion threshold voltage, the output signal of the switch control module controls the first switching device, the second switching device and the seventh switching device to conduct; when the When the voltage value of the input terminal of the switch control module is lower than the inversion threshold voltage, the output signal of the switch control module controls the first switching device, the second switching device and the seventh switching device to be disconnected; 其特征在于，所述动态运算放大器电路还包括第三NMOS管和第四NMOS管；It is characterized in that, the dynamic operational amplifier circuit further comprises a third NMOS transistor and a fourth NMOS transistor; 第三NMOS管的栅极连接偏置电压，其源极连接第一NMOS管的漏极，其漏极连接所述第一中间节点；The gate of the third NMOS transistor is connected to the bias voltage, the source of the third NMOS transistor is connected to the drain of the first NMOS transistor, and the drain of the third NMOS transistor is connected to the first intermediate node; 第四NMOS管的栅极连接所述偏置电压，其源极连接第二NMOS管的漏极，其漏极连接所述第二中间节点；The gate of the fourth NMOS transistor is connected to the bias voltage, the source of the fourth NMOS transistor is connected to the drain of the second NMOS transistor, and the drain of the fourth NMOS transistor is connected to the second intermediate node; 第一NMOS管和第二NMOS管工作在线性区，第三NMOS管和第四NMOS管工作在饱和区。The first NMOS transistor and the second NMOS transistor work in the linear region, and the third NMOS transistor and the fourth NMOS transistor work in the saturation region. 2.根据权利要求1所述的输入管处于线性区的动态运算放大器电路，其特征在于，所述开关控制模块包括第一反相器和第二反相器，第一反相器的输入端连接所述开关控制模块的输入端，其输出端连接第二反相器的输入端；第二反相器的输出端输出所述开关控制模块的输出信号。2. The dynamic operational amplifier circuit with an input tube in a linear region according to claim 1, wherein the switch control module comprises a first inverter and a second inverter, and the input end of the first inverter The input end of the switch control module is connected, and the output end thereof is connected to the input end of the second inverter; the output end of the second inverter outputs the output signal of the switch control module. 3.根据权利要求2所述的输入管处于线性区的动态运算放大器电路，其特征在于，第七开关器件为第五NMOS管，第五NMOS管的栅极连接所述开关控制模块的输出信号，其源极作为所述第七开关器件的第一连接端，其漏极作为所述第七开关器件的第二连接端。3 . The dynamic operational amplifier circuit with an input tube in a linear region according to claim 2 , wherein the seventh switching device is a fifth NMOS tube, and the gate of the fifth NMOS tube is connected to the output signal of the switch control module. 4 . , the source of which is used as the first connection terminal of the seventh switching device, and the drain of which is used as the second connection terminal of the seventh switching device. 4.根据权利要求1至3任一项所述的输入管处于线性区的动态运算放大器电路，其特征在于，第三开关器件为第一PMOS管，第四开关器件为第二PMOS管，第五开关器件为第三PMOS管，第六开关器件为第六NMOS管；4. The dynamic operational amplifier circuit with an input tube in a linear region according to any one of claims 1 to 3, wherein the third switching device is a first PMOS tube, the fourth switching device is a second PMOS tube, and the third switching device is a second PMOS tube. The fifth switching device is the third PMOS tube, and the sixth switching device is the sixth NMOS tube; 第一PMOS管、第二PMOS管和第三PMOS管的栅极均连接所述时钟信号，其源极均连接所述电源电压，第一PMOS管的漏极连接所述开关控制模块的输入端，第二PMOS管的漏极连接所述第一中间节点，第三PMOS管的漏极连接所述第二中间节点；The gates of the first PMOS transistor, the second PMOS transistor and the third PMOS transistor are all connected to the clock signal, their sources are all connected to the power supply voltage, and the drain of the first PMOS transistor is connected to the input end of the switch control module , the drain of the second PMOS transistor is connected to the first intermediate node, and the drain of the third PMOS transistor is connected to the second intermediate node; 第六NMOS管的栅极连接所述时钟信号，其漏极作为所述第六开关器件的第一连接端，其源极作为所述第六开关器件的第二连接端。The gate of the sixth NMOS transistor is connected to the clock signal, the drain thereof is used as the first connection terminal of the sixth switching device, and the source thereof is used as the second connection terminal of the sixth switching device. 5.一种输入管处于线性区的动态运算放大器电路，包括第一开关器件、第二开关器件、第三开关器件、第四开关器件、第五开关器件、第六开关器件、第七开关器件、第一负载电容、第二负载电容、第一采样电容、第二采样电容、开关控制模块、第一输入管和第二输入管，其中第一负载电容和第二负载电容的电容值相等，第一采样电容和第二采样电容的电容值相等，第一输入管为第四PMOS管，第二输入管为第五PMOS管；5. A dynamic operational amplifier circuit with an input tube in a linear region, comprising a first switching device, a second switching device, a third switching device, a fourth switching device, a fifth switching device, a sixth switching device, and a seventh switching device , a first load capacitor, a second load capacitor, a first sampling capacitor, a second sampling capacitor, a switch control module, a first input tube and a second input tube, wherein the capacitance values of the first load capacitor and the second load capacitor are equal, The capacitance values of the first sampling capacitor and the second sampling capacitor are equal, the first input tube is the fourth PMOS tube, and the second input tube is the fifth PMOS tube; 第一开关器件的第一连接端作为所述动态运算放大器电路的第一差分输出端并通过第一负载电容后接地，其第二连接端连接第一采样电容的第一连接端并作为第一中间节点；The first connection end of the first switching device is used as the first differential output end of the dynamic operational amplifier circuit and is grounded after passing through the first load capacitor, and the second connection end thereof is connected to the first connection end of the first sampling capacitor and serves as the first connection end of the first sampling capacitor. intermediate node; 第二开关器件的第一连接端作为所述动态运算放大器电路的第二差分输出端并通过第二负载电容后接地，其第二连接端连接第二采样电容的第一连接端并作为第二中间节点；The first connection end of the second switching device is used as the second differential output end of the dynamic operational amplifier circuit and is grounded after passing through the second load capacitor, and the second connection end of the second switching device is connected to the first connection end of the second sampling capacitor and serves as the second intermediate node; 第一采样电容的第二连接端连接第二采样电容的第二连接端和所述开关控制模块的输入端并通过第三开关器件后接地；The second connection end of the first sampling capacitor is connected to the second connection end of the second sampling capacitor and the input end of the switch control module, and is grounded after passing through the third switch device; 第四开关器件接在所述第一中间节点和地之间，第五开关器件接在所述第二中间节点和地之间；The fourth switching device is connected between the first intermediate node and the ground, and the fifth switching device is connected between the second intermediate node and the ground; 第六开关器件的第一连接端连接第七开关器件的第一连接端，其第二连接端连接电源电压；The first connection end of the sixth switch device is connected to the first connection end of the seventh switch device, and the second connection end of the sixth switch device is connected to the power supply voltage; 第七开关器件的第二连接端连接第四PMOS管的源极和第五PMOS管的源极，第四PMOS管的栅极作为所述动态运算放大器电路的第一差分输入端，第二PMOS端的栅极作为所述动态运算放大器电路的第二差分输入端；The second connection terminal of the seventh switching device is connected to the source of the fourth PMOS transistor and the source of the fifth PMOS transistor, the gate of the fourth PMOS transistor is used as the first differential input terminal of the dynamic operational amplifier circuit, and the second PMOS transistor The gate of the terminal is used as the second differential input terminal of the dynamic operational amplifier circuit; 所述第三开关器件、第四开关器件、第五开关器件和第六开关器件由时钟信号控制，当所述时钟信号为第一状态时，控制第三开关器件、第四开关器件和第五开关器件导通，控制第六开关器件断开；当所述时钟信号为第二状态时，控制第三开关器件、第四开关器件和第五开关器件断开，控制第六开关器件导通；The third switching device, the fourth switching device, the fifth switching device and the sixth switching device are controlled by a clock signal, and when the clock signal is in the first state, the third switching device, the fourth switching device and the fifth switching device are controlled The switching device is turned on, and the sixth switching device is controlled to be turned off; when the clock signal is in the second state, the third switching device, the fourth switching device and the fifth switching device are controlled to be turned off, and the sixth switching device is controlled to be turned on; 所述第一开关器件、第二开关器件和第七开关器件由所述开关控制模块的输出信号控制，所述开关控制模块用于将所述开关控制模块输入端的电压值与翻转阈值电压进行比较，当所述开关控制模块输入端的电压值不低于所述翻转阈值电压时，所述开关控制模块的输出信号控制第一开关器件、第二开关器件和第七开关器件导通；当所述开关控制模块输入端的电压值低于所述翻转阈值电压时，所述开关控制模块的输出信号控制第一开关器件、第二开关器件和第七开关器件断开；The first switching device, the second switching device and the seventh switching device are controlled by the output signal of the switch control module, and the switch control module is configured to compare the voltage value of the input terminal of the switch control module with the inversion threshold voltage , when the voltage value of the input terminal of the switch control module is not lower than the inversion threshold voltage, the output signal of the switch control module controls the first switching device, the second switching device and the seventh switching device to conduct; when the When the voltage value of the input terminal of the switch control module is lower than the inversion threshold voltage, the output signal of the switch control module controls the first switching device, the second switching device and the seventh switching device to be disconnected; 其特征在于，所述动态运算放大器电路还包括第六PMOS管和第七PMOS管；It is characterized in that, the dynamic operational amplifier circuit further comprises a sixth PMOS transistor and a seventh PMOS transistor; 第六PMOS管的栅极连接偏置电压，其源极连接第四PMOS管的漏极，其漏极连接所述第一中间节点；The gate of the sixth PMOS transistor is connected to the bias voltage, the source of the sixth PMOS transistor is connected to the drain of the fourth PMOS transistor, and the drain of the sixth PMOS transistor is connected to the first intermediate node; 第七PMOS管的栅极连接所述偏置电压，其源极连接第五PMOS管的漏极，其漏极连接所述第二中间节点；The gate of the seventh PMOS transistor is connected to the bias voltage, the source of the seventh PMOS transistor is connected to the drain of the fifth PMOS transistor, and the drain of the seventh PMOS transistor is connected to the second intermediate node; 第四PMOS管和第五PMOS管工作在线性区，第六PMOS管和第七PMOS管工作在饱和区。The fourth PMOS transistor and the fifth PMOS transistor work in the linear region, and the sixth PMOS transistor and the seventh PMOS transistor work in the saturation region. 6.根据权利要求5所述的输入管处于线性区的动态运算放大器电路，其特征在于，所述开关控制模块包括第一反相器和第二反相器，第一反相器的输入端连接所述开关控制模块的输入端，其输出端连接第二反相器的输入端；第二反相器的输出端输出所述开关控制模块的输出信号。6. The dynamic operational amplifier circuit with an input tube in a linear region according to claim 5, wherein the switch control module comprises a first inverter and a second inverter, and the input end of the first inverter The input end of the switch control module is connected, and the output end thereof is connected to the input end of the second inverter; the output end of the second inverter outputs the output signal of the switch control module. 7.根据权利要求6所述的输入管处于线性区的动态运算放大器电路，其特征在于，第七开关器件为第八PMOS管，第八PMOS管的栅极连接所述开关控制模块的输出信号，其源极作为所述第七开关器件的第一连接端，其漏极作为所述第七开关器件的第二连接端。7 . The dynamic operational amplifier circuit with an input tube in a linear region according to claim 6 , wherein the seventh switching device is an eighth PMOS tube, and the gate of the eighth PMOS tube is connected to the output signal of the switch control module. 8 . , the source of which is used as the first connection terminal of the seventh switching device, and the drain of which is used as the second connection terminal of the seventh switching device. 8.根据权利要求5至7任一项所述的输入管处于线性区的动态运算放大器电路，其特征在于，第三开关器件为第七NMOS管，第四开关器件为第八NMOS管，第五开关器件为第九NMOS管，第六开关器件为第九PMOS管；8. The dynamic operational amplifier circuit with an input tube in a linear region according to any one of claims 5 to 7, wherein the third switching device is a seventh NMOS tube, the fourth switching device is an eighth NMOS tube, and the third switching device is a seventh NMOS tube. The fifth switch device is the ninth NMOS tube, and the sixth switch device is the ninth PMOS tube; 第七NMOS管、第八NMOS管和第九NMOS管的栅极均连接所述时钟信号，其源极均接地，第七NMOS管的漏极连接所述开关控制模块的输入端，第八NMOS管的漏极连接所述第一中间节点，第九NMOS管的漏极连接所述第二中间节点；The gates of the seventh NMOS transistor, the eighth NMOS transistor and the ninth NMOS transistor are all connected to the clock signal, their sources are all grounded, the drain of the seventh NMOS transistor is connected to the input end of the switch control module, and the eighth NMOS transistor is connected to the input end of the switch control module. The drain of the transistor is connected to the first intermediate node, and the drain of the ninth NMOS transistor is connected to the second intermediate node; 第九PMOS管的栅极连接所述时钟信号，其漏极作为所述第六开关器件的第一连接端，其源极作为所述第六开关器件的第二连接端。The gate of the ninth PMOS transistor is connected to the clock signal, the drain thereof is used as the first connection terminal of the sixth switching device, and the source thereof is used as the second connection terminal of the sixth switching device.
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