CN114389585A - High-speed low-offset latch comparator - Google Patents

Abstract

The invention belongs to the technical field of comparators, and in particular relates to a high-speed low-offset latch comparator. The invention can reduce the static offset of the comparator and improve the speed of the latch by inserting a cross-coupling capacitor in the latch and introducing a reset transistor to reset the gate voltage of the PMOS transistor to ground in the reset stage. In addition, the introduction of the preamplifier provides higher speed, bandwidth and gain, further reduces the input offset of the comparator, and at the same time isolates the input signal from the output signal, reducing the kickback noise, thus realizing a lock with high speed and low offset. Save the comparator.

Description

A High Speed Low Offset Latching Comparator

technical field

The invention belongs to the technical field of comparators, in particular to a high-speed and low-offset latching comparator.

Background technique

The comparator is an important part of the analog integrated circuit, especially the analog-to-digital or digital-to-analog converter. Its function is to compare the two analog signals of the differential input, and according to the relative magnitude of the differential input signal, the output obtains the corresponding binary logic. Level 0 or 1. As the core module of the analog-to-digital converter, the speed and accuracy of the comparator directly affect the overall performance of the analog-to-digital converter. If the offset voltage of the comparator is large, it will cause the missing code of the analog-to-digital converter, resulting in conversion errors; if the speed of the comparator is low, it cannot complete the comparison and output the correct comparison result within the specified time, resulting in a metastable state. Therefore, to realize high-speed and high-precision analog-to-digital converters, the speed and accuracy of the comparator are the keys.

In high-speed comparators, the fast comparison characteristics of latched comparators are often used. Figure 1 shows the schematic diagram of the circuit structure of the existing latched comparators, which consists of two amplifying units (inverters) connected end-to-end. A loop is a positive feedback loop. When there is a difference in the differential input voltage, the function of the positive feedback is to increase the signal difference until one end is close to the power supply VDD, and the other end is close to the ground GND, so as to achieve the corresponding binary logic level. 0 or 1. The comparison speed of this latching comparator is inversely proportional to the size of the device, thereby forming a contradiction between offset and speed, that is, between precision and speed. At the same time, due to the direct connection between the input end and the output end of the comparator, the kickback noise of this structure is very large.

SUMMARY OF THE INVENTION

Aiming at the above-mentioned contradictions of the existing latching comparators, the present invention proposes a high-speed and low-offset latching comparator, which can improve the speed while reducing the offset of the comparator and reduce the kickback compared with the existing latching comparators. noise.

The technical scheme of the present invention is:

A high-speed, low-offset latching comparator including:

The pre-amplifier is used to amplify the input differential signal and load it into the latch input to isolate the input signal and the output signal;

The latch is connected with the preamplifier and used to compare the differential signal amplified by the preamplifier;

The preamplifier is composed of a differential input pair and a load resistor;

The latch is composed of two end-to-end amplifying units, each amplifying unit is coupled via a cross-coupling capacitor, the input end is controlled by a switch tube, and the output end of each amplifying unit is reset to ground by a reset tube, The switch tube and the reset tube receive the same clock signal to be turned on or off synchronously, which is a reset stage or a comparison stage, respectively.

Further, the pre-amplifier includes a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a first load resistor R1 and a second load resistor R2; wherein the first NMOS transistor MN1 and the second NMOS transistor The transistor MN2 is a differential input pair, and the gates of the first NMOS transistor MN1 and the second NMOS transistor MN2 receive differential input signals respectively; the third NMOS transistor MN3 is used as a bias current source, its gate is connected to a bias voltage, and its source The electrode is grounded, and its drain is connected to the source of the first NMOS transistor MN1 and the second NMOS transistor MN2 respectively for providing bias current; the drain of the first NMOS transistor MN1 is connected to the power supply through the first resistor R1, and the second NMOS transistor is connected to the power supply. MN2 is connected to the power supply through the second load resistor R2. The connection point between the first NMOS transistor MN1 and the first resistor R1 and the connection point between the second NMOS transistor MN2 and the second load resistor R2 are the differential signal output terminals of the preamplifier.

Further, the latch includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, and a seventh NMOS transistor MN7 , the eighth NMOS transistor MN8, the ninth NMOS transistor MN9, the first coupling capacitor C1 and the second coupling capacitor C2; wherein, the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5 are switch transistors, and the drain of the fourth NMOS transistor MN4 The drain of the first NMOS transistor MN1 is connected, the drain of the fifth NMOS transistor MN5 is connected to the drain of the second NMOS transistor MN2, and the gates of the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5 are connected to the same clock signal;

The sixth NMOS transistor MN6 and the first PMOS transistor MP1 constitute a first amplifying unit. The source of the first PMOS transistor MP1 is connected to the power supply, the drain of the first PMOS transistor MP1 is connected to the drain of the sixth NMOS transistor MN6, and the gate of the first PMOS transistor MP1 is connected to the power supply. The drain of the second PMOS transistor MP2; the gate of the sixth NMOS transistor MN6 is connected to the source of the fourth NMOS transistor MN4, and the source of the sixth NMOS transistor MN6 is grounded; the gate of the sixth NMOS transistor MN6 is connected to the first PMOS transistor The gates of MP1 are coupled through the first coupling capacitor C1;

The seventh NMOS transistor MN7 and the second PMOS transistor MP2 form a second amplifying unit. The source of the second PMOS transistor MP2 is connected to the power supply, the drain is connected to the drain of the seventh NMOS transistor MN7, and the gate of the second PMOS transistor MP2 is connected to the power supply. The drain of the first PMOS transistor MP1; the gate of the seventh NMOS transistor MN7 is connected to the source of the fifth NMOS transistor MN5, and the source of the seventh NMOS transistor MN7 is grounded; the gate of the seventh NMOS transistor MN7 and the second PMOS transistor The gates of MP2 are coupled through the second coupling capacitor C2;

The connection point of the gate of the first PMOS transistor MP1, the drain of the seventh NMOS transistor MN7 and the drain of the second PMOS transistor MP2, and the gate of the second PMOS transistor MP2, the drain of the sixth NMOS transistor MN6 and the drain of the first PMOS transistor MP1 The connection points of the poles are the two output terminals of the latch;

The eighth NMOS transistor MN8 and the ninth NMOS transistor MN9 are reset transistors, the drain of the eighth NMOS transistor MN8 is connected to the drain of the first PMOS transistor MP1, and the gate of the eighth NMOS transistor MN8 is connected to the fourth NMOS transistor The gate of MN4, the source of the eighth NMOS transistor MN8 is grounded; the drain of the ninth NMOS transistor MN9 is connected to the drain of the second PMOS transistor MP2, and the gate of the ninth NMOS transistor MN9 is connected to the drain of the fifth NMOS transistor MN5 The gate, the source of the ninth NMOS transistor MN9 is grounded.

The beneficial effects of the present invention are: by inserting a cross-coupling capacitor in the latch, and by introducing a reset transistor, the gate voltage of the PMOS transistor is reset to the ground in the reset stage, which can reduce the static offset of the comparator and improve the latching performance. storage speed. In addition, the introduction of the preamplifier provides higher speed, bandwidth and gain, further reduces the input offset of the comparator, and at the same time isolates the input signal from the output signal, reducing the kickback noise, thus realizing a lock with high speed and low offset. Save the comparator.

Description of drawings

1 is a schematic diagram of a circuit structure of an existing latch comparator;

2 is a schematic diagram of the circuit structure of a high-speed low-offset latch comparator proposed by the present invention;

3 is a schematic diagram of the circuit structure of the latching comparator reset stage proposed by the present invention;

FIG. 4 is a schematic diagram of the circuit structure of the comparison stage of the latch comparator proposed by the present invention.

Detailed ways

The technical solutions of the present invention are described in detail below in conjunction with the accompanying drawings:

The schematic diagram of the circuit structure of the existing latch comparator is shown in Figure 1. The principle is to control the comparator phase and reset phase through the clock signal Latch. When the Latch is at a high potential, the switch tubes MN3 and MN4 and the reset tube MN5 Both are turned on, the comparator enters the reset phase, and the output terminal (input terminal) of the comparator is pulled to the same potential. When the Latch is low, the switch tubes MN3 and MN4 and the reset tube MN5 are all turned off, and the comparator enters the comparison stage. The signal difference at its input triggers the positive feedback loop formed by the two amplifying units, and the signal difference is enlarged to one end. Close to the power supply VDD, one end is close to the ground GND. Since the speed of this structure is inversely proportional to the square of the channel length, in order to achieve a higher speed, the minimum channel length is generally selected, so the mismatch between transistors will become more and more serious, resulting in excessive offset and limiting the accuracy of the comparator .

A schematic diagram of the circuit structure of a high-speed low-offset latch comparator proposed by the present invention, as shown in FIG. 2 , includes a preamplifier and a latch. The preamplifier is used to amplify the input differential signal and load it into the latch input to isolate the input signal from the output signal; the latch is connected to the preamplifier and used to compare the preamplifier amplified differential signal.

The preamplifier includes a differential input pair 1 and a load resistor 2; the differential input pair 1 includes a first NMOS transistor MN1 and a second NMOS transistor MN2, and the gates of the first NMOS transistor MN1 and the second NMOS transistor MN2 are respectively connected to the differential input signal Vinn and Vinp, the source is connected to the bias current, and the drain is connected to the load resistance as the differential output of the preamplifier. The bias current source includes a third NMOS transistor MN3, the gate of which is connected to the bias voltage VB, the source is grounded to GND, and the drain is connected to the sources of the first NMOS transistor MN1 and the second NMOS transistor MN2, which are used for the differential The input pair provides bias current.

The load resistor 2 includes a first load resistor R1 and a second load resistor R2. Both ends of the first load resistor R1 are respectively connected to the drain of the first NMOS transistor MN1 and the power supply VDD, and both ends of the second load resistor R2 are respectively connected to the second NMOS transistor. Drain of MN2 and power supply VDD. One end connected to the drains of the first NMOS transistor MN1 and the second NMOS transistor MN2 is used as the output end of the pre-amplifier output, namely the output nodes V _on and V _op in FIG. 2 .

The preamplifier is loaded with a resistor, and its gain is:

A _V = -gm ₁ R _L

It can provide a certain gain, amplify the differential input signal by a certain multiple, and input it to the latch for comparison, thereby reducing the input offset of the comparator. On the other hand, using a resistor as a load can increase the speed of the pre-amplifier, thereby improving the comparison. speed of the device.

The latch includes a first switch tube, a second switch tube, a first amplifying unit 3 and a first amplifying unit 3 coupled by a cross-coupling capacitor (including a first coupling capacitor C1 and a second coupling capacitor C2, C ₁ =C ₂ =C). Two amplifying units 4 and a first reset tube and a second reset tube; the first switch tube includes a fourth NMOS tube MN4, the second switch tube includes a fifth NMOS tube MN5, and the drains of the switch tubes are respectively connected to the differential of the preamplifier. The output signal is connected to the drains (ie V _on and V _op ) of the first NMOS transistor MN1 and the second NMOS transistor MN2 respectively, the gate is connected to the same clock signal Latch, and the source is connected to the first amplifying unit and the second amplifying unit as an output. input of the unit. When the clock signal Latch is at a high potential, the switches are all turned on, and the differential signal amplified by the pre-amplifier is sampled to the input end of the amplifying unit; when the clock signal Latch is at a low potential, the switches are all turned off, at this time Enter the comparator comparison phase.

The first amplifying unit includes a sixth NMOS transistor MN6 and a first PMOS transistor MP1, and the second amplifying unit includes a seventh NMOS transistor MN7 and a second PMOS transistor MP2. The gate of the sixth NMOS transistor MN6 and the gate of the first PMOS transistor MP1 are coupled through the first coupling capacitor C1, and the gate of the sixth NMOS transistor MN6 is connected to the source of the fourth NMOS transistor MN4 as the first amplifying unit The gate of the first PMOS tube MP1 is connected to the seventh NMOS tube MN7 and the drain of the second PMOS tube MP2 as the differential output end of the latch; the gate of the seventh NMOS tube MN7 and the second PMOS tube MP2 The gates are coupled through the second coupling capacitor C2, the gate of the seventh NMOS transistor MN7 is connected to the source of the fifth NMOS transistor MN5 as the input terminal of the second amplifying unit, and the gate of the second PMOS transistor MP2 is connected to the first The drains of the six NMOS transistors MN6 and the first PMOS transistor MP1 are used as another differential output terminal of the latch; the sources of the first PMOS transistor MP1 and the second PMOS transistor MP2 are connected to the power supply VDD, and the sixth NMOS transistor MN6 and the seventh The source of the NMOS transistor MN7 is grounded to GND. Due to the introduction of the cross _- coupling capacitors _C1 and C2, the gate voltages of the PMOS and NMOS are isolated and can be biased separately. The bias voltage of the NMOS is determined by the output of the pre-amplifier, and the bias voltage of the PMOS is determined by the reset voltage. The voltage is determined, and due to the insertion of coupling capacitors, the gate-source voltage _VGS of NMOS and PMOS can be maximized, exceeding VDD. The sum of the gate-source voltages of the NMOS and PMOS of the traditional structure is:

V _GSN +V _GSP =V _DD

Due to the insertion of coupling capacitors, the sum of the gate-source voltages of NMOS and PMOS is:

V _GSN +V _GSP =V _DD +V _C

Therefore, the transconductance gm of the MOS transistor can be increased, thereby increasing the speed of the comparator. Not only that, the insertion of the cross-coupling capacitor can also play a memory function, which can reduce the static offset of the comparator.

The first reset transistor includes an eighth NMOS transistor MN8, the second reset transistor includes a ninth NMOS transistor MN9, the drain of the eighth NMOS transistor MN8 is connected to the drain of the sixth NMOS transistor MN6 and the drain of the first PMOS transistor MP1, and the ninth NMOS transistor The drain of MN9 is connected to the drain of the seventh NMOS transistor MN7 and the drain of the second PMOS transistor MP2, the gates of the eighth NMOS transistor MN8 and the ninth NMOS transistor MN9 are connected to the gate of the switch transistor and the clock signal Latch, and the eighth NMOS transistor MN8 and the source of the ninth NMOS transistor MN9 is grounded to GND.

When the clock signal Latch is at a high level, as shown in Figure 3, both the switch tube and the reset tube are turned on, and the differential signal amplified by the preamplifier is sampled to the input end of the amplifying unit. The sixth NMOS transistor MN6 and the first The drain voltage and source voltage of the seven NMOS transistor MN7 are both 0, the drain-source current is 0, no current flows, and the output signal of the preamplifier is continuously sampled to the cross-coupling capacitor; the gate voltage of the PMOS transistor is reset to the ground GND , so that in the next comparison stage of the comparator, the PMOS setup time is faster, and the PMOS speed is increased, thereby increasing the speed of the comparator; at this time, the differential output is reset to the ground GND at the same time.

When the clock signal Latch is at a low potential, as shown in Figure 4, both the switch tube and the reset tube are turned off. At this time, the connection between the preamplifier and the latch is disconnected, and the comparator enters the comparison stage. Before the switch tube is turned off The sampled voltages at the last moment are compared. At this time, the cross-coupling capacitor acts as a level shifter, raising the sum of the gate-source voltages of NMOS and PMOS to higher than VDD. It is now assumed that the gate voltage of the sixth NMOS transistor MN6 is slightly higher than the gate voltage of the seventh NMOS transistor MN7, and the drain-source current of the sixth NMOS transistor MN6 increases to reduce the voltage _{at the V outp terminal} . The drain-source current of the seven NMOS transistors MN7 will decrease, so that the voltage at the V _outn terminal will further increase. The two amplifying units form a positive feedback structure, and due to the positive feedback effect, the signal difference can be quickly enlarged so that one end is close to the power supply VDD, and the other end is close to the ground GND.

Therefore, according to the characteristics of the existing latching comparator, the present invention increases the gate-source voltage V _GS of the MOS transistor, increases the transconductance gm, and resets the gate voltage of the PMOS transistor to ground by inserting a cross-coupling capacitor and a reset transistor into the latch. Improve the speed of the PMOS, and then achieve the purpose of increasing the speed of the comparator; at the same time, adding a pre-amplifier can provide a certain gain while ensuring the speed of the pre-amplifier, reduce the input offset of the comparator, and at the same time, the input and output of the comparator can be processed. isolation to reduce kickback noise. Therefore, while improving the speed of the comparator, the effect of reducing the offset of the comparator is achieved, which is used for the high-speed high-precision analog-to-digital converter.

Claims (3)

1. a high-speed low-offset latching comparator, is characterized in that, comprises: The pre-amplifier is used to amplify the input differential signal and load it into the latch input to isolate the input signal and the output signal; The latch is connected with the preamplifier and used to compare the differential signal amplified by the preamplifier; The preamplifier is composed of a differential input pair and a load resistor; The latch is composed of two end-to-end amplifying units, each amplifying unit is coupled via a cross-coupling capacitor, the input end is controlled by a switch tube, and the output end of each amplifying unit is reset to ground by a reset tube, The switch tube and the reset tube receive the same clock signal to be turned on or off synchronously, which is a reset stage or a comparison stage, respectively. 2. The high-speed low-offset latch comparator according to claim 1, wherein the pre-amplifier comprises a first NMOS transistor (MN1), a second NMOS transistor (MN2), and a third NMOS transistor (MN3). ), a first load resistor (R1) and a second load resistor (R2); wherein the first NMOS transistor (MN1) and the second NMOS transistor (MN2) are differential input pairs, the first NMOS transistor (MN1) and the second NMOS transistor The gate of the tube (MN2) receives the differential input signal respectively; the third NMOS tube (MN3) is used as a bias current source, its gate is connected to the bias voltage, its source is grounded, and its drain is connected to the first NMOS tube respectively (MN1) and the source of the second NMOS transistor (MN2) are used to provide bias current; the drain of the first NMOS transistor (MN1) is connected to the power supply through the first resistor (R1), and the second NMOS transistor (MN2) passes through The second load resistor (R2) is connected to the power supply, and the connection point between the first NMOS transistor (MN1) and the first resistor (R1), and the connection point between the second NMOS transistor (MN2) and the second load resistor (R2) are the front Differential signal output of the preamplifier. 3. The high-speed low-offset latch comparator according to claim 2, wherein the latch comprises a first PMOS transistor (MP1), a second PMOS transistor (MP2), and a third NMOS transistor (MN3) , the fourth NMOS transistor (MN4), the fifth NMOS transistor (MN5), the sixth NMOS transistor (MN6), the seventh NMOS transistor (MN7), the eighth NMOS transistor (MN8), the ninth NMOS transistor (MN9), the A coupling capacitor (C1) and a second coupling capacitor (C2); wherein, the fourth NMOS transistor (MN4) and the fifth NMOS transistor (MN5) are switch transistors, and the drain of the fourth NMOS transistor (MN4) is connected to the first NMOS The drain of the transistor (MN1), the drain of the fifth NMOS transistor (MN5) is connected to the drain of the second NMOS transistor (MN2), and the gates of the fourth NMOS transistor (MN4) and the fifth NMOS transistor (MN5) are connected to the same clock signal; The sixth NMOS transistor (MN6) and the first PMOS transistor (MP1) constitute a first amplifying unit. The source of the first PMOS transistor (MP1) is connected to the power supply, and its drain is connected to the drain of the sixth NMOS transistor (MN6). The gate of a PMOS transistor (MP1) is connected to the drain of the second PMOS transistor (MP2); the gate of the sixth NMOS transistor (MN6) is connected to the source of the fourth NMOS transistor (MN4), and the sixth NMOS transistor (MN6) The source is grounded; the gate of the sixth NMOS transistor (MN6) and the gate of the first PMOS transistor (MP1) are coupled through a first coupling capacitor (C1); The seventh NMOS transistor (MN7) and the second PMOS transistor (MP2) constitute a second amplifying unit. The source of the second PMOS transistor (MP2) is connected to the power supply, and its drain is connected to the drain of the seventh NMOS transistor (MN7). The gates of the two PMOS transistors (MP2) are connected to the drain of the first PMOS transistor (MP1); the gate of the seventh NMOS transistor (MN7) is connected to the source of the fifth NMOS transistor (MN5), and the seventh NMOS transistor (MN7) The source is grounded; the gate of the seventh NMOS transistor (MN7) and the gate of the second PMOS transistor (MP2) are coupled through a second coupling capacitor (C2); The connection point of the gate of the first PMOS transistor (MP1), the drain of the seventh NMOS transistor (MN7) and the drain of the second PMOS transistor (MP2), and the gate of the second PMOS transistor (MP2), the sixth NMOS transistor (MN6) ) The connection point between the drain and the drain of the first PMOS tube (MP1) is the two output ends of the latch; The eighth NMOS transistor (MN8) and the ninth NMOS transistor (MN9) are reset transistors, the drain of the eighth NMOS transistor (MN8) is connected to the drain of the first PMOS transistor (MP1), and the eighth NMOS transistor ( The gate of MN8) is connected to the gate of the fourth NMOS transistor (MN4), and the source of the eighth NMOS transistor (MN8) is grounded; the drain of the ninth NMOS transistor (MN9) is connected to the drain of the second PMOS transistor (MP2). The drain, the gate of the ninth NMOS transistor (MN9) is connected to the gate of the fifth NMOS transistor (MN5), and the source of the ninth NMOS transistor (MN9) is grounded.

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