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CN112885802A - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

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Publication number
CN112885802A
CN112885802A CN201911205447.1A CN201911205447A CN112885802A CN 112885802 A CN112885802 A CN 112885802A CN 201911205447 A CN201911205447 A CN 201911205447A CN 112885802 A CN112885802 A CN 112885802A
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CN
China
Prior art keywords
layer
metal
solder
bump
forming
Prior art date
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Pending
Application number
CN201911205447.1A
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English (en)
Inventor
庄凌艺
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Publication date
Application filed by Changxin Memory Technologies Inc filed Critical Changxin Memory Technologies Inc
Priority to CN201911205447.1A priority Critical patent/CN112885802A/zh
Priority to PCT/CN2020/096085 priority patent/WO2021103489A1/zh
Priority to US17/429,592 priority patent/US11855032B2/en
Priority to EP20893357.2A priority patent/EP3940772B1/en
Publication of CN112885802A publication Critical patent/CN112885802A/zh
Pending legal-status Critical Current

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Abstract

本公开涉及半导体技术领域，提出了一种半导体结构及其制造方法，半导体结构包括半导体基底、金属焊盘、凸块、第一焊料层、金属阻绝层以及第二焊料层，金属焊盘设置于半导体基底上；凸块设置于金属焊盘上；第一焊料层设置于凸块远离金属焊盘的一侧；金属阻绝层设置于第一焊料层远离凸块的一侧，金属阻绝层具有相隔离的第一容纳槽和第二容纳槽，第一容纳槽的槽口朝向远离第一焊料层的方向，第一焊料层设置于第二容纳槽内；第二焊料层设置于第一容纳槽内，且第二焊料层的部分凸出第一容纳槽的槽口。由于第一焊料层和第二焊料层具有回流高温熔融可伸缩的特性，由此自动进行高度调整，从而可以减少回流后，因受封装基板变形导致的非润湿的问题。

Description

半导体结构及其制造方法
技术领域
本公开涉及半导体技术领域，尤其涉及一种半导体结构及其制造方法。
背景技术
随着集成电路的功能越来越强、性能和集成度越来越高，以及新型的集成电路出现，封装技术在集成电路产品中扮演着越来越重要的角色，在整个电子系统的价值中所占的比例越来越大。凸点互连技术，以其良好的电学性能、抗电迁移能力，正成为下一代芯片窄间距互连的关键技术。
现有技术中，芯片倒装焊接过程中，封装基板受热会出现翘曲，芯片和基板会出现高度差，爬锡造成焊料量不足导致非润湿的问题，而焊料量太多又会导致凸块间焊料桥接的问题。
发明内容
本公开的一个主要目的在于克服上述现有技术的至少一种缺陷，提供一种半导体结构及其制造方法。
根据本发明的第一个方面，提供了一种半导体结构，包括：
半导体基底；
金属焊盘，设置于半导体基底上；
凸块，设置于金属焊盘上；
第一焊料层，设置于凸块远离金属焊盘的一侧；
金属阻绝层，设置于第一焊料层远离凸块的一侧，金属阻绝层具有相隔离的第一容纳槽和第二容纳槽，第一容纳槽的槽口朝向远离第一焊料层的方向，第一焊料层设置于第二容纳槽内；
第二焊料层，设置于第一容纳槽内，且第二焊料层的部分凸出第一容纳槽的槽口。
在本发明的一个实施例中，金属阻绝层的截面为H型。
在本发明的一个实施例中，金属阻绝层与凸块间隔设置，金属阻绝层与凸块之间均设置有第一焊料层。
在本发明的一个实施例中，第一容纳槽内均设置有第二焊料层，第二容纳槽内均设置有第一焊料层。
在本发明的一个实施例中，凸块为铜柱，半导体结构还包括：
凸块下金属层，凸块下金属层的至少部分夹设于金属焊盘与凸块之间。
在本发明的一个实施例中，半导体结构还包括：
第一保护层，设置于半导体基底上，第一保护层具有第一开口，第一开口裸露部分金属焊盘。
在本发明的一个实施例中，半导体结构还包括：
第二保护层，设置于第一保护层上，第二保护层具有第二开口，第二开口的口径小于或等于第一开口的口径；
其中，凸块下金属层至少覆盖第二开口的底面及侧壁面，凸块下金属层的至少部分设置于第二开口内。
根据本发明的第二个方面，提供了一种半导体结构的制造方法，包括：
提供半导体基底，并在半导体基底上形成金属焊盘；
在金属焊盘上形成凸块；
在凸块远离金属焊盘的一侧形成第一焊料层；
在第一焊料层远离凸块的一侧形成金属阻绝层，金属阻绝层具有相隔离的第一容纳槽和第二容纳槽，第一容纳槽的槽口朝向远离第一焊料层的方向，第一焊料层设置于第二容纳槽内；
在第一容纳槽内形成第二焊料层，并且使得第二焊料层的部分凸出第一容纳槽的槽口。
在本发明的一个实施例中，在形成凸块之前，制造方法还包括：
在金属焊盘上形成凸块下金属层；
其中，凸块下金属层的至少部分夹设于金属焊盘与凸块之间。
在本发明的一个实施例中，在形成凸块之前，制造方法还包括：
在半导体基底上形成第一保护层；
其中，第一保护层具有第一开口，第一开口裸露部分金属焊盘。
在本发明的一个实施例中，形成第一保护层之后，制造方法还包括：
在第一保护层和金属焊盘的上表面形成第二保护层；
在形成第二保护层之后，在金属焊盘和第二保护层上形成凸块下金属层；
其中，第二保护层具有第二开口，第二开口的口径小于或等于第一开口的口径，凸块下金属层至少覆盖第二开口的底面及侧壁面，凸块下金属层的至少部分设置于第二开口内。
在本发明的一个实施例中，在形成凸块之前，制造方法还包括：
在半导体基底上与凸块以及第一焊料层对应的位置之外的部分处形成第一光阻层；
在形成凸块以及第一焊料层之后，去除第一光阻层。
在本发明的一个实施例中，在形成金属阻绝层之前，制造方法还包括：
在形成有第一焊料层的半导体基底上形成第一掩模层；
采用光刻工艺光刻第一掩模层以露出第一焊料层的部分；
采用化学酸蚀工艺蚀刻第一焊料层的部分，然后去除第一掩模层；
形成第二掩模层；
采用光刻工艺光刻第二掩模层以露出第一焊料层，并在第一焊料层以及第二掩模层上形成金属阻绝层，其中，金属阻绝层与凸块之间均设置有第一焊料层。
在本发明的一个实施例中，在形成金属阻绝层之后，制造方法还包括：
在金属阻绝层上与第一焊料层对应的位置处形成第二光阻层；
蚀刻未被第二光阻层覆盖位置处的金属阻绝层；
去除第二光阻层；
在第一容纳槽内填充焊料形成第二焊料层；
去除第二掩模层。
在本发明的一个实施例中，在形成金属阻绝层之后，制造方法还包括：
在金属阻绝层上与第一焊料层对应的位置处之外的部分形成第三光阻层；
在第一容纳槽内填充焊料形成第二焊料层；
去除第三光阻层；
蚀刻未被焊料覆盖位置处的金属阻绝层；
去除第二掩模层。
本发明的半导体结构由半导体基底、金属焊盘、凸块、第一焊料层、金属阻绝层以及第二焊料层组成，金属阻绝层的第一容纳槽和第二容纳槽内分别设置有第二焊料层和第一焊料层。由于第二焊料层和第一焊料层被包裹在金属阻绝层内，从而可以改善倒装芯片焊接过程中，爬锡时造成焊料量不足导致的非润湿的问题，以及焊料量太多导致的焊料桥接的问题。
附图说明
通过结合附图考虑以下对本公开的优选实施方式的详细说明，本公开的各种目标，特征和优点将变得更加显而易见。附图仅为本公开的示范性图解，并非一定是按比例绘制。在附图中，同样的附图标记始终表示相同或类似的部件。其中：
图1是根据一示例性实施方式示出的一种半导体结构的结构示意图；
图2是根据另一示例性实施方式示出的一种半导体结构的结构示意图；
图3是根据一示例性实施方式示出的一种半导体结构与封装基板的组装结构示意图；
图4是根据一示例性实施方式示出的一种利用半导体结构的制备方法形成凸块下金属层后的结构示意图；
图5是根据一示例性实施方式示出的一种利用半导体结构的制备方法形成第一焊料层后的结构示意图；
图6是根据一示例性实施方式示出的一种利用半导体结构的制备方法去除第一光阻层后的结构示意图；
图7是根据一示例性实施方式示出的一种利用半导体结构的制备方法形成第一掩模层后的结构示意图；
图8是根据一示例性实施方式示出的一种利用半导体结构的制备方法光刻第一掩模层后的结构示意图；
图9是根据一示例性实施方式示出的一种利用半导体结构的制备方法酸蚀第一掩模层后的结构示意图；
图10是根据一示例性实施方式示出的一种利用半导体结构的制备方法去除第一掩模层后的结构示意图；
图11是根据一示例性实施方式示出的一种利用半导体结构的制备方法形成金属阻绝层后的结构示意图；
图12是根据一示例性实施方式示出的一种利用半导体结构的制备方法形成第二光阻层后的结构示意图；
图13是根据一示例性实施方式示出的一种利用半导体结构的制备方法蚀刻金属阻绝层后的结构示意图；
图14是根据一示例性实施方式示出的一种利用半导体结构的制备方法去除第二光阻层后的结构示意图；
图15是根据一示例性实施方式示出的一种利用半导体结构的制备方法形成第二焊料层后的结构示意图；
图16是根据一示例性实施方式示出的一种利用半导体结构的制备方法蚀刻第二掩模层后的结构示意图。
附图标记说明如下：
1、封装基板；10、金属焊盘；11、第一光阻层；12、第一掩模层；13、第二掩模层；14、第二光阻层；20、半导体基底；30、凸块；40、第一焊料层；41、去除空间；50、金属阻绝层；51、第一容纳槽；52、第二容纳槽；60、第二焊料层；70、凸块下金属层；80、第一保护层；90、第二保护层。
具体实施方式
体现本公开特征与优点的典型实施例将在以下的说明中详细叙述。应理解的是本公开能够在不同的实施例上具有各种的变化，其皆不脱离本公开的范围，且其中的说明及附图在本质上是作说明之用，而非用以限制本公开。
在对本公开的不同示例性实施方式的下面描述中，参照附图进行，附图形成本公开的一部分，并且其中以示例方式显示了可实现本公开的多个方面的不同示例性结构，系统和步骤。应理解的是，可以使用部件，结构，示例性装置，系统和步骤的其他特定方案，并且可在不偏离本公开范围的情况下进行结构和功能性修改。而且，虽然本说明书中可使用术语“之上”，“之间”，“之内”等来描述本公开的不同示例性特征和元件，但是这些术语用于本文中仅出于方便，例如根据附图中的示例的方向。本说明书中的任何内容都不应理解为需要结构的特定三维方向才落入本公开的范围内。
本发明的一个实施例提供了一种半导体结构，请参考图1和图2，半导体结构包括：半导体基底20；金属焊盘10，设置于半导体基底20上；凸块30，设置于金属焊盘10上；第一焊料层40，设置于凸块30远离金属焊盘10的一侧；金属阻绝层50，设置于第一焊料层40远离凸块30的一侧，金属阻绝层50具有相隔离的第一容纳槽51和第二容纳槽52，第一容纳槽51的槽口朝向远离第一焊料层40的方向，第一焊料层40设置于第二容纳槽52内；第二焊料层60，设置于第一容纳槽51内，且第二焊料层60的部分凸出第一容纳槽51的槽口。
本发明一个实施例的半导体结构由半导体基底20、金属焊盘10、凸块30、第一焊料层40、金属阻绝层50以及第二焊料层60组成，金属焊盘10设置在半导体基底20的上表面，然后向上依次设置有凸块30、第一焊料层40、金属阻绝层50以及第二焊料层60。由于第二焊料层60和第一焊料层40被包裹在金属阻绝层50内，从而可以改善倒装芯片焊接过程中，爬锡时造成焊料量不足导致的非润湿的问题，以及焊料量太多导致的焊料桥接的问题。
在一个实施例中，如图3所示，半导体结构为一种可伸缩的金属在倒装芯片焊接过程中，封装基板1受热造成的翘曲，而第一焊料层40具有回流高温熔融可伸缩的特性，由此自动进行高度调整，从而可以减少回流后，因受封装基板1变形，导致的非润湿的问题。
在一个实施例中，金属阻绝层50的第一容纳槽51和第二容纳槽52均仅具有一个开口，即第一容纳槽51和第二容纳槽52均为半封闭槽，在倒装回流过程中，金属阻绝层50可以阻挡焊料的流动并且起到引流作用，从而不会出现第二焊料层60大量扩散，避免了出现焊料桥接的问题，以此实现良率提升的目标。
在一个实施例中，第一焊料层40和第二焊料层60可以为铅、锡及银中的一种或包含上述任意一种焊料金属的合金。例如，第一焊料层40，和/或第二焊料层60的材料可以为含锡量91.5％～98.5％，含银量8.5％～1.5％的合金。可选地，第一焊料层40，和/或第二焊料层60的材料可以为含锡量93.2％～96.5％，含银量6.8％～3.5％的合金，第一焊料层40，和/或第二焊料层60的材料可以为含锡量98.2％～98.5％，含银量1.8％～1.5％的合金。
在一个实施例中，半导体基底20包括半导体衬底及若干IC线路及绝缘层。金属焊盘10的材料可以为铝或铜，但不局限于此。
在一个实施例中，金属阻绝层50的截面为H型。金属阻绝层50的截面参考图1和图2可以理解为金属阻绝层50的纵向截面。金属阻绝层50为一个中间隔开的桶状结构，第二焊料层60和第一焊料层40彼此不接触。
在一个实施例中，金属阻绝层50与凸块30间隔设置，金属阻绝层50与凸块30之间均设置有第一焊料层40。第一焊料层40具有T形截面，即小端位于第二容纳槽52内，而大端位于第二容纳槽52外。
在一个实施例中，第一容纳槽51内均设置有第二焊料层60，第二容纳槽52内均设置有第一焊料层40。其中，第二焊料层60凸出第一容纳槽51的部分可以覆盖金属阻绝层50的局部上表面，或完全覆盖金属阻绝层50的上表面，也不排除完全不覆盖金属阻绝层50的上表面。
在一个实施例中，金属阻绝层50的材料可以包括镍。
在一个实施例中，凸块30为铜柱，半导体结构还包括：凸块下金属层70，凸块下金属层70的至少部分夹设于金属焊盘10与凸块30之间。凸块下金属层70的金属材料层可包括Ti层、TiW层及Cu层。凸块下金属层70与金属焊盘10电连接。凸块下金属层70使得凸块30不与金属焊盘10直接接触。
在一个实施例中，半导体结构还包括：第一保护层80，设置于半导体基底20上，第一保护层80具有第一开口，第一开口裸露部分金属焊盘10，即第一保护层80覆盖金属焊盘10的周向外边缘。其中，第一保护层80的材料可以为二氧化硅及氮化硅中的一种或其组合。
在一个实施例中，第一保护层80覆盖部分金属焊盘10以及金属焊盘10之外的半导体基底20区域。
在一个实施例中，半导体结构还包括：第二保护层90，设置于第一保护层80上，第二保护层90具有第二开口，第二开口的口径小于或等于第一开口的口径；其中，凸块下金属层70至少覆盖第二开口的底面及侧壁面，凸块下金属层70的至少部分设置于第二开口内。第二保护层90的材料可以为聚酰亚胺。
在一个实施例中，凸块下金属层70设置在部分第二保护层90以及裸露出来的金属焊盘10上。在一个实施例中，凸块下金属层70可以包裹凸块30，即凸块30均位于凸块下金属层70形成的开口腔内，凸块下金属层70的槽口所在平面与第一焊料层40的底面在同一个平面上。
在一个实施例中，如图1所示，半导体结构由半导体基底20、金属焊盘10、凸块30、第一焊料层40、金属阻绝层50、第二焊料层60、凸块下金属层70、第一保护层80以及第二保护层90组成，第一保护层80覆盖在金属焊盘10上，且遮挡金属焊盘10的部分，而第二保护层90设置在第一保护层80上，且覆盖金属焊盘10的部分，第二保护层90以及第一保护层80覆盖金属焊盘10的位置相对接，即第一保护层80均位于第二保护层90的下方。第二保护层90并不覆盖金属焊盘10的中部，而凸块下金属层70通过物理气相沉积方式将Ti层、TiW层及Cu层等金属材料层设置在第二保护层90以及金属焊盘10上，利用Ti层能够实现粘附和阻挡金属铜进入半导体基底20，利用Cu层能形成电镀的电极。凸块30具有T形截面，即小端位于凸块下金属层70内，而大端位于凸块下金属层70外。
在另一个实施例中，如图2所示，半导体结构由半导体基底20、金属焊盘10、凸块30、第一焊料层40、金属阻绝层50、第二焊料层60、凸块下金属层70以及第一保护层80组成，第一保护层80覆盖在金属焊盘10上，且遮挡金属焊盘10的部分。凸块下金属层70通过物理气相沉积方式将Ti层、TiW层及Cu层等金属材料层设置在金属焊盘10上，利用Ti层能够实现粘附和阻挡金属铜进入半导体基底20，利用Cu层能形成电镀的电极。凸块30具有矩形截面，凸块30位于凸块下金属层70和第一焊料层40之间。
本发明的一个实施例还提供了一种半导体结构的制造方法，包括：提供半导体基底20，并在半导体基底20上形成金属焊盘10；在金属焊盘10上形成凸块30；在凸块30远离金属焊盘10的一侧形成第一焊料层40；在第一焊料层40远离凸块30的一侧形成金属阻绝层50，金属阻绝层50具有相隔离的第一容纳槽51和第二容纳槽52，第一容纳槽51的槽口朝向远离第一焊料层40的方向，第一焊料层40设置于第二容纳槽52内；在第一容纳槽51内形成第二焊料层60，并且使得第二焊料层60的部分凸出第一容纳槽51的槽口。
在一个实施例中，在形成凸块30之前，制造方法还包括：在金属焊盘10上形成凸块下金属层70；其中，凸块下金属层70的至少部分夹设于金属焊盘10与凸块30之间。
在一个实施例中，在形成凸块30之前，制造方法还包括：在半导体基底20上形成第一保护层80；其中，第一保护层80具有第一开口，第一开口裸露部分金属焊盘10。
在一个实施例中，形成第一保护层80之后，制造方法还包括：在第一保护层80和金属焊盘10的上表面形成第二保护层90；在形成第二保护层90之后，在金属焊盘10和第二保护层90上形成凸块下金属层70；其中，第二保护层90具有第二开口，第二开口的口径小于或等于第一开口的口径，凸块下金属层70至少覆盖第二开口的底面及侧壁面，凸块下金属层70的至少部分设置于第二开口内。
在一个实施例中，在形成凸块30之前，制造方法还包括：在半导体基底20上与凸块30以及第一焊料层40对应的位置之外的部分处形成第一光阻层11；在形成凸块30以及第一焊料层40之后，去除第一光阻层11。
在一个实施例中，在形成金属阻绝层50之前，制造方法还包括：在形成有第一焊料层40的半导体基底20上形成第一掩模层12；采用光刻工艺光刻第一掩模层12以露出第一焊料层40的部分；采用化学酸蚀工艺蚀刻第一焊料层40的部分，然后去除第一掩模层12；形成第二掩模层13；采用光刻工艺光刻第二掩模层13以露出第一焊料层40，并在第一焊料层40以及第二掩模层13上形成金属阻绝层50，其中，金属阻绝层50与凸块30之间均设置有第一焊料层40。
在一个实施例中，在形成金属阻绝层50之后，制造方法还包括：在金属阻绝层50上与第一焊料层40对应的位置处形成第二光阻层14；蚀刻未被第二光阻层14覆盖位置处的金属阻绝层50；去除第二光阻层14；在第一容纳槽51内填充焊料形成第二焊料层60；去除第二掩模层13。
在一个实施例中，在形成金属阻绝层50之后，制造方法还包括：在金属阻绝层50上与第一焊料层40对应的位置处之外的部分形成第三光阻层；在第一容纳槽51内填充焊料形成第二焊料层60；去除第三光阻层；蚀刻未被焊料覆盖位置处的金属阻绝层50；去除第二掩模层13。
在一个实施例中，针对一种半导体结构的制造方法具体步骤包括：
如图4所示，在金属焊盘10上形成第一保护层80，使用沉积工艺在第一保护层80和金属焊盘10的上表面形成第二保护层90，采用光刻工艺在第二保护层90中预制备凸块30的位置形成开孔，在金属焊盘10以及第二保护层90上沉积金属材料形成凸块下金属层70，其中，凸块下金属层70覆盖全部的第二保护层90并且覆盖第二保护层90的开孔。其中，第一保护层80的材料可以为二氧化硅及氮化硅中的一种或其组合，第二保护层90的材料可以为聚酰亚胺。凸块下金属层70的金属材料层可包括Ti层、TiW层及Cu层，凸块下金属层70通过物理气相沉积(PVD)方式形成在金属焊盘10以及第二保护层90上，利用凸块下金属层70的Ti层能够实现粘附和阻挡金属铜进入半导体基底20及金属焊盘10内，利用凸块下金属层70的Cu层能作为形成电镀铜柱(凸块30)的电极。
如图5所示，在第二保护层90上与凸块30以及第一焊料层40对应的位置之外的部分处形成第一光阻层11，即在第一光阻层11的中部预留出形成凸块30以及第一焊料层40的空间，然后电镀凸块30以及第一焊料层40。其中，第一光阻层11可以为光刻胶层，涂布光刻胶层后，对光刻胶层进行曝光，显影，即可以形成用于设置凸块30以及第一焊料层40的空间。第一焊料层40的材料可以为铅、锡及银中的一种或包含上述任意一种焊料金属的合金。例如，第一焊料层40的材料可以为含含锡量91.5％～98.5％，含银量8.5％～1.5％的合金。可选地，第一焊料层40的材料可以为含锡量93.2％～96.5％，含银量6.8％～3.5％的合金，第一焊料层40的材料可以为含锡量98.2％～98.5％，含银量1.8％～1.5％的合金，凸块30为铜柱。
如图6所示，形成电镀凸块30以及第一焊料层40后去除第一光阻层11。
如图7所示，在形成有第一焊料层40的半导体基底20上形成第一掩模层12，第一掩模层12覆盖第一焊料层40以及凸块下金属层70。其中，第一掩模层12可以为聚酰亚胺层。
如图8所示，光刻第一掩模层12以露出第一焊料层40的部分顶面。
如图9所示，利用化学酸蚀将第一焊料层40蚀刻一部分，以形成去除空间41。
如图10所示，去除第一掩模层12。
如图11所示，形成第二掩模层13，第二掩模层13覆盖第一焊料层40以及凸块下金属层70，光刻第二掩模层13以露出第一焊料层40，利用物理气相沉积(Physical VaporDeposition，PVD)技术将金属阻绝层50沉积在第二掩模层13以及第一焊料层40的上方。其中，金属阻绝层50可以为镍层，在需要增厚金属阻绝层50的场合则再采用电镀工艺使得镍层厚度增加。其中，第二掩模层13可以为聚酰亚胺层。
如图12所示，在金属阻绝层50上与第一焊料层40对应的位置处形成第二光阻层14。其中，第二光阻层14将第一焊料层40的上方覆盖，作为光刻金属阻绝层50时的掩模，第二光阻层14可以为光刻胶层。
如图13所示，蚀刻未被第二光阻层14覆盖位置处的金属阻绝层50的金属材料。
如图14所示，去除第二光阻层14，以在金属阻绝层50上露出第一容纳槽51。
如图15所示，在第一容纳槽51内填充焊料形成第二焊料层60，第二焊料层60的高度高于金属阻绝层50。其中，第二焊料层60的材料可以为铅、锡及银中的一种或包含上述任意一种焊料金属的合金。例如，第二焊料层60的材料可以为含锡量91.5％～98.5％，含银量8.5％～1.5％的合金。可选地，第二焊料层60的材料可以为含锡量93.2％～96.5％，含银量6.8％～3.5％的合金，第二焊料层60的材料可以为含锡量98.2％～98.5％，含银量1.8％～1.5％的合金。
如图16所示，蚀刻第二掩模层13。然后蚀刻凸块下金属层70，最后采用高温回流工艺于金属阻绝层50的表面形成焊料凸点，即形成如图1所示的半导体结构。
在另一个实施例中，针对一种半导体结构的制造方法具体步骤包括：
在完成图4至图11的制备过程后，即利用物理气相沉积(Physical VaporDeposition，PVD)技术将金属阻绝层50沉积在第二掩模层13以及第一焊料层40的上方。
在金属阻绝层50的金属材料上与第一焊料层40对应的位置处之外的部分形成第三光阻层。其中，第三光阻层可以为光刻胶层。
在第一容纳槽51内填充焊料形成第二焊料层60，第二焊料层60的高度高于金属阻绝层50但低于第三光阻层。其中，焊料层的材料可以为铅、锡及银中的一种或包含上述任意一种焊料金属的合金。例如，第二焊料层60的材料可以为含锡量91.5％～98.5％，含银量8.5％～1.5％的合金。可选地，第二焊料层60的材料可以为含锡量93.2％～96.5％，含银量6.8％～3.5％的合金，第二焊料层60的材料可以为含锡量98.2％～98.5％，含银量1.8％～1.5％的合金。
去除第三光阻层。
蚀刻第二掩模层13。然后蚀刻凸块下金属层70，最后采用高温回流工艺于金属阻绝层50的表面形成焊料凸点，即形成如图1所示的半导体结构。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本发明的其它实施方案。本发明旨在涵盖本发明的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本发明的一般性原理并包括本发明未公开的本技术领域中的公知常识或惯用技术手段。说明书和示例实施方式仅被视为示例性的，本发明的真正范围和精神由下面的权利要求指出。
应当理解的是，本发明并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本发明的范围仅由所附的权利要求来限制。

Claims (15)

1.一种半导体结构，其特征在于，包括：
半导体基底；
金属焊盘，设置于所述半导体基底上；
凸块，设置于所述金属焊盘上；
第一焊料层，设置于所述凸块远离所述金属焊盘的一侧；
金属阻绝层，设置于所述第一焊料层远离所述凸块的一侧，所述金属阻绝层具有相隔离的第一容纳槽和第二容纳槽，所述第一容纳槽的槽口朝向远离所述第一焊料层的方向，所述第一焊料层设置于所述第二容纳槽内；
第二焊料层，设置于所述第一容纳槽内，且所述第二焊料层的部分凸出所述第一容纳槽的槽口。
2.根据权利要求1所述的半导体结构，其特征在于，所述金属阻绝层的截面为H型。
3.根据权利要求1所述的半导体结构，其特征在于，所述金属阻绝层与所述凸块间隔设置，所述金属阻绝层与所述凸块之间均设置有所述第一焊料层。
4.根据权利要求1所述的半导体结构，其特征在于，所述第一容纳槽内均设置有所述第二焊料层，所述第二容纳槽内均设置有所述第一焊料层。
5.根据权利要求1至4中任一项所述的半导体结构，其特征在于，所述凸块为铜柱，所述半导体结构还包括：
凸块下金属层，所述凸块下金属层的至少部分夹设于所述金属焊盘与所述凸块之间。
6.根据权利要求5所述的半导体结构，其特征在于，所述半导体结构还包括：
第一保护层，设置于所述半导体基底上，所述第一保护层具有第一开口，所述第一开口裸露部分所述金属焊盘。
7.根据权利要求6所述的半导体结构，其特征在于，所述半导体结构还包括：
第二保护层，设置于所述第一保护层上，所述第二保护层具有第二开口，所述第二开口的口径小于或等于所述第一开口的口径；
其中，所述凸块下金属层至少覆盖所述第二开口的底面及侧壁面，所述凸块下金属层的至少部分设置于所述第二开口内。
8.一种半导体结构的制造方法，其特征在于，包括：
提供半导体基底，并在所述半导体基底上形成金属焊盘；
在所述金属焊盘上形成凸块；
在所述凸块远离所述金属焊盘的一侧形成第一焊料层；
在所述第一焊料层远离所述凸块的一侧形成金属阻绝层，所述金属阻绝层具有相隔离的第一容纳槽和第二容纳槽，所述第一容纳槽的槽口朝向远离所述第一焊料层的方向，所述第一焊料层设置于所述第二容纳槽内；
在所述第一容纳槽内形成第二焊料层，并且使得所述第二焊料层的部分凸出所述第一容纳槽的槽口。
9.根据权利要求8所述的制造方法，其特征在于，在形成所述凸块之前，所述制造方法还包括：
在所述金属焊盘上形成凸块下金属层；
其中，所述凸块下金属层的至少部分夹设于所述金属焊盘与所述凸块之间。
10.根据权利要求9所述的制造方法，其特征在于，在形成所述凸块之前，所述制造方法还包括：
在所述半导体基底上形成第一保护层；
其中，所述第一保护层具有第一开口，所述第一开口裸露部分所述金属焊盘。
11.根据权利要求10所述的制造方法，其特征在于，形成所述第一保护层之后，所述制造方法还包括：
在所述第一保护层和所述金属焊盘的上表面形成第二保护层；
在形成所述第二保护层之后，在所述金属焊盘和所述第二保护层上形成所述凸块下金属层；
其中，所述第二保护层具有第二开口，所述第二开口的口径小于或等于所述第一开口的口径，所述凸块下金属层至少覆盖所述第二开口的底面及侧壁面，所述凸块下金属层的至少部分设置于所述第二开口内。
12.根据权利要求8至11中任一项所述的制造方法，其特征在于，在形成所述凸块之前，所述制造方法还包括：
在所述半导体基底上与所述凸块以及所述第一焊料层对应的位置之外的部分处形成第一光阻层；
在形成所述凸块以及所述第一焊料层之后，去除所述第一光阻层。
13.根据权利要求8至11中任一项所述的制造方法，其特征在于，在形成所述金属阻绝层之前，所述制造方法还包括：
在形成有所述第一焊料层的半导体基底上形成第一掩模层；
采用光刻工艺光刻所述第一掩模层以露出所述第一焊料层的部分；
采用化学酸蚀工艺蚀刻所述第一焊料层的部分，然后去除所述第一掩模层；
形成第二掩模层；
采用光刻工艺光刻所述第二掩模层以露出所述第一焊料层，并在所述第一焊料层以及所述第二掩模层上形成所述金属阻绝层，其中，所述金属阻绝层与所述凸块之间均设置有所述第一焊料层。
14.根据权利要求13所述的制造方法，其特征在于，在形成所述金属阻绝层之后，所述制造方法还包括：
在所述金属阻绝层上与所述第一焊料层对应的位置处形成第二光阻层；
蚀刻未被所述第二光阻层覆盖位置处的所述金属阻绝层；
去除所述第二光阻层；
在所述第一容纳槽内填充焊料形成所述第二焊料层；
去除所述第二掩模层。
15.根据权利要求13所述的制造方法，其特征在于，在形成所述金属阻绝层之后，所述制造方法还包括：
在所述金属阻绝层上与所述第一焊料层对应的位置处之外的部分形成第三光阻层；
在所述第一容纳槽内填充焊料形成所述第二焊料层；
去除所述第三光阻层；
蚀刻未被焊料覆盖位置处的所述金属阻绝层；
去除所述第二掩模层。
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US9355980B2 (en) * 2013-09-03 2016-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional chip stack and method of forming the same
US10276539B1 (en) 2017-10-30 2019-04-30 Micron Technology, Inc. Method for 3D ink jet TCB interconnect control
US10483221B2 (en) 2017-10-30 2019-11-19 Micron Technology, Inc. 3DI solder cup
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