CN112865727B - Dynamic bias power amplifier - Google Patents
Dynamic bias power amplifier Download PDFInfo
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- CN112865727B CN112865727B CN202110090071.5A CN202110090071A CN112865727B CN 112865727 B CN112865727 B CN 112865727B CN 202110090071 A CN202110090071 A CN 202110090071A CN 112865727 B CN112865727 B CN 112865727B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
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Abstract
The invention discloses a dynamic bias power amplifier, comprising: the input and matching module is used for carrying out impedance matching and straightening on the input radio frequency signals; the laminated power amplification module is used for amplifying the power of the matched radio frequency signals under the control of the dynamic bias voltage; the output and matching module is used for carrying out impedance matching and straightening on the output radio frequency signals of the laminated power amplification module; and the dynamic bias module is used for generating dynamic bias voltage to the power amplifier tube of the laminated power amplifier module according to the magnitude of the input radio frequency signal.
Description
Technical Field
The present invention relates to a power amplifier, and more particularly, to a dynamically biased power amplifier.
Background
The power amplifier (PowerAmplifier, PA) is used as a key device of the radio frequency front end transmitting link, and the efficiency of the power amplifier affects the system power consumption. In order to improve the communication rate, the 5G communication adopts a 64-QAM modulation technology, and the power amplifier PA needs to work under a higher output power peak-to-average power ratio PAPR, so that the improvement of the power back-off area PAE of the power amplifier PA is important to reduce the power consumption of the system.
Fig. 1 is a circuit configuration diagram of a prior art fixed bias power amplifier. As shown in fig. 1, the conventional fixed bias power amplifier includes an input and matching module 10, a stacked power amplifying module 20, an output and matching module 30, and a fixed bias module 40. The input and matching module 10 consists of an input matching inductance Lin and an input blocking matching capacitance Cin, and is used for completing input matching and blocking; the laminated power amplifier module 20 is composed of a common source NMOS power amplifier tube M 1 Grid isolation resistor R 1 Multistage common-gate NMOS power amplifier M 2 、M 3 、M 4 Isolation resistor R 2 、R 3 、R 4 And a grid grounding capacitor C 2 、C 3 、C 4 The component is used for completing the power amplification of the radio frequency signals; the output and matching module 30 consists of a load inductance Ld and an output matching blocking capacitor Co, and is used for finishing output matching and blocking; the fixed bias module 40 is composed of a plurality of NMOS bias tubes M connected by diodes 5 、M 6 、M 7 、M 8 Composition for supplying common source NMOS power amplifier M under control of reference current Iref 1 Co-grid NMOS power amplifier tube M 2 、M 3 、M 4 A fixed bias voltage is set.
The RF signal RFin is connected to the common end of the input matching inductance Lin and the input blocking matching capacitance Cin, the other end of the input matching inductance Lin is grounded to the RF GND, and the other end of the input blocking matching capacitance Cin is connected to the common source NMOS power amplifier M 1 Gate and isolation resistor R of (2) 1 Is a member of the group; common source NMOS power amplifier M 1 Is connected with the source electrode and the substrate of the radio frequency ground RF GND, and the common-source NMOS power amplifier M 1 Is connected to the drain electrode of the common gate NMOS power amplifier M 2 Common gate NMOS power amplifier M 2 Is connected to the isolation resistor R 2 One end of (2) and the grounded capacitance C of the grid 2 Is a common-gate NMOS power amplifier M 2 Is connected to the drain electrode of the common gate NMOS power amplifier M 3 Common gate NMOS power amplifier M 3 Is connected to the isolation resistor R 3 One end of (2) and the grounded capacitance C of the grid 3 Is a common-gate NMOS power amplifier M 3 Is connected to the drain electrode of the common gate NMOS power amplifier M 4 Common gate NMOS power amplifier M 4 Is connected to the isolation resistor R 4 One end of (2) and the grounded capacitance C of the grid 4 A gate-to-ground capacitor C 2 、C 3 、C 4 The other end of the first electrode is grounded; common-gate NMOS power amplifier M 4 The drain electrode of the output matching blocking capacitor Co is connected with the common end of the load inductance Ld, the other end of the load inductance Ld is connected with the power supply Vdd, and the other end of the output matching blocking capacitor Co is an output end RFout of the power amplifier;
NMOS bias tube M 5 Is connected to the NMOS bias tube M after being short-circuited with the drain electrode and the grid electrode 6 Source and substrate of (a) and isolation resistor R 1 Is arranged at the other end of NMOS bias tube M 5 Is grounded to the source electrode and substrate of the NMOS bias tube M 6 Is connected to the NMOS bias tube M after being short-circuited with the drain electrode and the grid electrode 7 Source and substrate of (a) and isolation resistor R 2 Is arranged at the other end of NMOS bias tube M 7 Is connected to the NMOS bias tube M after being short-circuited with the drain electrode and the grid electrode 8 Source and substrate isolation resistance R 3 Is arranged at the other end of NMOS bias tube M 8 Is connected to the reference current Iref and the other end of the isolation resistor R4 after shorting.
Although the Power amplifier with fixed bias can improve output Power by adopting a 4-FET laminated structure, the Power amplifier needs to adopt fixed bias according to the maximum Power design, and direct current (dc) current meets the requirement of larger current for maximum Power output.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention aims to provide a dynamic bias power amplifier so as to effectively adjust the grid bias voltage of a power amplifier tube according to the input power and control the bias dc current to realize the dynamic adjustment of the self-adaptive power consumption input power and effectively improve the PAE efficiency of a power back-off area.
To achieve the above and other objects, the present invention provides a dynamically biased power amplifier comprising:
the input and matching module is used for carrying out impedance matching and straightening on the input radio frequency signals;
the laminated power amplification module is used for amplifying the power of the matched radio frequency signals under the control of the dynamic bias voltage;
the output and matching module is used for carrying out impedance matching and straightening on the output radio frequency signals of the laminated power amplification module;
the dynamic bias module is used for generating dynamic bias voltage to the power amplifier tube of the laminated power amplifier module according to the magnitude of an input radio frequency signal;
wherein the dynamic biasing module further comprises:
the input detection amplifier is used for collecting input power and carrying out proper equidirectional gain amplification, and converting the input power into radio frequency signal current which is injected into the bias adjustment module; the method comprises the steps of,
the bias adjusting module is used for dynamically adjusting bias voltages of the common-source NMOS power amplifier tube and the common-gate NMOS power amplifier tube of the laminated power amplifying module under the influence of the sampling radio frequency signal output by the input detection amplifier, and the bias adjusting module comprises:
the fixed bias module is used for sequentially adjusting grid drain voltage to bias voltage of each common-grid NMOS power amplifier tube of the laminated power amplifier module under the constraint of reference current to realize grid bias adjustment;
the variable bias module is used for adjusting the grid electrode and drain electrode voltage of the NMOS bias tube according to the injection current, so as to realize the grid electrode bias adjustment of the common source NMOS power amplifier tube of the laminated power amplifier module;
and the clamp is used for protecting that the grid bias is excessively adjusted when the input power is maximum so that each power amplifying tube of the laminated power amplifying module enters a linear region.
Preferably, the fixed bias module comprises a diode-connected sixth NMOS bias tube (M 6 ) Seventh NMOS bias tube (M) 7 ) Eighth NMOS bias tube (M) 8 ) The eighth NMOS bias tube (M 8 ) After being short-circuited, the gate-drain is connected to the reference current (Iref) and is connected to the laminated power amplifier module, the seventh NMOS bias tube (M 7 ) The gate-drain short circuit is connected with the eighth NMOS bias tube (M) 8 ) A source connected to the stacked power amplifier module, and a sixth NMOS bias tube (M 6 ) After the gate and drain are short-circuited, the seventh NMOS bias tube (M 7 ) A source connected to the stacked power amplifier module, and a sixth NMOS bias tube (M 6 ) The source electrode is connected with the variable bias module.
Preferably, the variable bias module comprises an NMOS bias tube (M 5 ) Bias resistor (R) 5 ) Rectifying capacitor (C) 5 ) The bias resistor (R 5 ) One end of the second NMOS bias tube is connected with the second NMOS bias tube (M 6 ) A source, the bias resistor (R 5 ) The other end is connected to the NMOS bias tube (M 5 ) Said rectifying capacitor (C 5 ) Is provided, the clamp, and the stacked power amplification module, the NMOS bias tube (M 5 ) A source and a substrate are connected to the rectifying capacitor (C 5 ) The other end is grounded at the radio frequency.
Preferably, the clamp comprises a first diode (D 1 ) Second diode (D) 2 ) The first diode (D 1 ) Is connected to the bias resistor (R 5 ) Said rectifying capacitor (C 5 ) And the laminated power amplification module, a cathode is connected with the firstTwo diodes (D) 2 ) Is arranged between the first diode (D 2 ) The cathode is grounded at radio frequency.
Preferably, the clamp comprises a current limiting resistor (Rd) and a diode connected first NMOS tube (MD 1 ) Second NMOS tube (MD) 2 ) One end of the current limiting resistor (Rd) is connected with the NMOS bias tube (M) 5 ) The other end of the gate is connected with a first NMOS tube (MD 1 ) Is a drain and gate of a first NMOS transistor (MD 1 ) Is connected with the source electrode and the substrate of the second NMOS tube (MD) 2 ) And the drain and gate of the second NMOS transistor (MD 2 ) Is grounded to the rf ground.
Preferably, the input sense amplifier comprises a sampling dc blocking capacitor (C 9 ) And a single-ended amplifier (Sa), the radio frequency signal RFin being connected to the sampling dc blocking capacitance (C 9 ) One end of the sampling DC blocking capacitor (C 9 ) The other end is connected to the input end of the single-ended amplifier (Sa), and the output end of the single-ended amplifier (Sa) is connected to the NMOS bias tube (M 5 ) Drain of (d), bias resistance (R 5 ) Is connected to one end of the sixth NMOS bias tube (M 6 ) Is provided.
Preferably, the single-ended amplifier (Sa) includes a ninth NMOS transistor (M) 9 ) Tenth NMOS tube (M) 10 ) Ninth self-bias resistor (R) 9 ) Tenth self-bias resistor (R 10 ) The ninth self-bias resistor (R 9 ) And a ninth NMOS tube (M) 9 ) Is connected to the gate of the single-ended amplifier to form the input terminal of the single-ended amplifier, the ninth self-bias resistor (R 9 ) The other end of the transistor is connected with a ninth NMOS tube (M) 9 ) Is a drain electrode of a tenth NMOS transistor (M 10 ) And a tenth self-bias resistor (R) 10 ) A tenth self-bias resistor (R) 10 ) Is connected with the other end of the tenth NMOS tube (M 10 ) Is connected to the drain of the single-ended amplifier to form the output end of the single-ended amplifier, and a ninth NMOS transistor (M 9 ) Tenth NMOS tube (M) 10 ) Is connected to analog ground.
Preferably, the stacked power amplification module comprises a common source NMOS power amplifier tube (M 1 ) And its gate isolation resistor (R) 1 ) Second common gate NMOS powerAmplifying tube (M) 2 ) Third common gate NMOS power amplifier (M) 3 ) Fourth common gate NMOS power amplifier (M) 4 ) And its second isolation resistor (R 2 ) A third isolation resistor (R 3 ) Fourth isolation resistor (R) 4 ) And a second gate grounding capacitance (C 2 ) Third Gate ground capacitor (C) 3 ) Fourth grid grounding capacitor (C) 4 ) The common source NMOS power amplifier (M 1 ) A gate connected to the gate isolation resistor (R 1 ) And is connected to the input and matching module, the source is connected to the radio frequency ground, and the drain is connected to the second common gate NMOS power amplifier (M 2 ) Is arranged between the source and the substrate of the second common gate NMOS power amplifier (M 2 ) Is connected to the second isolation resistor (R 2 ) And a second grounded-gate capacitance (C) 2 ) Is connected to the second common gate NMOS power amplifier (M 2 ) Is connected to the drain of the third common gate NMOS power amplifier (M 3 ) Is a source and substrate of a third common gate NMOS power amplifier (M 3 ) Is connected to the gate of the isolation resistor (R 3 ) And a third gate-to-ground capacitance (C) 3 ) Is a third common gate NMOS power amplifier (M 3 ) Is connected to the drain of the fourth common gate NMOS power amplifier (M 4 ) A fourth common gate NMOS power amplifier (M 4 ) Is connected to the gate of the fourth isolation resistor (R 4 ) And a fourth grounded capacitance (C) 4 ) A second gate-to-ground capacitance (C 2 ) Third Gate ground capacitor (C) 3 ) Fourth grid grounding capacitor (C) 4 ) The other end of the first electrode is grounded; fourth common gate NMOS power amplifier (M) 4 ) The drain electrode of the (C) is connected with the output and matching module.
Compared with the prior art, the invention discloses a dynamic bias power amplifier, which is used for effectively adjusting the grid bias voltage of a power amplifier tube and controlling the bias dc current according to the input power to realize the power consumption self-adaptive input power dynamic adjustment and effectively improving the PAE efficiency of a power back-off area.
Drawings
Fig. 1 is a circuit configuration diagram of a power amplifier of a fixed bias in the prior art;
FIG. 2 is a circuit diagram of one embodiment of a dynamically biased power amplifier of the present invention;
FIG. 3 is a circuit diagram of another embodiment of a dynamically biased power amplifier of the present invention;
FIG. 4 is a graph comparing simulation results of the present invention with those of the prior art.
Detailed Description
Other advantages and effects of the present invention will become readily apparent to those skilled in the art from the following disclosure, when considered in light of the accompanying drawings, by describing embodiments of the present invention with specific embodiments thereof. The invention may be practiced or carried out in other embodiments and details within the scope and range of equivalents of the various features and advantages of the invention.
Fig. 2 is a circuit diagram of one embodiment of a dynamically biased power amplifier according to the present invention. As shown in fig. 2, a dynamically biased power amplifier of the present invention includes an input and matching module 10, a stacked power amplification module 20, an output and matching module 30, and a dynamic bias module 40. The input and matching module 10 consists of an input matching inductance Lin and an input blocking matching capacitance Cin, and is used for completing input matching and blocking; the laminated power amplifier module 20 is composed of a common source NMOS power amplifier tube M 1 Grid isolation resistor R 1 Multistage common-gate NMOS power amplifier M 2 、M 3 、M 4 Isolation resistor R 2 、R 3 、R 4 And a grid grounding capacitor C 2 、C 3 、C 4 The component is used for completing the power amplification of the radio frequency signals; the output and matching module 30 consists of a load inductance Ld and an output matching blocking capacitor Co, and is used for finishing output matching and blocking; the dynamic bias module 40 is composed of an input detection amplifier 41 and a bias adjustment module 42, and specifically, the input detection amplifier 41 comprises a sampling blocking capacitor C 9 And a single-ended amplifier Sa for sampling and amplifying the RF signal, the bias adjustment module 42 includes a diode-connected NMOS bias tube M 6 、M 7 、M 8 Composition of the compositionIs formed by NMOS bias tube M and fixed bias module 421 of (1) 5 Bias resistor R 5 Rectifying capacitor C 5 Variable bias module 422 and diode D 1 、D 2 A clamp 423 for dynamically adjusting the common source NMOS power amplifier M under the influence of the sampled RF signal output from the input sense amplifier 41 1 Co-grid NMOS power amplifier tube M 2 、M 3 、M 4 Is set in the above-described state.
Specifically, the radiofrequency signal RFin is connected to the input matching inductance Lin and the sampling blocking capacitor C 9 And the common end of the input blocking matching capacitor Cin, the other end of the input matching inductor Lin is connected with the radio frequency ground RF GND, and the other end of the input blocking matching capacitor Cin is connected with the common source NMOS power amplifier tube M 1 Gate and isolation resistor R of (2) 1 Is a member of the group; common source NMOS power amplifier M 1 Source electrode of (2) is connected with radio frequency ground RF GND, and common-source NMOS power amplifier tube M 1 Is connected to the drain electrode of the common gate NMOS power amplifier M 2 Common gate NMOS power amplifier M 2 Is connected to the isolation resistor R 2 One end of (2) and the grounded capacitance C of the grid 2 Is a common-gate NMOS power amplifier M 2 Is connected to the drain electrode of the common gate NMOS power amplifier M 3 Common gate NMOS power amplifier M 3 Is connected to the isolation resistor R 3 One end of (2) and the grounded capacitance C of the grid 3 Is a common-gate NMOS power amplifier M 3 Is connected to the drain electrode of the common gate NMOS power amplifier M 4 Common gate NMOS power amplifier M 4 Is connected to the isolation resistor R 4 One end of (2) and the grounded capacitance C of the grid 4 A gate-to-ground capacitor C 2 、C 3 、C 4 The other end of the first electrode is grounded; common-gate NMOS power amplifier M 4 The drain electrode of the output matching blocking capacitor Co is connected with the common end of the load inductance Ld, the other end of the load inductance Ld is connected with the power supply Vdd, and the other end of the output matching blocking capacitor Co is an output end RFout of the power amplifier;
sampling blocking capacitor C 9 The other end of the (a) is connected to the input end of the single-ended amplifier SaThe output end of the amplifier Sa is connected to an NMOS bias tube M 5 Drain of (d), bias resistor R 5 One end of (2) and NMOS bias tube M 6 Source and substrate of (a), bias resistor R 5 Is connected to the NMOS bias tube M 5 Gate, diode D of (c) 1 Anode, rectifying capacitor C of (2) 5 And an isolation resistor R 1 Is connected with the other end of diode D 1 Cathode connection diode D 2 Is an anode of NMOS bias tube M 5 Source and substrate of (D), diode D 2 Cathode of (C) and rectifying capacitor C 5 Is connected with the other end of the ground signal ground (RF GND); NMOS bias tube M 6 Is connected to the NMOS bias tube M after being short-circuited with the drain electrode and the grid electrode 7 Source and substrate of (a) and isolation resistor R 2 Is arranged at the other end of NMOS bias tube M 7 Is connected to the NMOS bias tube M after being short-circuited with the drain electrode and the grid electrode 8 Source and substrate isolation resistance R 3 Is arranged at the other end of NMOS bias tube M 8 Is connected to the reference current Iref and the isolation resistor R after being short-circuited with the drain and the gate of (a) 4 And the other end of (2).
It can be seen that the input detection amplifier 41 of the present invention converts the input power into the rf signal current by collecting the input power and amplifying the rf signal current with the same gain, and the rf signal current is injected into the bias adjustment module 42, and the NMOS self-bias adjustment tube M5 of the bias adjustment module 42 adjusts the gate and drain voltages according to the injection current, thereby realizing the common-source NMOS power amplifier M 1 Is controlled by the NMOS bias tube M under the constraint of the reference current Iref 6 /M 7 /M 8 The grid drain voltage is sequentially adjusted to M according to the drain voltage of the NMOS bias tube M5 2 /M 3 /M 4 The grid bias adjustment is realized, the grid bias voltage of the power amplifying tube can be effectively adjusted according to the input power, the bias dc current is controlled, the power consumption self-adaptive input power dynamic adjustment is realized, the PAE efficiency of the power back-off area can be effectively improved, and meanwhile, the clamp 423 can protect that the grid bias is excessively adjusted when the input power is maximum, so that the laminated power amplifying tube enters a linear area, and the linearity is degraded.
Fig. 3 is a circuit diagram of another embodiment of a dynamically biased power amplifier according to the present invention. Preferably, as shown in fig. 3, the single-ended amplifier SaFrom NMOS tube M 9 、M 10 Self-bias resistor R 9 、R 10 Composition, self-bias resistor R 9 And NMOS tube M 9 The grid of the self-bias resistor R is connected with the input end of the single-ended amplifier Sa 9 The other end of (a) is connected with an NMOS tube M 9 Drain electrode of NMOS transistor M 10 Gate of (2) and self-bias resistor R 10 Is self-biased by resistor R 10 The other end of (2) is connected with NMOS tube M 10 The drain electrodes of the NMOS transistor M are connected to form the output end of the single-ended amplifier Sa 9 、M 10 Is connected with analog ground;
preferably, as shown in FIG. 3, the clamp 423 is composed of a current limiting resistor Rd and a diode connected NMOS tube MD 1 、MD 2 One end of the current limiting resistor Rd is connected with the NMOS bias tube M 5 The other end of the grid electrode is connected with an NMOS tube MD 1 Drain and gate of NMOS transistor MD 1 Is connected with the NMOS tube MD by the source electrode and the substrate 2 Drain and gate of NMOS transistor MD 2 Is grounded to the radio frequency ground RF GND.
That is, in the present embodiment, the input sense amplifier is formed by two-stage self-bias common source amplification, the clamp is implemented by diode-connected MOS and resistor in series, and the clamp protection bias maximum voltage can be adjusted according to the maximum power output.
Fig. 4 is a diagram comparing the simulation of the present invention with the prior art. From the simulation comparison of fig. 4, it can be seen that the power back-off area PAE can be effectively improved by using the dynamic bias technique, and the 6dB back-off point PAE can be improved by more than 5%.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, the scope of the invention is to be indicated by the appended claims.
Claims (8)
1. A dynamically biased power amplifier, comprising:
the input and matching module is used for carrying out impedance matching and straightening on the input radio frequency signals;
the laminated power amplification module is used for amplifying the power of the matched radio frequency signals under the control of the dynamic bias voltage;
the output and matching module is used for carrying out impedance matching and straightening on the output radio frequency signals of the laminated power amplification module;
the dynamic bias module is used for generating dynamic bias voltage to the power amplifier tube of the laminated power amplifier module according to the magnitude of an input radio frequency signal;
wherein the dynamic biasing module further comprises:
the input detection amplifier is used for collecting input power and carrying out proper equidirectional gain amplification, and converting the input power into radio frequency signal current which is injected into the bias adjustment module; the method comprises the steps of,
the bias adjusting module is used for dynamically adjusting bias voltages of the common-source NMOS power amplifier tube and the common-gate NMOS power amplifier tube of the laminated power amplifying module under the influence of the sampling radio frequency signal output by the input detection amplifier, and the bias adjusting module comprises:
the fixed bias module is used for sequentially adjusting grid drain voltage to bias voltage of each common-grid NMOS power amplifier tube of the laminated power amplifier module under the constraint of reference current to realize grid bias adjustment;
the variable bias module is used for adjusting the grid electrode and drain electrode voltage of the NMOS bias tube according to the injection current, so as to realize the grid electrode bias adjustment of the common source NMOS power amplifier tube of the laminated power amplifier module;
and the clamp is used for protecting that the grid bias is excessively adjusted when the input power is maximum so that each power amplifying tube of the laminated power amplifying module enters a linear region.
2. A dynamically biased power amplifier as recited in claim 1, wherein: the fixed bias module includes a diode-connected sixth NMOS bias tube (M 6 ) Seventh NMOS bias tube (M) 7 ) Eighth NMOS bias tube (M) 8 ) The eighth NMOS bias tube (M 8 ) After the gate-drain is shorted, the reference current (Iref) is connected in parallelThe seventh NMOS bias tube (M 7 ) The gate-drain short circuit is connected with the eighth NMOS bias tube (M) 8 ) A source connected to the stacked power amplifier module, and a sixth NMOS bias tube (M 6 ) The gate-drain short circuit is connected with the seventh NMOS bias tube (M) 7 ) A source connected to the stacked power amplifier module, and a sixth NMOS bias tube (M 6 ) The source electrode is connected with the variable bias module.
3. A dynamically biased power amplifier as recited in claim 2, wherein: the variable bias module includes an NMOS bias tube (M 5 ) Bias resistor (R) 5 ) Rectifying capacitor (C) 5 ) The bias resistor (R 5 ) One end of the second NMOS bias tube is connected with the second NMOS bias tube (M 6 ) A source, the bias resistor (R 5 ) The other end is connected to the NMOS bias tube (M 5 ) Said rectifying capacitor (C 5 ) Is provided, the clamp, and the stacked power amplification module, the NMOS bias tube (M 5 ) A source and a substrate are connected to the rectifying capacitor (C 5 ) The other end is grounded at the radio frequency.
4. A dynamically biased power amplifier as recited in claim 3, wherein: the clamp comprises a first diode (D 1 ) Second diode (D) 2 ) The first diode (D 1 ) Is connected to the bias resistor (R 5 ) Said rectifying capacitor (C 5 ) And the laminated power amplification module, a cathode connected to the second diode (D 2 ) Is arranged between the first diode (D 2 ) The cathode is grounded at radio frequency.
5. A dynamically biased power amplifier as recited in claim 3, wherein: the clamp comprises a current limiting resistor (Rd) and a diode connected first NMOS tube (MD 1 ) Second NMOS tube (MD) 2 ) One end of the current limiting resistor (Rd) is connected with the NMOS bias tube (M) 5 ) The other end of the gate is connected with a first NMOS tube (MD 1 ) A kind of electronic deviceDrain and gate, first NMOS transistor (MD 1 ) Is connected with the source electrode and the substrate of the second NMOS tube (MD) 2 ) And the drain and gate of the second NMOS transistor (MD 2 ) Is grounded to the rf ground.
6. A dynamically biased power amplifier as recited in claim 4 or 5, wherein: the input sense amplifier includes a sampling dc blocking capacitor (C 9 ) And a single-ended amplifier (Sa), the radio frequency signal RFin being connected to the sampling dc blocking capacitance (C 9 ) One end of the sampling DC blocking capacitor (C 9 ) The other end is connected to the input end of the single-ended amplifier (Sa), and the output end of the single-ended amplifier (Sa) is connected to the NMOS bias tube (M 5 ) Drain of (d), bias resistance (R 5 ) Is connected to one end of the sixth NMOS bias tube (M 6 ) Is provided.
7. A dynamically biased power amplifier as recited in claim 6, wherein: the single-ended amplifier (Sa) includes a ninth NMOS transistor (M) 9 ) Tenth NMOS tube (M) 10 ) Ninth self-bias resistor (R) 9 ) Tenth self-bias resistor (R 10 ) The ninth self-bias resistor (R 9 ) And a ninth NMOS tube (M) 9 ) Is connected to the gate of the single-ended amplifier to form the input terminal of the single-ended amplifier, the ninth self-bias resistor (R 9 ) The other end of the transistor is connected with a ninth NMOS tube (M) 9 ) Is a drain electrode of a tenth NMOS transistor (M 10 ) And a tenth self-bias resistor (R) 10 ) Is a self-bias resistor (R) 10 ) Is connected with the other end of the tenth NMOS tube (M 10 ) Is connected to the drain of the single-ended amplifier to form the output end of the single-ended amplifier, and a ninth NMOS transistor (M 9 ) Tenth NMOS tube (M) 10 ) Is connected to analog ground.
8. A dynamically biased power amplifier as recited in claim 7, wherein: the stacked power amplification module includes a common source NMOS power amplifier tube (M 1 ) And its gate isolation resistor (R) 1 ) Second common-gate NMOS power amplifier (M) 2 )、Third common gate NMOS power amplifier (M) 3 ) Fourth common gate NMOS power amplifier (M) 4 ) And its second isolation resistor (R 2 ) A third isolation resistor (R 3 ) Fourth isolation resistor (R) 4 ) And a second gate grounding capacitance (C 2 ) Third Gate ground capacitor (C) 3 ) Fourth grid grounding capacitor (C) 4 ) The common source NMOS power amplifier (M 1 ) A gate connected to the gate isolation resistor (R 1 ) And is connected to the input and matching module, the source is connected to the radio frequency ground, and the drain is connected to the second common gate NMOS power amplifier (M 2 ) Is arranged between the source and the substrate of the second common gate NMOS power amplifier (M 2 ) Is connected to the second isolation resistor (R 2 ) And a second grounded-gate capacitance (C) 2 ) Is connected to the second common gate NMOS power amplifier (M 2 ) Is connected to the drain of the third common gate NMOS power amplifier (M 3 ) Is a source and substrate of a third common gate NMOS power amplifier (M 3 ) Is connected to the gate of the isolation resistor (R 3 ) And a third gate-to-ground capacitance (C) 3 ) Is a third common gate NMOS power amplifier (M 3 ) Is connected to the drain of the fourth common gate NMOS power amplifier (M 4 ) A fourth common gate NMOS power amplifier (M 4 ) Is connected to the gate of the fourth isolation resistor (R 4 ) And a fourth grounded capacitance (C) 4 ) A second gate-to-ground capacitance (C 2 ) Third Gate ground capacitor (C) 3 ) Fourth grid grounding capacitor (C) 4 ) The other end of the first electrode is grounded; fourth common gate NMOS power amplifier (M) 4 ) The drain electrode of the (C) is connected with the output and matching module.
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| CN111611534B (en) | 2019-02-26 | 2023-12-01 | 北京知存科技有限公司 | Dynamic bias analog vector-matrix multiplication operation circuit and operation control method thereof |
| CN112803905B (en) * | 2021-04-14 | 2021-09-28 | 广州慧智微电子有限公司 | Compensation circuit |
| CN113721699A (en) * | 2021-09-06 | 2021-11-30 | 湖南微朗科技有限公司 | Power adjustable solid state radio frequency source |
| CN115580233B (en) * | 2022-12-08 | 2023-06-16 | 西安博瑞集信电子科技有限公司 | Dynamic bias method and system for low-noise amplifier and dynamic bias circuit |
| CN118646374B (en) * | 2024-08-12 | 2024-11-12 | 成都信息工程大学 | On-chip capacitor bandwidth widening circuit and electronic device |
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| CN103795356A (en) * | 2014-01-21 | 2014-05-14 | 浙江大学 | Envelope tracking radio frequency power amplifier |
| CN111313849A (en) * | 2020-02-26 | 2020-06-19 | 上海华虹宏力半导体制造有限公司 | High-linearity radio frequency power amplifier |
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| WO2002003544A1 (en) * | 2000-06-30 | 2002-01-10 | Mitsubishi Denki Kabushiki Kaisha | High-frequency amplifier |
| TWI509979B (en) * | 2013-01-04 | 2015-11-21 | Advanced Semiconductor Eng | Electronic system, radio frequency power amplifier and method for dynamic adjusting bias point. |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1551486A (en) * | 2003-05-19 | 2004-12-01 | 三星电子株式会社 | Integratable, voltage-controlled RF power amplifier |
| CN102045032A (en) * | 2009-10-19 | 2011-05-04 | 财团法人工业技术研究院 | Power amplifier |
| CN103795356A (en) * | 2014-01-21 | 2014-05-14 | 浙江大学 | Envelope tracking radio frequency power amplifier |
| CN111313849A (en) * | 2020-02-26 | 2020-06-19 | 上海华虹宏力半导体制造有限公司 | High-linearity radio frequency power amplifier |
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