CN112835321B - Programmable controller systems and modules - Google Patents

Abstract

The present invention provides a programmable controller system and a module, wherein the programmable controller system can synchronize the self-module cycles of the modules constituting the programmable controller system. The programmable controller system (SYS) comprises a substrate (B1) and a plurality of modules (M1 to M6) connected to the substrate, wherein the plurality of modules each comprises: an independent clock generating unit (CL1 to CL6) for generating an independent clock; a counter unit (Co1 to Co6) for generating a self-module cycle based on the independent clock generated by the independent clock generating unit; and a synchronization correction unit (SY1 to SY6) for calculating the offset of the self-module cycle based on the self-module cycle and a synchronization reference point based on a synchronization start signal output from a synchronization control unit, and correcting the self-module cycle based on the calculated offset.

Description

Programmable controller systems and modules

Technical Field

The invention relates to a programmable controller system and a module.

Background technique

In recent years, the application fields of programmable controller (also called "PLC") systems have expanded with the development of high performance and high functionality, and the needs of users have also become diverse. In order to cope with the high performance and high functionality of programmable controller systems and devices using programmable controller systems, control methods based on advanced control theories such as predictive control have been adopted as control methods using PLCs. In addition, the computing performance of the CPU (Central Processing Unit) module used to perform control operations of programmable controller systems has been improved to cope with this.

As such a programmable controller system, the following technology is known: the time synchronization between the units of a control device composed of a plurality of modules (units) is used to improve the performance of the programmable controller system as a whole (for example, refer to Patent Document 1). Each module described in Patent Document 1 performs scanning based on a pulse generated by a clock generating unit. Originally, in the case of devices operating with the same structure and the same performance, the scanning operation is also the same.

However, the scanning timing may be offset due to differences in the power-on time, the initialization content of the CPU module, etc. The pulse generated by the clock generation unit may be any pulse, but is generally a stable signal provided by a crystal oscillator, etc., and is described as a clock pulse in the following description.

Therefore, in the programmable controller system described in Patent Document 1, the reference clocks of the modules connected to the substrate are synchronized by a synchronization control circuit configured on the substrate. In the programmable controller system described in Patent Document 1, the reference time of all modules is synchronized after the start of each module.

Prior art literature

Patent Literature

Patent Document 1: International Publication No. 2012/081115

Summary of the invention

Problem that the invention aims to solve

However, when part of each module has a cycle of different integer multiples and the startup start time of some modules is delayed, or when some modules are started later and synchronized, there is a problem that the starting point of the reference time is inconsistent in the relationship between the modules that have been running with a cycle of different integer multiples from the beginning and the modules that are started later.

The present invention has been made in view of the above-mentioned problems, and one object of the present invention is to provide a programmable controller system capable of synchronizing the module cycles of the modules constituting the programmable controller system.

Solutions for solving problems

Regarding the programmable controller system of the present embodiment, in one mode, it is a programmable controller system including a substrate and a plurality of modules connected to the substrate, wherein the programmable controller system is characterized in that the substrate includes a synchronization control unit for controlling the synchronization of the plurality of modules, and each of the plurality of modules includes: an independent clock generating unit for generating an independent clock; a counter unit for generating a self-module period based on the independent clock generated by the independent clock generating unit; and a synchronization correction unit for calculating an offset of the self-module period based on the self-module period and a synchronization reference point based on a synchronization start signal output from the synchronization control unit, and correcting the self-module period based on the calculated offset.

Effects of the Invention

According to the present invention, it is possible to provide a programmable controller system capable of synchronizing the module cycles of the modules constituting the programmable controller system.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing a configuration of a programmable controller system according to the present embodiment.

FIG. 2 is a diagram showing an example of a functional configuration of a PLC system.

FIG. 3 is a diagram showing an example of a timing chart of information notified between the first to sixth CPU modules and the substrate.

FIG. 4 is a diagram showing a state in which the first to sixth CPU modules, which have received a synchronization start signal, transition from a missynchronization state to a synchronization state.

5 is a diagram showing an example of a sequence chart of a synchronization correction process executed between the first CPU module, the second CPU module, and the substrate constituting the PLC system.

FIG. 6 is a flowchart showing an example of synchronization correction processing executed by the first CPU module.

FIG. 7 is a flowchart showing an example of synchronization correction execution processing.

Description of Reference Numerals

SYS: programmable controller system; M1~M6: first CPU module~sixth CPU module; K1~K6: connector; B1: baseboard; P1~P6: processor; W1~W6: interrupt control unit; CL1~CL6: independent clock generation unit; Co1~Co6: counter unit; Pa1~Pa6: power supply control unit; SY1~SY6: synchronization correction unit; BSY1: synchronization control unit; BCL1: reference clock generation unit.

Detailed ways

Hereinafter, an embodiment of the present invention (hereinafter simply referred to as “embodiment”) will be described in detail. Note that the present invention is not limited to the following embodiment, and can be implemented with various modifications within the scope of the gist thereof.

Fig. 1 is a diagram showing a configuration of a programmable controller system according to an embodiment of the present invention. A programmable controller (hereinafter referred to as "PLC") system SYS is configured to include first to sixth CPU modules M1 to M6, connectors K1 to K6, and a substrate B1.

The first to sixth CPU modules M1 to M6 are connected via connectors K1 to K6 and via a bus (not shown) on the substrate B1. The first to sixth CPU modules M1 to M6 are hereinafter referred to as "modules M" unless otherwise specifically distinguished.

Fig. 2 is a diagram showing an example of the functional structure of the PLC system. The first CPU module M1 to the sixth CPU module M6 each include processors P1 to P6, interrupt control units W1 to W6, independent clock generation units CL1 to CL6, counter units Co1 to Co6, power supply control units Pa1 to Pa6, and synchronization correction units SY1 to SY6. The substrate B1 includes a synchronization control unit BSY1 and a reference clock generation unit BCL1.

The first CPU module M1 and the second CPU module M2 have an application execution function for executing the user's application. The third CPU module M3 and the fourth CPU module M4 are also called IO bus built-in CPU modules, which have IO bus functions and application execution functions. The IO bus function is used to communicate between remote networks that they have at a constant cycle. The fifth CPU module M5 and the sixth CPU module M6 are also called IO bus master modules, which have IO bus functions. Each module M can also set various modules such as other input modules and output modules as synchronization objects.

The independent clock generating units CL1 to CL6 generate independent clocks of the self-module cycles executed by the first CPU module M1 to the sixth CPU module M6. The counter units Co1 to Co6 generate the self-module cycles based on the independent clocks generated by the independent clock generating units CL1 to CL6. In addition, the counter units Co1 to Co6 count the independent clock values generated by the independent clock generating units CL1 to CL6 and hold them as count values. In this embodiment, the independent clock generating units CL1 to CL6 use a crystal of a specified frequency to generate a pulse of an arbitrary cycle and then output it. The crystal oscillator error (parts per million (PPM: Parts Per Million) error) of the crystal of each independent clock generating unit CL1 to CL6 varies, and the clock frequency also changes according to the temperature and is not constant, so the self-module cycle of each module M gradually shifts. The independent clock of the self-module cycle at the independent time generated by the independent clock generating units CL1 to CL6 can be an arbitrary value, but in this embodiment, the independent clock generating units CL1 to CL6 use a 1MHz crystal to generate a pulse of a 100μs cycle.

Processors P1 to P6 respectively execute the independent functions of the first CPU module M1 to the sixth CPU module M6 at a constant cycle. Processors P1 to P6 can execute input functions, application execution functions, output functions, etc., wherein the input function is used to obtain input signals of the PLC system SYS and notify the input signals as input data, the application execution function is used to receive the input data, perform operations on the input data, and notify the operation results as output data, and the output function is used to receive output data and output the output data as digital or analog signals. Processors P1 to P6 can also have bus functions, external memories, input circuits or output circuits, etc. for connecting modules as needed.

The power control units Pa1 to Pa6 notify the synchronization control unit BSY1 disposed on the substrate B1 of the power state (SY_P1 to SY_P6) of each of the first CPU module M1 to the sixth CPU module M6. The power state (SY_P1 to SY_P6) is information for notifying the synchronization control unit BSY1 of the substrate B1 of the power state of its own module M, and is notified when the power of the synchronization correction units SY1 to SY6 of each of the first CPU module M1 to the sixth CPU module M6 is turned on. The power state (SY_P1 to SY_P6) is, for example, information consisting of 1 bit, which is "0" (off) in the initial state, and the power control units Pa1 to Pa6 notify "1" (on) when the power of their own modules M is turned on.

Processors P1 to P6 use synchronization start request registers and synchronization setting registers to set synchronization correction units SY1 to SY6 to indicate whether they are synchronization targets, depending on whether synchronization is required, and issue synchronization start requests when each module is started up.

The synchronization correction units SY1 to SY6 notify the synchronization control unit BSY1 disposed on the substrate B1 of the synchronization setting states (SY_EN1 to SY_EN6) of the first to sixth CPU modules M1 to M6 using the synchronization setting registers.

The synchronization setting status register is information for notifying the synchronization control unit BSY1 of the substrate B1 whether its own module M is a synchronization target, and is notified when the power of its own module M is turned on. The synchronization setting status register is, for example, information consisting of 1 bit. When its own module M is not a synchronization target, the synchronization correction units SY1 to SY6 set "0" (off) to the synchronization setting status register and notify, and when its own module M is a synchronization target, they set "1" (on) to the synchronization setting status register and notify.

The synchronization correction units SY1 to SY6 notify the synchronization control unit BSY1 disposed on the substrate B1 of the synchronization start requests (SY_RQ1 to SY_RQ6) of the first to sixth CPU modules M1 to M6 respectively using the synchronization start request registers.

The synchronization start request register is used to request the synchronization control unit BSY1 on the substrate B1 to start synchronization. It is notified at any time such as the power supply state (SY_P1 to SY_P6) of the module M itself, the synchronization setting state (SY_EN1 to SY_EN6), and the completion of initialization. The synchronization start request register is, for example, information composed of 1 bit. Before making a request for synchronization start, the synchronization correction unit SY1 to SY6 sets the synchronization start request register to "0" (off) and notifies. When making a request for synchronization start, it sets the synchronization start request register to "1" (on) and notifies.

The reference clock generator BCL1 generates a reference time that is used as a reference for synchronizing the PLC system SYS. The reference clock generator BCL1 outputs the information of the generated reference time to the synchronization correction units SY1 to SY6 configured in the first CPU module M1 to the sixth CPU module M6 and the synchronization control unit BSY1 configured on the substrate B1. The period of the reference time generated by the reference clock generator BCL1 can be any value, but in this embodiment, the reference clock generator BCL1 uses a 1MHz crystal to generate a pulse with a period of 100μs (CLK100μs), and outputs the pulse as the reference time.

The synchronization control unit BSY1 generates a synchronization start signal (SY_EXE) based on the synchronization setting state (SY_EN1 to SY_EN6), synchronization start request (SY_RQ1 to SY_RQ6), power supply state (SY_P1 to SY_P6) received from each of the first CPU module M1 to the sixth CPU module M6, and the reference time (CLK100μs) generated by the reference clock generation unit BCL1, and outputs the synchronization start signal to the synchronization correction unit SY1 to SY6 of each of the first CPU module M1 to the sixth CPU module M6. For example, the synchronization control unit BSY1 outputs the synchronization start signal (SY_EXE) to the synchronization correction unit SY1 to SY6 of each of the first CPU module M1 to the sixth CPU module M6 based on the rising edge or falling edge of the reference time (CLK100μs) generated by the reference clock generation unit BCL1.

Fig. 3 is a diagram showing an example of a timing diagram of information notified between the first CPU module to the sixth CPU module and the substrate B1. When the power supply states (SY_P1 to SY_P6) of the first CPU module M1 to the sixth CPU module M6 and the synchronization setting states (SY_EN1 to SY_EN6) of the modules M to be synchronized are on, and the synchronization start requests (SY_RQ1 to SY_RQ6) of all the modules M to be synchronized are on, the synchronization control unit BSY1 uses a trigger to hold the synchronization start request (SY_RQ1 to SY_RQ6) of each module M.

The synchronization control unit BSY1 receives the synchronization start request (SY_RQ1 to SY_RQ6) in the form of pulses from the synchronization correction units SY1 to SY6 of the first CPU module M1 to the sixth CPU module M6. The synchronization control unit BSY1 determines whether all the synchronization start requests (SY_RQ1 to SY_RQ6) of the module M that is the synchronization object are received at the time T1 to T6 based on the rising edge of the reference time (clock). The synchronization control unit BSY1 latches the received synchronization start request (SY_RQ1 to SY_RQ6) as an internal signal (SY_RQFF1 to SY_RQFF6), thereby being able to determine whether the synchronization start request (SY_RQ1 to SY_RQ6) is received from all the modules M that are the synchronization object. When receiving synchronization start requests (SY_RQ1 to SY_RQ6) from all modules M to be synchronized, the synchronization control unit BSY1 outputs a synchronization start signal (SY_EXE) in the form of a pulse to each module M to be synchronized based on the rising or falling edge of the reference time (CLK100 μs).

Fig. 4 is a diagram showing the state where the first to sixth CPU modules that have received the synchronization start signal (SY_EXE) transition from the synchronization inconsistency state to the synchronization state. Fig. 4 (1) is a diagram showing the synchronization inconsistency state of the first CPU module M1 to the sixth CPU module M6. Fig. 4 (2) is a diagram showing the state where the first CPU module M1 to the sixth CPU module M6 transition from the synchronization inconsistency state to the synchronization state.

As shown in (1) of Fig. 4, before the synchronization correction, the starting points of the cycles of the modules M of the first CPU module M1 to the sixth CPU module M6 (hereinafter also referred to as "self-module cycles") are inconsistent, for example, at time T7. Therefore, the synchronization correction is performed so that the starting points of the self-module cycles of the first CPU module M1 to the sixth CPU module M6 are consistent.

First, the synchronization correction units SY1 to SY6 of each module M that receives the synchronization start signal (SY_EXE) obtain the self-module cycle from the time state of the counter units Co1 to Co6 respectively. The synchronization correction units SY1 to SY6 calculate the synchronization reference offset amplitude based on the self-module cycle and the synchronization reference point based on the synchronization start signal (SY_EXE). The synchronization reference offset amplitude is the difference in the offset amount from the self-module cycle. The synchronization reference point is the moment that serves as the reference for synchronizing each module M. In this embodiment, the synchronization correction units SY1 to SY6 set the synchronization reference point based on the rising edge of the synchronization start signal (SY_EXE). In this case, the moment of outputting the synchronization start signal (SY_EXE) coincides with the moment of the synchronization reference point. In addition, the synchronization correction units SY1 to SY6 may also set the moment after a specified time has passed since the output of the synchronization start signal (SY_EXE) as the synchronization reference point.

The synchronization correction units SY1 to SY6 calculate the elapsed time from the start of the module cycle to the synchronization reference point as the synchronization reference offset width. For example, as shown in (2) of FIG. 4 , the synchronization correction unit SY1 of the first CPU module M1 calculates the elapsed time (Te-t1=k1) from the start of the cycle of the first CPU module M1 to the synchronization reference point Te set based on the rising edge of the synchronization start signal (SY_EXE) as the synchronization reference offset width of the first CPU module M1. The synchronization correction unit SY1 sets the correction direction based on which of the equations (1) and (2) the calculated synchronization reference offset width satisfies.

Synchronous reference offset width ≥ (self-module period - synchronous reference offset width): Negative (-) correction direction... (1)

Synchronous reference offset width < (self-module period - synchronous reference offset width): Positive (+) correction direction... (2)

When equation (1) holds true, the synchronization correction unit SY1 sets the correction direction to the - (negative) correction direction, that is, the direction in which the cycle is shortened. When equation (2) holds true, the synchronization correction unit SY1 sets the correction direction to the + (positive) correction direction, that is, the direction in which the cycle is extended. The synchronization correction units SY2 to SY6 set the correction directions of the second CPU module M2 to the sixth CPU module M6 in the same way as the synchronization correction unit SY1. In (2) of FIG. 4 , the correction direction of - (negative) or the cycle of the correction direction in the direction in which the cycle is shortened (for example, the next cycle C1, C3, C5) is indicated by two arrows, and the correction direction of + (positive) or the cycle of the correction direction in the direction in which the cycle is extended (for example, the next cycle C2, C4, C6) is indicated by three arrows. In addition, the synchronization correction units SY1 to SY6 may calculate the elapsed time from the synchronization reference point to the end time of the self-module cycle as the synchronization reference offset width. In this case, the synchronization correction units SY1 to SY6 set the positive and negative signs of the correction directions in reverse.

The synchronization correction units SY1 to SY6 set the information of the determined correction direction to the synchronization correction direction register. The synchronization correction direction register is information for determining whether to perform correction in the negative direction or in the positive direction. The synchronization correction direction register is, for example, information consisting of 1 bit. When the determined correction direction is + (positive), the synchronization correction units SY1 to SY6 set "0" to the synchronization correction direction register, and when the determined correction direction is - (negative), the synchronization correction direction register is set to "1".

For example, the case of the fifth CPU module M5 in FIG. 4 in which the self-module cycle is "4000 μs" and the synchronization reference offset width is "3700 μs" is described. When a pulse of the synchronization start signal (SY_EXE) is received at 3700 μs from the start of the self-module cycle, that is, when the synchronization reference point Te is set to 3700 μs, it is determined whether the value obtained by subtracting the synchronization reference offset width "3700 μs" from the self-module cycle "4000 μs" is greater than the synchronization reference offset width "3700 μs".

The value "300μs" obtained by subtracting the synchronization reference offset width "3700μs" from the self-module cycle "4000μs" is less than the synchronization reference offset width "3700μs", that is, equation (1) holds. In this case, the synchronization correction unit SY5 of the fifth CPU module M5 sets the correction direction to the correction direction of - (negative), that is, the direction in which the cycle of the next cycle (hereinafter also referred to as "next cycle") C5 is shortened even when a pulse of the synchronization start signal (SY_EXE) is received.

In addition, the case of the sixth CPU module M6 in FIG. 4 in which the self-module cycle is 4000 μs and the synchronization reference offset width is "1800 μs" is described. When a pulse of the synchronization start signal (SY_EXE) is received at 1800 μs from the start of the self-module cycle, that is, when the synchronization reference point Te is 1800 μs, it is determined whether the value obtained by subtracting the synchronization reference offset width "1800 μs" from the self-module cycle "4000 μs" is greater than the synchronization reference offset width "1800 μs".

The value "2200μs" obtained by subtracting the synchronization reference offset width "1800μs" from the self-module cycle "4000μs" is greater than the synchronization reference offset width "1800μs", that is, equation (2) holds. In this case, the synchronization correction unit SY6 of the sixth CPU module M6 sets the correction direction to the + (positive) correction direction, that is, the direction in which the cycle of the next cycle C6 is extended.

In addition, when the starting point t6' of the cycle of the sixth CPU module M6 is consistent with the synchronization reference point Te set based on the rising edge of the synchronization start signal (SY_EXE) as in the example of the synchronization consistency of the sixth CPU module M6, that is, when the synchronization reference offset amplitude is 0, the synchronization correction units SY1~SY6 do not set the correction direction and do not perform synchronization correction.

By changing the correction direction based on whether the value obtained by subtracting the synchronization reference shift width from the self-module period is larger than the synchronization reference shift width, correction can be performed in approximately half the self-module period when correction up to the self-module period is required.

The synchronization correction units SY1 to SY6 set the smaller value of the synchronization reference offset width and the value obtained by subtracting the synchronization reference offset width from the self-module period to the synchronization correction target time register as the synchronization correction target time. The synchronization correction target time register is information composed of an arbitrary number of bits. The synchronization correction target time is information on the overall time for synchronization correction.

For example, the case of the fifth CPU module M5 in FIG. 4 in which the self-module cycle is "4000μs" and the synchronization reference offset width is "3700μs" is described. The synchronization reference offset width "3700μs" of the fifth CPU module M5 is greater than the value "4000μs-3700μs=300μs" obtained by subtracting the synchronization reference offset width from the self-module cycle. Therefore, the synchronization correction unit SY5 of the fifth CPU module M5 sets the value "300μs" obtained by subtracting the synchronization reference offset width from the self-module cycle as the synchronization correction target time to the synchronization correction target time register.

In addition, the case of the sixth CPU module M6 in FIG. 4 in which the self-module period is "4000μs" and the synchronization reference offset width is "1800μs" is described. The synchronization reference offset width "1800μs" of the sixth CPU module M6 is smaller than the value "4000μs-1800μs=2200μs" obtained by subtracting the synchronization reference offset width from the self-module period. Therefore, the synchronization correction unit SY6 of the sixth CPU module M6 sets the synchronization reference offset width "1800μs" as the synchronization correction target time to the synchronization correction target time register.

The synchronization correction units SY1 to SY6 set an arbitrary unit time when performing synchronization correction as the synchronization correction amplitude in the synchronization correction amplitude register. The synchronization correction units SY1 to SY6 use the synchronization correction amplitude set in the synchronization correction amplitude register as a unit to correct an amount corresponding to the synchronization correction target time. The synchronization correction amplitude register is information composed of an arbitrary number of bits. The synchronization correction amplitude is information indicating the unit time for correction in one cycle and indicating the degree of amplitude by which the synchronization correction target time is divided for correction.

The synchronization correction amplitude set in the synchronization correction amplitude register may also be a value specified in advance in the processors P1 to P6 and the interrupt control units W1 to W6. In addition, the synchronization correction target time for actual correction may also be specified in the synchronization correction amplitude register. When the synchronization correction target time is longer than the synchronization correction amplitude, the self-module cycle may be corrected by increasing or decreasing the amount corresponding to the synchronization correction amplitude from the cycle time by one cycle after the next cycle. Thus, through the IO bus and the functions realized by the first CPU module M1 to the sixth CPU module M6, it is possible to prevent problems such as the detachment of the part (module) added to the IO bus due to a one-time large-scale correction. When the synchronization correction target time is the same as the synchronization correction amplitude, or the synchronization correction target time is shorter than the synchronization correction amplitude, the amount corresponding to the synchronization correction target time may also be corrected in the next cycle.

The synchronization correction units SY1 to SY6 set information for indicating the execution of synchronization correction in the synchronization correction execution register. The synchronization correction execution register is, for example, information consisting of 1 bit. Before performing synchronization correction, the synchronization correction units SY1 to SY6 set the synchronization correction execution register to "0" (off) and notify, and when performing synchronization correction, set the synchronization correction execution register to "1" (on) and notify.

The synchronization correction units SY1 to SY6 set information of a synchronization correction target time register, information of a synchronization correction direction register, and information of a synchronization correction width register, and start synchronization correction by setting a synchronization correction execution register to "1" (ON).

For example, when the synchronization correction target time is less than the synchronization correction width, the synchronization correction units SY1 to SY6 set the synchronization correction target time as the actual correction time. On the other hand, when the synchronization correction target time is greater than the synchronization correction width, the synchronization correction unit SY1 calculates the synchronization correction width and sets it as the actual correction time.

For example, the case of the fifth CPU module M5 in FIG. 4 where the synchronization correction target time is "300μs" and the synchronization correction width is "500μs" is described. When the synchronization correction target time "300μs" is less than the synchronization correction width "500μs", the synchronization correction unit SY5 sets the synchronization correction target time "300μs" as the actual correction time. Then, when the set correction direction is the - (negative) direction, the synchronization correction unit SY5 sets the value "4000μs-300μs=3700μs" obtained by subtracting the set actual correction time "300μs" from the self-module cycle "4000μs" as the length C5 of the next cycle to correct the self-module cycle.

The case of the sixth CPU module M6 in FIG. 4 in which the synchronization correction target time is "1800μs" and the synchronization correction width is "500μs" is described. When the synchronization correction target time "1800μs" is less than the synchronization correction width "500μs", the synchronization correction unit SY5 sets the synchronization correction target time "1800μs" as the actual correction time. Then, when the set correction direction is the + (positive) direction, the synchronization correction unit SY5 sets the value "4000μs+1800μs=5800μs" obtained by adding the set actual correction time "1800μs" to the self-module cycle "4000μs" as the length of the next cycle C6 to correct the self-module cycle.

Thus, the starting point Tb of the next cycle C5b of the cycle C5 of the fifth CPU module M5, which also has a self-module cycle of "4000 μs", coincides with the starting point Tb of the next cycle C6b of the cycle C6 of the sixth CPU module M6. Thus, as shown in (1) of FIG. 4 , the starting points of the self-module cycles of the modules M in a state of synchronization inconsistency can be made consistent.

In addition, the lengths of the first CPU module M1 with a module cycle of "1000μs", the next cycles C1 and C2 of the second CPU module M2, and the third CPU module M3 with a module cycle of "2000μs", and the next cycles C3 and C4 of the third CPU module M3 are determined in the same way and synchronization correction is performed.

Therefore, as shown in (2) of Figure 4, the starting starting point Tb of the self-module cycles of each module can be made consistent after the least common multiple "4ms" of the self-module cycles of the first CPU module M1 and the second CPU module M2, the self-module cycles of the third CPU module M3 and the fourth CPU module M4, and the self-module cycles of the fifth CPU module M5 and the sixth CPU module M6.

That is, as shown in (1) of FIG. 4 , in the asynchronous state before a series of synchronization corrections starting with the synchronization start signal (SY_EXE) are performed, the first CPU module M1 to the sixth CPU module M6 are in the +++ state.

In contrast, in the present embodiment, when a series of synchronization corrections are performed starting from the synchronization start signal (SY_EXE), upon receiving the synchronization start signal (SY_EXE), the synchronization correction units SY1 to SY6 of the first CPU module M1 to the sixth CPU module M6 determine the synchronization correction direction and the synchronization correction target time. Thus, the synchronization correction units SY1 to SY6 can synchronize the starting point in the first cycle or the second cycle after the least common multiple of each module M by performing synchronization correction in the next cycle. Thus, the self-module cycle of each module M constituting the PLC system SYS can be synchronized without separately having a module or the like for managing the synchronization of the PLC system SYS.

In addition, when the synchronization correction target time is "300μs" and the synchronization correction width is "1μs", the synchronization correction units SY1~SY6 perform correction in a manner divided into a cycle of "300 times", where "300 times" is the value obtained by dividing the synchronization correction target time "300μs" by the synchronization correction width "1μs".

In this case, when the correction direction is the - (negative) direction, the synchronization correction units SY1 to SY6 perform correction in a cycle of "300 times" with a value "299 μs" obtained by subtracting the synchronization correction width "1 μs" from the synchronization correction target time "300 μs".

When the correction direction is the positive direction, the synchronization correction units SY1 to SY6 perform correction in a cycle of "300 times" with a value "301 μs" obtained by adding the synchronization correction width "1 μs" to the synchronization correction target time "300 μs".

More specifically, the case where the synchronization correction target time is "300μs", the self-module cycle is "4000μs", and the synchronization correction width is "100μs" is described. When the synchronization correction target time "300μs" is greater than the synchronization correction width "100μs", the synchronization correction unit SY5 sets the synchronization correction width "100μs" as the actual correction time. Then, when the set correction direction is the + (positive) direction, the synchronization correction units SY1 to SY6 set the value "4000μs+100μs=4100μs" obtained by adding the set actual correction time "100μs" to the self-module cycle "4000μs" as the length of the next cycle to correct the self-module cycle.

The synchronization correction units SY1 to SY6 set the value "300μs-100μs=200μs" obtained by subtracting the actual correction time "100μs" from the synchronization correction target time "300μs" as the synchronization correction target time. Thereafter, the synchronization correction units SY1 to SY6 repeatedly perform the self-module cycle correction in three cycles by adding the actual correction time and subtracting the synchronization correction target time in each cycle until the synchronization correction target time becomes equal to or less than "0".

By performing correction in a divided manner into a plurality of cycles in this way, a sudden shortening of the self-module cycle can be suppressed, thereby preventing the application execution function and the IO bus function from being unable to be executed within the shortened cycle, thereby preventing malfunction of the PLC system SYS.

In addition, the synchronization correction width may be set to a value greater than the synchronization correction target time. In this case, the synchronization correction units SY1 to SY6 correct by an amount corresponding to the synchronization correction target time. For example, when the synchronization correction target time is "300 μs" and the synchronization correction width is "500 μs", the synchronization correction width "500 μs" is greater than the synchronization correction target time "300 μs". In this case, the synchronization correction units SY1 to SY6 perform correction with the synchronization correction target time "300 μs".

In addition, at the initial startup of the PLC system SYS (for example, at the time of initialization), as the synchronization correction amplitude, a maximum value is set, and the self-module cycle is corrected in one cycle. When each module M is started separately after the PLC system SYS is started (for example, when at least one of the multiple modules M is in action), an arbitrary synchronization correction amplitude can be set, and the self-module cycle is corrected in a manner of dividing it into n (n>2) cycles. As a result, at the initial startup of the PLC system SYS, synchronization correction can be performed early, and when each module M is started separately after the PLC system SYS is started, it can be prevented that each module M cannot perform various functions due to a sudden shortening of the self-module cycle.

Furthermore, after the synchronization correction, the synchronization correction units SY1 to SY6 use the counter units Co1 to Co6 and the like to determine the crystal oscillator error (PPM error) between the independent clock generators CL1 to CL6 of each module M and the reference clock generator BCL1 on the substrate B1. Then, when the result of the determination is that the crystal oscillator error (PPM error) exceeds a certain range, the same synchronization correction process is started when the reference clock generator BCL1 on the substrate B1 is started, or at any time specified in the IO bus function of the processors P1 to P6 and the interrupt control units W1 to W6, and the self-module cycle of each module M is corrected by temporarily performing subtraction or addition, thereby continuously maintaining synchronization.

Fig. 5 is a diagram showing an example of a sequence diagram of a synchronization correction process performed between the first CPU module M1, the second CPU module M2 and the substrate B1 constituting the PLC system SYS. In the embodiment of Fig. 5, only the first CPU module M1 and the second CPU module M2 among the first CPU module M1 to the sixth CPU module M6 are described, and the third CPU module M3 to the fourth CPU module 6 are also described in the same manner.

First, when the power of the first CPU module M1 is turned on, the power control unit Pa1 of the first CPU module M1 notifies the board B1 of the power state (SY_P1) (S101). In addition, the synchronization correction unit SY1 of the first CPU module M1 notifies the board B1 of the synchronization setting state (SY_EN1) (S102).

Similarly, when the power of the second CPU module M2 is turned on, the power control unit Pa2 of the second CPU module M2 notifies the board B1 of the power state (SY_P2) (S103). In addition, the synchronization correction unit SY2 of the second CPU module M2 notifies the board B1 of the synchronization setting state (SY_EN2) (S104).

The synchronization correction unit SY1 of the first CPU module M1 uses the synchronization start request register to notify the synchronization control unit BSY1 configured on the substrate B1 of the synchronization start request (SY_RQ1) at any time (S105). Similarly, the synchronization correction unit SY2 of the second CPU module M2 uses the synchronization start request register to notify the synchronization control unit BSY1 configured on the substrate B1 of the synchronization start request (SY_RQ2) at any time (S106).

The synchronization control unit BSY1 of the substrate B1 determines whether the synchronization start request (SY_RQ1 to SY_RQ6) is received from all the modules M as synchronization targets (S107). If the synchronization start request (SY_RQ1 to SY_RQ6) is not received from all the modules M as synchronization targets (S107: "No"), the process is put on standby until the synchronization start request (SY_RQ1 to SY_RQ6) is received from all the modules M as synchronization targets.

When a synchronization start request (SY_RQ1 to SY_RQ6) is received from all modules M that are synchronization objects (S107: "Yes"), the synchronization control unit BSY1 of the substrate B1 outputs the synchronization start signal (SY_EXE) and the reference time (CLK100μs) to the synchronization correction unit SY1 of the first CPU module M1 and the synchronization correction unit SY2 of the second CPU module M2, respectively, based on the rising edge of the reference time (CLK100μs) generated by the reference clock generation unit BCL1 (S108 to S111).

The synchronization correction unit SY1 of the first CPU module M1 that has received the synchronization start request (SY_RQ1) performs the synchronization correction process (S112) described later. Similarly, the synchronization correction unit SY2 of the second CPU module M2 that has received the synchronization start request (SY_RQ2) performs the synchronization correction process (S113) described later. The synchronization correction process of S112 performed by the first CPU module M1 and the synchronization correction process of S113 performed by the second CPU module M2 are substantially the same processes, and therefore are described below using a flowchart based on the same reference numerals.

Fig. 6 is a flowchart showing an example of the synchronization correction process executed by the first CPU module. The synchronization correction process executed by the second CPU module M2 to the sixth CPU module M6 is also the same as the synchronization correction process executed by the first CPU module M1, so the description thereof is omitted.

First, when the module itself is the synchronization target, the synchronization correction unit SY1 performs the initial setting of the module function (S201). The synchronization correction unit SY1 determines whether the initial setting has been completed (S202). If the result of the determination is that the initial setting has not been completed (S202: "No"), the process is put on standby. If the result of the determination is that the initial setting has been completed (S202: "Yes"), the synchronization correction unit SY1 notifies the substrate B1 of the synchronization start request (SY_RQ1) (S203).

The synchronization correction unit SY1 determines whether the synchronization start signal (SY_EXE) is received from the synchronization control unit BSY1 of the substrate B1 (S204). If the synchronization start signal (SY_EXE) is not received from the synchronization control unit BSY1 (S204: No), the process is put on standby until the synchronization start signal (SY_EXE) is received.

When receiving the synchronization start signal (SY_EXE) from the synchronization control unit BSY1 (S204: YES), the synchronization correction unit SY1 sets the correction direction based on whether the calculated synchronization reference shift width satisfies equation (1) or equation (2) (S205).

The synchronization correction unit SY1 sets the smaller value between the value of the synchronization reference offset width and the value obtained by subtracting the synchronization reference offset width from the self-module period as the synchronization correction target time (S206). The synchronization correction unit SY1 sets an arbitrary unit time when performing synchronization correction as the synchronization correction width in the synchronization correction width register (S207).

The synchronization correction unit SY1 determines whether a synchronization correction execution request is received from the processor P1 (S208). If a synchronization correction execution request is not received from the processor P1 (S208: No), the process is put on standby until a synchronization correction execution request is received from the processor P1. If a synchronization correction execution request is received from the processor P1 (S208: Yes), the synchronization correction execution process described later is performed (S209).

Fig. 7 is a flowchart showing an example of synchronization correction execution processing. First, the synchronization correction unit SY1 determines whether the synchronization correction target time set in S206 of Fig. 6 is greater than 0 (S301). When the synchronization correction target time is less than 0 (S301: No), the synchronization correction execution processing ends.

When the synchronization correction target time is greater than 0 ( S301 : Yes), the synchronization correction unit SY1 determines whether the synchronization correction target time is equal to or less than the synchronization correction width set in S207 of FIG. 6 ( S302 ).

When the synchronization correction target time is less than the synchronization correction width (S302: Yes), the synchronization correction unit SY1 sets the synchronization correction target time as the actual correction time (S303). When this process is completed, the process proceeds to S305. When the synchronization correction target time is greater than the synchronization correction width (S302: No), the synchronization correction unit SY1 sets the synchronization correction width as the actual correction time (S304). When this process is completed, the process proceeds to S305.

In S305, the synchronization correction unit SY1 determines the correction direction set in S205 of FIG. 6 (S305). When the correction direction set is the + (positive) direction, the synchronization correction unit SY1 sets the time obtained by adding the actual correction time to the self-module cycle as the next cycle (S306). When this process is completed, the process proceeds to S308. When the correction direction set is the - (negative) direction, the synchronization correction unit SY1 sets the time obtained by subtracting the actual correction time from the self-module cycle as the next cycle (S306). When this process is completed, the process proceeds to S308.

The synchronization correction unit SY1 sets the value obtained by subtracting the actual correction time from the synchronization correction target time as the synchronization correction target time (S308). The synchronization correction unit SY1 determines whether the synchronization correction target time is greater than 0 (S309).

When the synchronization correction target time is greater than 0 (S309: Yes), the process returns to S302, and the processes of S302, S304 to S309 are repeatedly executed until the synchronization correction target time becomes 0. When the synchronization correction target time is less than 0 (S309: No), the synchronization correction unit SY1 turns off the synchronization start request (SY_RQ1) (S310), and ends the synchronization correction execution process.

In addition, the present invention is not limited to the above-mentioned embodiment, and various changes can be made to implement. In the above-mentioned embodiment, the size, shape, function, etc. of the constituent elements illustrated in the accompanying drawings are not limited thereto, and can be appropriately changed within the scope of the effect of the present invention. In addition, as long as it does not depart from the scope of the purpose of the present invention, it can be appropriately changed to implement.

Industrial Applicability

As described above, the present invention can synchronize the module cycles of the modules constituting the programmable controller system, and is preferably applied to equipment using the programmable controller system.

Claims (9)

1. A programmable controller system comprising a substrate and a plurality of modules connected to the substrate, characterized in that,

The substrate is provided with a synchronization control part for controlling the synchronization of the plurality of modules,

The plurality of modules each include:

An independent clock generation section for generating an independent clock;

A counter unit that generates a self-module period based on the independent clock generated by the independent clock generation unit; and

A synchronization correction unit that calculates an offset of the self-module period from the self-module period and a synchronization reference point based on a synchronization start signal outputted from the synchronization control unit, corrects the self-module period based on the calculated offset,

Wherein the synchronization correction section performs correction of subtracting or adding an amount corresponding to the synchronization correction target time in a next cycle in a case where the synchronization correction target time is the same as or shorter than a synchronization correction amplitude, the synchronization correction target time being an overall time at which synchronization correction is performed, the synchronization correction amplitude being an arbitrary unit time at which synchronization correction is performed,

When the synchronization correction target time is longer than the synchronization correction amplitude, the synchronization correction unit performs correction to increase or decrease the amount corresponding to the synchronization correction amplitude by one cycle from the cycle time after the next cycle.

2. The programmable controller system of claim 1, wherein the controller is configured to control the programmable logic device,

The synchronization correction unit sets the synchronization reference point based on a rising edge or a falling edge of the synchronization start signal.

3. A programmable controller system according to claim 1 or 2, characterized in that,

The synchronization correction unit sets a time point after a predetermined time has elapsed since the synchronization start signal was output as the synchronization reference point.

4. A programmable controller system according to claim 1 or 2, characterized in that,

The synchronization correction unit performs correction of subtraction or addition for the self-module period by one period.

5. A programmable controller system according to claim 1 or 2, characterized in that,

The synchronization correction unit performs subtraction or addition correction on the self-module period so as to divide the period into n periods, where n >2.

6. A programmable controller system according to claim 1 or 2, characterized in that,

At the time of initialization, the synchronization correction section performs correction of subtraction or addition for the self-module period by one period,

At the time when at least one of the modules operates, the synchronization correction unit performs subtraction or addition correction on the self-module cycle so as to divide the self-module cycle into n cycles, where n >2.

7. A programmable controller system according to claim 1 or 2, characterized in that,

The substrate further includes a reference clock generating section for generating a reference time,

The synchronization control unit outputs the synchronization start signal to each of the modules based on the reference time.

8. The programmable controller system of claim 7, wherein the controller is configured to control the programmable logic device,

When the parts per million error between the independent clock generating section of each module and the reference clock generating section on the substrate exceeds a constant range, correction is performed by temporarily subtracting or adding for each module independent period, thereby continuously maintaining synchronization.

9. A module of a programmable controller system, a plurality of the modules being connected to a substrate provided with a synchronization control section for controlling synchronization of the plurality of the modules, the module being characterized in that,

Each of the plurality of modules includes:

An independent clock generation section for generating an independent clock;

A counter unit that generates a self-module period based on the independent clock generated by the independent clock generation unit; and

A synchronization correction unit that calculates an offset of the self-module period from the self-module period and a synchronization reference point based on a synchronization start signal outputted from the synchronization control unit, corrects the self-module period based on the calculated offset,

Wherein the synchronization correction section performs correction of subtracting or adding an amount corresponding to the synchronization correction target time in a next cycle in a case where the synchronization correction target time is the same as or shorter than a synchronization correction amplitude, the synchronization correction target time being an overall time at which synchronization correction is performed, the synchronization correction amplitude being an arbitrary unit time at which synchronization correction is performed,

When the synchronization correction target time is longer than the synchronization correction amplitude, the synchronization correction unit performs correction to increase or decrease the amount corresponding to the synchronization correction amplitude by one cycle from the cycle time after the next cycle.