CN112825332B - LDMOS device and method for manufacturing the same - Google Patents

Abstract

The invention discloses an LDMOS device, which comprises: a channel region and a drift region in lateral contact, a source region formed at a surface of the channel region and self-aligned to the first side of the gate structure. The drift region is directly connected to the drain electrode composed of the front metal layer through the drift region lead-out region and the second contact hole, so that a drain-free structure is formed, and the length of the drift region is directly determined by the distance between the first side surface of the drift region and the second contact hole. The invention also discloses a manufacturing method of the LDMOS device. The invention can reduce the length of the drift region, thereby reducing the output capacitance of the device and reducing the loss of the device in the switching process.

Description

LDMOS device and method for manufacturing the same

Technical Field

The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to an LDMOS device. The present invention also relates to a manufacturing method of the LDMOS device.

Background technique

LDMOS devices have high breakdown voltage and low capacitance, mainly input capacitance (Ciss), and are widely used in BCD process to realize high-voltage tubes or RF power amplifier tubes.

For an LDMOS device with excellent performance, we not only want its input capacitance to be low, but also want its output capacitance (Coss) to be low. As shown in Figure 1, it is a cross-sectional structure diagram of an existing LDMOS device; taking an N-type device as an example, the existing LDMOS devices include:

A P-type doped channel region 2 and an N-type doped drift region 3 are formed on a semiconductor substrate 1 , and a first side surface of the drift region 3 is in lateral contact with the channel region 2 .

The gate structure covers the surface of the channel region 2 and extends onto the drift region 3; the surface of the channel region 2 covered by the gate structure is used to form a channel.

The gate structure includes a gate dielectric layer 6 and a gate conductive material layer 4 which are stacked in sequence.

An N-type heavily doped source region 5 a is formed on the surface of the channel region 2 and is self-aligned with the first side surface of the gate structure.

The N-type heavily doped drain region 5 b is formed on the surface of the drift region 3 and is spaced apart from the second side surface of the gate structure.

The top of the source region 5 a is connected to the source electrode composed of the front metal layer through a first contact hole 8 .

The top of the drain region 5 b is connected to the drain electrode composed of the front metal layer through the second contact hole 7 .

Typically, an epitaxial layer is formed on the surface of the semiconductor substrate 1. The resistivity of the epitaxial layer is related to the breakdown voltage required by the LDMOS device. The higher the breakdown voltage required by the LDMOS device, the higher the resistivity and the thicker the epitaxial layer.

The channel region lead-out region 9 can be implemented by photolithography definition plus ion implantation alone, or it can be implanted after the opening of the corresponding first contact hole 8 is opened so as to be formed only at the bottom of the corresponding first contact hole 8. For N-type devices, the implanted impurity of the ion implantation of the channel region lead-out region 9 is usually BF2, the implantation energy is usually 40keV, and the implantation dose is as high as 1e15cm ^-2 . This makes the B ion concentration on the surface of the corresponding first contact hole 8 very high, thus increasing the doping concentration of the contact interface between the corresponding first contact hole 8 and the channel region 2, so that a good ohmic contact can be achieved. In addition, the dose of the doping ion implantation of the source region 5a is about 5e15cm ^-2 , so even if the ion implantation of the channel region lead-out region 9 is performed on the surface of the source region 5a corresponding to the bottom of the first contact hole 8, even after inversion, the doping concentration of the source region 5a is still very high, so the source region 5a can still achieve a good ohmic contact with the first contact hole 8.

Note that in the prior art, for LDMOS devices, the drain region 5b is definitely required, otherwise the second contact hole 7 will be directly connected to the drift region 3, and because the doping concentration of the drift region 3 is low, the contact formed between the second contact hole 7 and the drift region 3 is a Schottky contact rather than an Ohmic contact. In this way, the on-resistance of the LDMOS device will become very large.

However, due to the presence of the drain region 5b, the length of the entire drift region 3 will be increased, as explained below:

As shown in Fig. 1, the length L3 of the drain region 5b is usually between 0.15 μm and 0.3 μm. For high-voltage LDMOS devices, such as devices with a breakdown voltage exceeding 100 V, the length L1 of the drift region 3 is usually above 5 μm, and this distance L3 is not so important. L2 is the difference between L1 and L3, corresponding to the length of the drift region 3 after deducting the drain region 5b.

However, for RF power devices, the breakdown voltage is usually 65V, and the length of drift region 3 is usually only 2.6μm; or for some lower voltage LDMOS devices, such as devices with a breakdown voltage of 30V, the length of drift region 3 is usually only 1.0μm, then this increased distance L2 becomes particularly important. The increase in this distance will mainly increase the output capacitance of the LDMOS device, thereby increasing the loss of the LDMOS device during the switching process.

Summary of the invention

The technical problem to be solved by the present invention is to provide an LDMOS device that can reduce the length of the drift region, thereby reducing the output capacitance of the device and reducing the loss of the device during the switching process. To this end, the present invention also provides a method for manufacturing the LDMOS device.

In order to solve the above technical problems, the LDMOS device provided by the present invention comprises:

A channel region doped with a second conductivity type and a drift region doped with a first conductivity type are formed on a semiconductor substrate, wherein a first side surface of the drift region is in lateral contact with the channel region.

The gate structure covers the surface of the channel region and extends onto the drift region; the surface of the channel region covered by the gate structure is used to form a channel.

The gate structure includes a gate dielectric layer and a gate conductive material layer stacked in sequence.

A source region heavily doped with a first conductivity type is formed on a surface of the channel region and is self-aligned with a first side surface of the gate structure.

The top of the source region is connected to a source electrode composed of a front metal layer through a first contact hole.

A second contact hole is formed at the top of the drift region, and the second contact hole is spaced a distance apart from the second side of the gate structure in a lateral direction.

A drift region lead-out region is self-alignedly formed at the bottom of the second contact hole by implantation of heavily doped ions of the first conductive type, and the drift region lead-out region and the second contact hole form an ohmic contact. The drift region is directly connected to the drain composed of the front metal layer through the drift region lead-out region and the second contact hole, thereby forming a drain-free structure. The drain-free structure enables the length of the drift region to be directly determined by the distance between the first side surface of the drift region and the second contact hole, thereby eliminating the influence of the drain region on the length of the drift region, reducing the length of the drift region and thereby reducing the output capacitance of the device.

The length direction of the channel is the direction from the source region to the drift region; the width direction of the channel is the direction perpendicular to the length direction of the channel.

In the width direction of the channel, the gate structure, the source region, the channel region and the drift region all extend continuously, the first contact hole includes more than one and is selectively arranged in the source region, and the second contact hole includes more than one and is selectively arranged in the drift region.

A further improvement is that a channel region lead-out region formed by implantation of heavily doped ions of the second conductivity type is also formed on the surface of the channel region, and the top of the channel region lead-out region is connected to the source through a corresponding first contact hole.

A further improvement is that the first conductivity type heavily doped ion implanted impurities of the drift region lead-out area are also implanted into the bottom of the corresponding first contact hole, the implantation dose of the first conductivity type heavily doped ions of the drift region lead-out area is less than the implantation dose of the second conductivity type heavily doped ions of the channel region lead-out area, and the surface of the channel region lead-out area still maintains the second conductivity type heavily doped and enables the channel region lead-out area and the first contact hole corresponding to the top to form an ohmic contact.

A further improvement is that a first injection region is also formed in the drift region, the first injection region is lightly doped with the first conductivity type, the first injection region is superimposed on the drift region near the side of the second contact hole and the junction depth of the first injection region is greater than or equal to the junction depth of the drift region, the second contact hole is located at the top of the first injection region, and in the direction from the second contact hole to the first side of the drift region, the overlapping area of the first injection region and the drift region has a concentration gradient structure with a gradually decreasing doping concentration.

A further improvement is that more than one layer of field plates are formed on the top of the drift region, and the field plates are connected to the source; the field plates are metal field plates or polysilicon field plates.

A further improvement is that a field oxide is formed in the drift region near the first side surface of the drift region, and the gate structure further extends above the field oxide.

A further improvement is that the LDMOS device is an N-type device, the first conductivity type is N-type, the second conductivity type is P-type, the implanted impurities of the first conductivity type heavily doped ion implantation in the drift region lead-out region are phosphorus or arsenic, the implantation energy is 30keV~100keV, and the implantation dose is 1e15cm ^-2 ~2e15cm ^-2 ; or, the LDMOS device is an N-type device, the first conductivity type is N-type, the second conductivity type is P-type, the implanted impurities of the first conductivity type heavily doped ion implantation in the drift region lead-out region include boron, the implantation energy is 30keV~100keV, and the implantation dose is 1e15cm ^-2 ~2e15cm ^-2 .

In order to solve the above technical problems, the present invention provides a method for manufacturing an LDMOS device, comprising the following steps:

Step 1: providing a semiconductor substrate, and completing a process of forming a channel region doped with a second conductivity type, a drift region doped with a first conductivity type, and a gate structure on the semiconductor substrate.

The first side surface of the drift region is in lateral contact with the channel region.

The gate structure covers the surface of the channel region and extends onto the drift region; the surface of the channel region covered by the gate structure is used to form a channel.

The gate structure includes a gate dielectric layer and a gate conductive material layer stacked in sequence.

Step 2: Using the first side surface of the gate structure as a self-alignment condition, implanting heavily doped ions of the first conductivity type into the surface of the channel region to form a source region, and eliminating the drain region formation process while forming the source region.

Step three, forming an interlayer film; performing etching to form an opening of a contact hole passing through the interlayer film, and filling a metal layer in the opening of the contact hole to form the contact hole; forming a front metal layer and patterning the front metal layer to form a source, a drain and a gate.

The top of the source region is connected to the source electrode through a first contact hole.

A second contact hole is formed at the top of the drift region, and the second contact hole is spaced a distance apart from the second side of the gate structure in a lateral direction.

After the opening of the contact hole is opened and before the metal is filled, the method also includes the step of performing a first conductive type heavily doped ion implantation to form a drift region lead-out region on the surface of the drift region at the bottom of the second contact hole, wherein the drift region lead-out region and the second contact hole form an ohmic contact, and the drift region is directly connected to the drain composed of the front metal layer through the drift region lead-out region and the second contact hole, thereby forming a drain-free structure, wherein the drain-free structure enables the length of the drift region to be directly determined by the spacing between the first side surface of the drift region and the second contact hole, thereby eliminating the influence of the drain region on the length of the drift region, reducing the length of the drift region and thereby reducing the output capacitance of the device.

The length direction of the channel is the direction from the source region to the drift region; the width direction of the channel is the direction perpendicular to the length direction of the channel.

In the width direction of the channel, the gate structure, the source region, the channel region and the drift region all extend continuously, the first contact hole includes more than one and is selectively arranged in the source region, and the second contact hole includes more than one and is selectively arranged in the drift region.

A further improvement is that before forming the interlayer film, it also includes the step of implanting second conductive type heavily doped ions into a channel region lead-out region formed on the surface of the channel region. In step three, a corresponding first contact hole is also formed in the channel region lead-out region and the source is connected through the corresponding first contact hole.

A further improvement is that the first conductivity type heavily doped ion implanted impurities of the drift region lead-out area are also implanted into the bottom of the corresponding first contact hole, the implantation dose of the first conductivity type heavily doped ions of the drift region lead-out area is less than the implantation dose of the second conductivity type heavily doped ions of the channel region lead-out area, and the surface of the channel region lead-out area still maintains the second conductivity type heavily doped and enables the channel region lead-out area and the first contact hole corresponding to the top to form an ohmic contact.

A further improvement is that before forming the interlayer film, the step also includes forming a first injection region in the drift region, the first injection region is lightly doped with the first conductivity type, the first injection region is superimposed on the drift region near the side of the second contact hole and the junction depth of the first injection region is greater than or equal to the junction depth of the drift region, the second contact hole is located at the top of the first injection region, and in the direction from the second contact hole to the first side of the drift region, the overlapping area of the first injection region and the drift region has a concentration gradient structure with a gradually decreasing doping concentration.

A further improvement is that more than one layer of field plates are formed on the top of the drift region, and the field plates are connected to the source; the field plates are metal field plates or polysilicon field plates.

A further improvement is that a field oxide is formed in the drift region near the first side of the drift region, and the gate structure further extends above the field oxide.

A further improvement is that the semiconductor substrate is a silicon substrate.

The gate dielectric layer is a gate oxide layer, which is formed by a thermal oxidation process.

The gate conductive material layer is a polysilicon gate.

A further improvement is that the LDMOS device is an N-type device, the first conductivity type is N-type, the second conductivity type is P-type, the implanted impurities of the first conductivity type heavily doped ion implantation in the drift region lead-out region are phosphorus or arsenic, the implantation energy is 30keV~100keV, and the implantation dose is 1e15cm ^-2 ~2e15cm ^-2 ; or, the LDMOS device is an N-type device, the first conductivity type is N-type, the second conductivity type is P-type, the implanted impurities of the first conductivity type heavily doped ion implantation in the drift region lead-out region include boron, the implantation energy is 30keV~100keV, and the implantation dose is 1e15cm ^-2 ~2e15cm ^-2 .

The present invention eliminates the drain region in the drift region of the LDMOS device and directly leads the drift region to the drain composed of the front metal layer through a contact hole with a drift region lead-out region at the bottom, namely, a second contact hole. The drift region lead-out region forms an ohmic contact with the second contact hole. Compared with the prior art in which the LDMOS device occupies a certain width of the drift region, the present invention can reduce the length of the drift region while maintaining the voltage resistance of the device, thereby reducing the output capacitance of the device and reducing the loss of the device during the switching process.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

FIG1 is a cross-sectional structural diagram of a conventional LDMOS device;

2 is a cross-sectional structural diagram of an LDMOS device according to a first embodiment of the present invention;

3 is a cross-sectional structural diagram of an LDMOS device according to a second embodiment of the present invention;

4 is a cross-sectional structural diagram of an LDMOS device according to a third embodiment of the present invention;

5 is a cross-sectional structural diagram of an LDMOS device according to a fourth embodiment of the present invention;

FIG. 6 is a cross-sectional structural diagram of an LDMOS device according to a fifth embodiment of the present invention.

Detailed ways

As shown in FIG. 2 , it is a cross-sectional structural diagram of an LDMOS device according to a first embodiment of the present invention; the LDMOS device according to the first embodiment of the present invention comprises:

A channel region 2 doped with the second conductivity type and a drift region 3 doped with the first conductivity type are formed on a semiconductor substrate 1 , and a first side surface of the drift region 3 is in lateral contact with the channel region 2 .

The gate structure covers the surface of the channel region 2 and extends onto the drift region 3; the surface of the channel region 2 covered by the gate structure is used to form a channel.

The gate structure includes a gate dielectric layer 6 and a gate conductive material layer 4 which are stacked in sequence.

A heavily doped source region 5 a of the first conductivity type is formed on the surface of the channel region 2 and is self-aligned with the first side surface of the gate structure.

The top of the source region 5 a is connected to the source electrode composed of the front metal layer through a first contact hole 8 .

A corresponding contact hole is also formed on the top of the gate conductive material layer 4 of the gate structure and is connected to the gate composed of the front metal layer through the corresponding contact hole on the top.

The second contact hole 7 is formed at the top of the drift region 3 , and the second contact hole 7 is spaced apart from the second side of the gate structure in a lateral direction.

A drift region lead-out region is self-alignedly formed at the bottom of the second contact hole 7 by implantation of heavily doped ions of the first conductive type. The drift region lead-out region and the second contact hole 7 form an ohmic contact. The drift region 3 is directly connected to the drain composed of the front metal layer through the drift region lead-out region and the second contact hole 7, thereby forming a drain-free structure. The drain-free structure enables the effective length of the drift region 3 to be directly determined by the distance between the first side surface of the drift region 3 and the second contact hole 7, thereby eliminating the influence of the drain region on the effective length of the drift region 3, reducing the effective length of the drift region 3 and thereby reducing the output capacitance of the device.

The length direction of the channel is the direction from the source region 5 a to the drift region 3 ; the width direction of the channel is the direction perpendicular to the length direction of the channel.

In the width direction along the channel (not shown), the gate structure, the source region 5a, the channel region 2 and the drift region 3 all extend continuously, the first contact hole 8 includes more than one and is selectively arranged in the source region 5a, and the second contact hole 7 includes more than one and is selectively arranged in the drift region 3.

A channel region lead-out region 9 formed by second conductivity type heavily doped ion implantation is also formed on the surface of the channel region 2 , and the top of the channel region lead-out region 9 is connected to the source through a corresponding first contact hole 8 .

The first conductivity type heavily doped ion-implanted impurities of the drift region lead-out area are also injected into the bottom of the corresponding first contact hole 8, and the injection dose of the first conductivity type heavily doped ions of the drift region lead-out area is less than the injection dose of the second conductivity type heavily doped ions of the channel region lead-out area 9, and the surface of the channel region lead-out area 9 still maintains the second conductivity type heavily doped and enables the channel region lead-out area 9 and the first contact hole 8 corresponding to the top to form an ohmic contact.

In the first embodiment of the present invention, the LDMOS device is an N-type device, the first conductivity type is N-type, the second conductivity type is P-type, the implanted impurity of the first conductivity type heavily doped ion implantation in the drift region lead-out region is phosphorus or arsenic, the implantation energy is 30keV to 100keV, and the implantation dose is 1e15cm ^-2 to 2e15cm ^-2 . In other embodiments, the LDMOS device can also be an N-type device, the first conductivity type is N-type, the second conductivity type is P-type, the implanted impurity of the first conductivity type heavily doped ion implantation in the drift region lead-out region includes boron, the implantation energy is 30keV to 100keV, and the implantation dose is 1e15cm ^-2 to 2e15cm ^-2 .

The semiconductor substrate 1 is a silicon substrate. The gate dielectric layer 6 is a gate oxide layer formed by a thermal oxidation process. The gate conductive material layer 4 is a polysilicon gate.

Typically, an epitaxial layer is formed on the surface of the semiconductor substrate 1. The resistivity of the epitaxial layer is related to the breakdown voltage required by the LDMOS device. The higher the breakdown voltage required by the LDMOS device, the higher the resistivity and the thicker the epitaxial layer.

The channel region lead-out region 9 can be implemented by photolithography definition plus ion implantation alone, or it can be implanted after the opening of the corresponding first contact hole 8 is opened so as to be formed only at the bottom of the corresponding first contact hole 8. For N-type devices, the implanted impurity of the ion implantation of the channel region lead-out region 9 is usually BF2, the implantation energy is usually 40keV, and the implantation dose is as high as 1e15cm ^-2 . This makes the B ion concentration on the surface of the corresponding first contact hole 8 very high, thus increasing the doping concentration of the contact interface between the corresponding first contact hole 8 and the channel region 2, so that a good ohmic contact can be achieved. In addition, the dose of the doping ion implantation of the source region 5a is about 5e15cm ^-2 , so even if the ion implantation of the channel region lead-out region 9 is performed on the surface of the source region 5a corresponding to the bottom of the first contact hole 8, even after inversion, the doping concentration of the source region 5a is still very high, so the source region 5a can still achieve a good ohmic contact with the first contact hole 8.

The length of the drift region 3 varies according to the withstand voltage requirements of the LDMOS device, for example:

For the LDMOS device for high voltage applications with a breakdown voltage exceeding 100V, the length of the drift region 3 is usually above 5 μm.

For the LDMOS device used as a radio frequency power device, the breakdown voltage is usually 65 V. The length of the drift region 3 is usually only 2.6 μm.

For some lower voltage LDMOS devices, such as devices with a breakdown voltage of 30V, the length of the drift region 3 is usually only 1.0 μm.

The first embodiment of the present invention eliminates the drain region in the drift region 3 of the LDMOS device and directly leads the drift region 3 to the drain composed of the front metal layer through a contact hole with a drift region lead-out region at the bottom, namely, a second contact hole 7. The drift region lead-out region forms an ohmic contact with the second contact hole 7. Compared with the LDMOS device in the prior art that occupies a certain width of the drift region 3, the first embodiment of the present invention can reduce the length of the drift region 3 while maintaining the voltage resistance of the device, thereby reducing the output capacitance of the device and reducing the loss of the device during the switching process.

The LDMOS device of the second embodiment of the present invention:

The difference between the LDMOS device of the second embodiment of the present invention and the LDMOS device of the first embodiment of the present invention is that the LDMOS device of the second embodiment of the present invention has the following features:

As shown in Figure 3, it is a cross-sectional structure diagram of the LDMOS device of the second embodiment of the present invention; a first injection region 10 is also formed in the drift region 3, the first injection region 10 is lightly doped with the first conductivity type, the first injection region 10 is superimposed on the drift region 3 near the side of the second contact hole 7 and the junction depth of the first injection region 10 is greater than or equal to the junction depth of the drift region 3, the second contact hole 7 is located at the top of the first injection region 10, and in the direction from the second contact hole 7 to the first side of the drift region 3, the overlapping area of the first injection region 10 and the drift region 3 has a concentration gradient structure with a gradually decreasing doping concentration, which is beneficial to improving the robustness of the device.

The LDMOS device of the third embodiment of the present invention:

The difference between the LDMOS device of the third embodiment of the present invention and the LDMOS device of the first embodiment of the present invention is that the LDMOS device of the third embodiment of the present invention has the following features:

As shown in FIG. 4 , it is a cross-sectional structural diagram of an LDMOS device according to a third embodiment of the present invention; a field plate 11 is formed on the top of the drift region 3 , and the field plate 11 is connected to the source.

The field plate 11 is a metal field plate or a polysilicon field plate. The polysilicon field plate is usually made of heavily doped polysilicon. The metal field plate can be a material with low resistivity such as metal silicide.

The advantages of the field plate 11 are as follows:

It can shield the gate and the drift region 3, thereby greatly reducing the gate-drain coupling capacitance (Cgd), but it will increase the gate-source coupling capacitance (Cgs), where Cgs is mainly the capacitance of the gate and the field plate 11. With the field plate 11, the Cgd of the LDMOS device with a breakdown voltage of 65V at present can be 10fF per millimeter of gate width at 28V, that is, for a device with a total gate width of 1mm, the Cgd of the device with the field plate 11 at 28V can be 10fF.

The field plate 11 can also reduce the electric field strength at the gate and the drift region 3. In addition, the field plate 11 on the drift region 3 can also be depleted in the longitudinal direction with the drift region 3, thereby increasing the doping concentration of the drift region 3 and reducing the specific on-resistance.

For these reasons, the field plate structure, that is, the structure formed with the field plate 11 is the mainstream of the current LDMOS device. FIG. 4 adopts a single-layer field plate structure, that is, only one layer of the field plate 11 is formed.

The LDMOS device of the fourth embodiment of the present invention:

The difference between the LDMOS device of the fourth embodiment of the present invention and the LDMOS device of the third embodiment of the present invention is that the LDMOS device of the fourth embodiment of the present invention has the following features:

As shown in FIG5 , it is a cross-sectional structural diagram of the LDMOS device of the third embodiment of the present invention; it includes a multi-layer field plate structure, and FIG5 shows a two-layer field plate structure, wherein the first layer of field plate is marked with a mark 11, and the first layer of field plate 11 is the same as the field plate 11 in FIG4 . The second layer of field plate is marked with a mark 12. The multi-layer field plate structure is currently widely used in LDMOS devices with a breakdown voltage exceeding 100V. Both field plates 11 and 12 are connected to the source through corresponding contact holes or through holes.

The multi-layer field plate structure can better optimize the electric field intensity distribution of the drift region 3 , thereby further increasing the doping concentration of the drift region 3 without reducing the breakdown voltage, thereby obtaining a lower specific on-resistance.

The fifth embodiment of the present invention is an LDMOS device:

The difference between the LDMOS device of the fifth embodiment of the present invention and the LDMOS device of the first embodiment of the present invention is that the LDMOS device of the fifth embodiment of the present invention has the following features:

As shown in FIG6 , it is a cross-sectional structural diagram of the LDMOS device of the fifth embodiment of the present invention; a field oxide 13 is formed in the drift region 3 near the first side of the drift region 3, and the gate structure also extends above the field oxide 13. The shallow trench isolation (STI) process is widely used in the BCD process to achieve isolation. The field oxide 13 in FIG6 is formed by the STI process, and the function of the field oxide 13 is to reduce the electric field strength at the junction of the gate and the drift region, which is beneficial to improve the reliability of the device.

Various combinations of the embodiments of the present invention can also provide device structures of various other embodiments, which will not be listed here one by one.

A method for manufacturing an LDMOS device according to a first embodiment of the present invention:

The manufacturing method of the LDMOS device according to the first embodiment of the present invention comprises the following steps:

Step 1: providing a semiconductor substrate 1, and completing a process of forming a second conductivity type doped channel region 2, a first conductivity type doped drift region 3, and a gate structure on the semiconductor substrate 1.

The first side surface of the drift region 3 is in lateral contact with the channel region 2 .

The gate structure covers the surface of the channel region 2 and extends onto the drift region 3; the surface of the channel region 2 covered by the gate structure is used to form a channel.

The gate structure includes a gate dielectric layer 6 and a gate conductive material layer 4 which are stacked in sequence.

Step 2: Using the first side of the gate structure as a self-alignment condition, first conductivity type heavily doped ions are implanted on the surface of the channel region 2 to form a source region 5a, and while forming the source region 5a, the drain region formation process is eliminated.

Step three, forming an interlayer film; performing etching to form an opening of a contact hole passing through the interlayer film, and filling a metal layer in the opening of the contact hole to form the contact hole; forming a front metal layer and patterning the front metal layer to form a source, a drain and a gate.

The top of the source region 5 a is connected to the source electrode through a first contact hole 8 .

The top of the gate conductive material layer 4 of the gate structure is connected to the gate through a corresponding contact hole.

The second contact hole 7 is formed at the top of the drift region 3 , and the second contact hole 7 is spaced apart from the second side of the gate structure in a lateral direction.

After the opening of the contact hole is opened and before the metal is filled, the method further includes the step of implanting heavily doped ions of the first conductive type to form a drift region lead-out region on the surface of the drift region 3 at the bottom of the second contact hole 7, wherein the drift region lead-out region and the second contact hole 7 form an ohmic contact, and the drift region 3 is directly connected to the drain composed of the front metal layer through the drift region lead-out region and the second contact hole 7, thereby forming a drain-free structure, wherein the drain-free structure enables the effective length of the drift region 3 to be directly determined by the spacing between the first side surface of the drift region 3 and the second contact hole 7, thereby eliminating the influence of the drain region on the effective length of the drift region 3, reducing the effective length of the drift region 3 and thereby reducing the output capacitance of the device.

The length direction of the channel is the direction from the source region 5 a to the drift region 3 ; the width direction of the channel is the direction perpendicular to the length direction of the channel.

In the width direction along the channel, the gate structure, the source region 5a, the channel region 2 and the drift region 3 extend continuously, the first contact hole 8 includes more than one and is selectively arranged in the source region 5a, and the second contact hole 7 includes more than one and is selectively arranged in the drift region 3.

In the method of the first embodiment of the present invention, before forming the interlayer film, it also includes the step of implanting second conductive type heavily doped ions into the surface of the channel region 2 to form a channel region lead-out region 9. In step three, a corresponding first contact hole 8 is also formed in the channel region lead-out region 9 and the source is connected through the corresponding first contact hole 8.

The first conductivity type heavily doped ion-implanted impurities of the drift region lead-out area are also injected into the bottom of the corresponding first contact hole 8, and the injection dose of the first conductivity type heavily doped ions of the drift region lead-out area is less than the injection dose of the second conductivity type heavily doped ions of the channel region lead-out area 9, and the surface of the channel region lead-out area 9 still maintains the second conductivity type heavily doped and enables the channel region lead-out area 9 and the first contact hole 8 corresponding to the top to form an ohmic contact.

In the first embodiment of the present invention, the LDMOS device is an N-type device, the first conductivity type is N-type, the second conductivity type is P-type, the first conductivity type heavily doped ion implanted impurities in the drift region lead-out region are phosphorus or arsenic, the implantation energy is 30keV to 100keV, and the implantation dose is 1e15cm ^-2 to 2e15cm ^-2 . In other embodiments, the LDMOS device is an N-type device, the first conductivity type is N-type, the second conductivity type is P-type, the first conductivity type heavily doped ion implanted impurities in the drift region lead-out region include boron, the implantation energy is 30keV to 100keV, and the implantation dose is 1e15cm ^-2 to 2e15cm ^-2 .

The semiconductor substrate 1 is a silicon substrate. The gate dielectric layer 6 is a gate oxide layer formed by a thermal oxidation process. The gate conductive material layer 4 is a polysilicon gate.

Typically, an epitaxial layer is formed on the surface of the semiconductor substrate 1. The resistivity of the epitaxial layer is related to the breakdown voltage required by the LDMOS device. The higher the breakdown voltage required by the LDMOS device, the higher the resistivity and the thicker the epitaxial layer.

The method for manufacturing the LDMOS device according to the first embodiment of the present invention forms the device according to the first embodiment of the present invention shown in FIG. 2 .

A method for manufacturing an LDMOS device according to a second embodiment of the present invention:

The difference between the method for manufacturing the LDMOS device of the second embodiment of the present invention and the method for manufacturing the LDMOS device of the first embodiment of the present invention is that the method for manufacturing the LDMOS device of the second embodiment of the present invention has the following features:

Before forming the interlayer film, the step of forming a first injection region 10 in the drift region 3 is also included, the first injection region 10 is lightly doped with the first conductivity type, the first injection region 10 is superimposed in the drift region 3 near the second contact hole 7 and the junction depth of the first injection region 10 is greater than or equal to the junction depth of the drift region 3, the second contact hole 7 is located at the top of the first injection region 10, and in the direction from the second contact hole 7 to the first side of the drift region 3, the superimposed area of the first injection region 10 and the drift region 3 has a concentration gradient structure with a gradually decreasing doping concentration. The manufacturing method of the LDMOS device of the second embodiment of the present invention forms the device of the second embodiment of the present invention shown in FIG. 3.

A method for manufacturing an LDMOS device according to a third embodiment of the present invention:

The difference between the method for manufacturing the LDMOS device of the third embodiment of the present invention and the method for manufacturing the LDMOS device of the first embodiment of the present invention is that the method for manufacturing the LDMOS device of the third embodiment of the present invention has the following features:

A field plate 11 is formed on the top of the drift region 3, and the field plate 11 is connected to the source; the field plate 11 is a metal field plate 11 or a polysilicon field plate 11. The manufacturing method of the LDMOS device of the third embodiment of the present invention forms the device of the third embodiment of the present invention shown in FIG.

A method for manufacturing an LDMOS device according to a fourth embodiment of the present invention:

The difference between the manufacturing method of the LDMOS device of the fourth embodiment of the present invention and the manufacturing method of the LDMOS device of the third embodiment of the present invention is that the manufacturing method of the LDMOS device of the fourth embodiment of the present invention has the following features:

More than two layers of field plates 11 are formed on the top of the drift region 3, and each layer of the field plates 11 is connected to the source; the field plates 11 are metal field plates 11 or polysilicon field plates 11. The manufacturing method of the LDMOS device of the fourth embodiment of the present invention forms the device of the fourth embodiment of the present invention shown in FIG. 5 .

A method for manufacturing an LDMOS device according to a fifth embodiment of the present invention:

The difference between the manufacturing method of the LDMOS device of the fifth embodiment of the present invention and the manufacturing method of the LDMOS device of the first embodiment of the present invention is that the manufacturing method of the LDMOS device of the fifth embodiment of the present invention has the following features:

A field oxide 13 is formed in the drift region 3 near a first side surface of the drift region 3 , and the gate structure further extends to above the field oxide 13 .

Typically, the field oxide 13 is formed by using an STI process. The field oxide 13 can be formed before or after the drift region 3 is formed.

The method for manufacturing the LDMOS device according to the fifth embodiment of the present invention forms the device according to the fifth embodiment of the present invention shown in FIG. 6 .

Various combinations of the embodiments of the present invention can also yield other embodiments, which will not be listed here one by one.

The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be regarded as the protection scope of the present invention.

Claims (15)

1. An LDMOS device, comprising:

a second conductivity type doped channel region and a first conductivity type doped drift region formed on a semiconductor substrate, a first side of the drift region being in lateral contact with the channel region;

a gate structure covers the channel region surface and extends onto the drift region; a surface of the channel region covered by the gate structure is used to form a channel;

the grid structure comprises a grid dielectric layer and a grid conductive material layer which are sequentially overlapped;

a heavily doped source region of the first conductivity type formed on a surface of the channel region and self-aligned to a first side of the gate structure;

the top of the source region is connected to a source electrode formed by the front metal layer through a first contact hole;

a second contact hole is formed on top of the drift region, the second contact hole being laterally spaced apart from the second side of the gate structure;

a drift region leading-out region formed by the first conductive type heavy doping ion injection is formed at the bottom of the second contact hole in a self-aligning mode, ohmic contact is formed between the drift region leading-out region and the second contact hole, the drift region is directly connected to a drain electrode formed by a front metal layer through the drift region leading-out region and the second contact hole, so that a drain-free region structure is formed, the length of the drift region is directly determined by the distance between the first side surface of the drift region and the second contact hole, the influence of a drain region on the length of the drift region is eliminated, the length of the drift region is reduced, and the output capacitance of a device is reduced;

the length direction of the channel is the direction from the source region to the drift region; the width direction of the channel is a direction perpendicular to the length direction of the channel;

the gate structure, the source region, the channel region, and the drift region all extend continuously in a width direction along the channel, the first contact hole includes one or more and is selectively provided in the source region, and the second contact hole includes one or more and is selectively provided in the drift region.

2. The LDMOS device of claim 1, wherein: and a channel region leading-out region formed by second conductive type heavy doping ion implantation is formed on the surface of the channel region, and the top of the channel region leading-out region is connected with the source electrode through a corresponding first contact hole.

3. The LDMOS device of claim 2, wherein: the first conductive type heavily doped ion implantation impurity of the drift region extraction region is also implanted into the bottom of the corresponding first contact hole, the implantation dosage of the first conductive type heavily doped ion implantation of the drift region extraction region is smaller than that of the second conductive type heavily doped ion implantation of the channel region extraction region, the surface of the channel region extraction region still keeps the second conductive type heavily doped, and ohmic contact can be formed between the channel region extraction region and the first contact hole corresponding to the top.

4. The LDMOS device of claim 1, wherein: the drift region is also provided with a first injection region which is lightly doped with a first conduction type, the first injection region is overlapped in the drift region close to one side of the second contact hole, the junction depth of the first injection region is larger than or equal to that of the drift region, the second contact hole is positioned at the top of the first injection region, and in the direction from the second contact hole to the first side face of the drift region, the overlapped region of the first injection region and the drift region is provided with a concentration gradient structure with the doping concentration gradually reduced.

5. The LDMOS device of claim 1, wherein: forming more than one layer of field plate on the top of the drift region, wherein the field plate is connected to the source electrode; the field plate is a metal field plate or a polysilicon field plate.

6. The LDMOS device of claim 1, wherein: a field oxide is formed in the drift region proximate to the first side of the drift region, the gate structure also extending over the field oxide.

7. The LDMOS device of any of claims 1-6, wherein: the LDMOS device is an N-type device, the first conductivity type is N-type, the second conductivity type is P-type, the implantation impurity of the first conductivity type heavy doping ion implantation of the drift region leading-out region is phosphorus or arsenic, the implantation energy is 30 keV-100 keV, and the implantation dosage is 1e15cm ^-2 ～2e15cm ^-2 The method comprises the steps of carrying out a first treatment on the surface of the Or the LDMOS device is an N-type device, the first conductivity type is N-type, the second conductivity type is P-type, the implantation impurity of the first conductivity type heavy doping ion implantation of the drift region leading-out region comprises boron, the implantation energy is 30 keV-100 keV, and the implantation dosage is 1e15cm ^-2 ～2e15cm ^-2 。

8. The manufacturing method of the LDMOS device is characterized by comprising the following steps of:

step one, providing a semiconductor substrate, and completing a process of forming a second conductive type doped channel region, a first conductive type doped drift region and a gate structure on the semiconductor substrate;

the first side surface of the drift region is in lateral contact with the channel region;

a gate structure covers the channel region surface and extends onto the drift region; a surface of the channel region covered by the gate structure is used to form a channel;

the grid structure comprises a grid dielectric layer and a grid conductive material layer which are sequentially overlapped;

secondly, carrying out first conductivity type heavy doping ion implantation on the surface of the channel region to form a source region by taking the first side face of the grid structure as a self-alignment condition, and canceling a drain region forming process while forming the source region;

step three, forming an interlayer film; etching to form an opening of a contact hole penetrating through the interlayer film, and filling a metal layer in the opening of the contact hole to form the contact hole; forming a front metal layer and patterning the front metal layer to form a source electrode, a drain electrode and a grid electrode;

the top of the source region is connected to the source electrode through a first contact hole;

a second contact hole is formed on top of the drift region, the second contact hole being laterally spaced apart from the second side of the gate structure;

after the opening of the contact hole is opened and before metal filling, the method further comprises the step of performing first conductivity type heavy doping ion injection on the surface of the drift region at the bottom of the second contact hole to form a drift region leading-out region, wherein the drift region leading-out region and the second contact hole form ohmic contact, the drift region is directly connected to a drain electrode formed by a front metal layer through the drift region leading-out region and the second contact hole, so that a non-drain region structure is formed, the length of the drift region is directly determined by the distance between the first side surface of the drift region and the second contact hole, and therefore the influence of a drain region on the length of the drift region is eliminated, the length of the drift region is reduced, and the output capacitance of a device is reduced;

the length direction of the channel is the direction from the source region to the drift region; the width direction of the channel is a direction perpendicular to the length direction of the channel;

the gate structure, the source region, the channel region, and the drift region all extend continuously in a width direction along the channel, the first contact hole includes one or more and is selectively provided in the source region, and the second contact hole includes one or more and is selectively provided in the drift region.

9. The method of manufacturing an LDMOS device of claim 8, wherein: before forming the interlayer film, the method further comprises the step of performing second conductivity type heavily doped ion implantation on a channel region leading-out region formed on the surface of the channel region, wherein in the step three, the corresponding first contact hole is formed in the channel region leading-out region and is connected with the source electrode through the corresponding first contact hole.

10. The method of manufacturing an LDMOS device of claim 9, wherein: the first conductive type heavily doped ion implantation impurity of the drift region extraction region is also implanted into the bottom of the corresponding first contact hole, the implantation dosage of the first conductive type heavily doped ion implantation of the drift region extraction region is smaller than that of the second conductive type heavily doped ion implantation of the channel region extraction region, the surface of the channel region extraction region still keeps the second conductive type heavily doped, and ohmic contact can be formed between the channel region extraction region and the first contact hole corresponding to the top.

11. The method of manufacturing an LDMOS device of claim 8, wherein: before forming the interlayer film, the method further comprises the step of forming a first injection region in the drift region, wherein the first injection region is lightly doped with a first conductive type, the first injection region is overlapped in the drift region close to one side of the second contact hole, the junction depth of the first injection region is greater than or equal to that of the drift region, the second contact hole is positioned at the top of the first injection region, and in the direction from the second contact hole to the first side surface of the drift region, the overlapped region of the first injection region and the drift region has a concentration gradient structure with the doping concentration gradually reduced.

12. The method of manufacturing an LDMOS device of claim 8, wherein: forming more than one layer of field plate on the top of the drift region, wherein the field plate is connected to the source electrode; the field plate is a metal field plate or a polysilicon field plate.

13. The method of manufacturing an LDMOS device of claim 8, wherein: a field oxide is formed in the drift region proximate to a first side of the drift region, the gate structure also extending over the field oxide.

14. The method of manufacturing an LDMOS device of claim 8, wherein: the semiconductor substrate is a silicon substrate;

the gate dielectric layer is a gate oxide layer and is formed by adopting a thermal oxidation process;

the gate conductive material layer is a polysilicon gate.

15. The method of manufacturing an LDMOS device according to any of claims 8 to 14, wherein: the LDMOS device is an N-type device, the first conductivity type is N-type, the second conductivity type is P-type, the implantation impurity of the first conductivity type heavy doping ion implantation of the drift region leading-out region is phosphorus or arsenic, the implantation energy is 30 keV-100 keV, and the implantation dosage is 1e15cm ^-2 ～2e15cm ^-2 The method comprises the steps of carrying out a first treatment on the surface of the Or the LDMOS device is an N-type device, the first conductivity type is N-type, the second conductivity type is P-type, and the drift region is provided with a lead-out regionThe implantation impurity of the first conductive type heavily doped ion implantation comprises boron, the implantation energy is 30 keV-100 keV, and the implantation dosage is 1e15cm ^-2 ～2e15cm ^-2 。