CN104347724A - LDMOS (Laterally Diffused Metal Oxide Semiconductor) device with shielding ring and preparation method thereof - Google Patents

Abstract

An LDMOS device with a shielding ring and a preparation method thereof. The invention is applicable to the field of integrated circuit manufacturing, and provides an LDMOS device with a shielding ring and a manufacturing method thereof. The device includes: a P+ silicon substrate; a P-type epitaxial region formed epitaxially on the P+ silicon substrate; a channel region; source region; drift region; drain region; gate polysilicon; shielding ring. In the embodiment of the present invention, by adding a shielding ring to the LDMOS device, the breakdown voltage of the radio frequency LDMOS device is changed, and the performance of the radio frequency LDMOS device is optimized.

Description

A kind of LDMOS device with shielding ring and its preparation method

technical field

The invention belongs to the field of integrated circuits, in particular to an LDMOS device with a shielding ring and a preparation method thereof.

Background technique

Lateral Double-diffused MOS (LDMOS) is a radio frequency power device with great market demand and broad development prospects. In the field of radio frequency wireless communication, base stations and long-distance transmitters almost all use silicon-based LDMOS high-power transistors; in addition, LDMOS is also widely used in radio frequency amplifiers, such as HF, VHF and UHF communication systems, pulse radar, industrial, scientific and medical applications , Avionics and WiMAXTM communication systems and other fields. Because LDMOS has the advantages of high gain, high linearity, high withstand voltage, high output power, and easy compatibility with CMOS technology, silicon-based LDMOS transistors have become a new hot spot in radio frequency semiconductor power devices. Compared with SiGe and GaAs processes, although the high-frequency performance and noise performance of SiLDMOS technology are not optimal, its process is the most mature, the cost is the lowest, the power consumption is the smallest, and the application is the most extensive, especially with the device feature size etc. The ratio is reduced, and the frequency and noise characteristics of LDMOS transistors are gradually improved. Therefore, in the long run, silicon-based LDMOS radio frequency circuits will be the trend of future development.

As shown in Figure 1, it is a schematic structural diagram of an existing radio frequency LDMOS device; the basic structure of an existing radio frequency LDMOS device includes:

The P+ silicon substrate 101 is the substrate doped with high-concentration P-type impurities and the P- epitaxial layer 102 formed above the P+ silicon substrate; the resistivity of the P+ silicon substrate 101 is 0.01 ohm·cm-0.02 ohm cm, the thickness and doping concentration of the P-epitaxial layer 102 are set according to the requirements of the withstand voltage of the device. Microns.

A P+ sinker layer (P+SINKER) 103 formed by implantation and diffusion, the P+ sinker layer 103 passes through the P- epitaxial layer 102 and the bottom of the P+ sinker layer 103 enters the P+ silicon substrate 101 in.

P well 104, the P well 104 is used to form the channel region of the device.

The gate oxide layer and the gate polysilicon 108 cover the P well 104 , and the P well 104 of the gate polysilicon 108 forms a channel region.

The drift region 105 is composed of an N-doped region formed in the P- epitaxial layer 102 , and the drift region 105 is adjacent to one side of the gate polysilicon 108 .

The source region 106 , consisting of an N+ doped region, is self-aligned with the other side of the gate polysilicon 108 .

The drain region 107 is composed of an N+ doped region, is separated from the gate polysilicon 108 by a certain distance, and is connected to the P well 104 through the drift region 105 .

The source S, the drain D and the gate G are drawn out through the metal pattern 109 . From the drain region 107 to the drain D includes multiple layers of metal layers and contact holes and through holes for connection between adjacent metal layers, wherein the contact hole is used for the connection between the drain region 107 and the first layer of metal, the through hole Used for connections between metal layers. Between the source region 106 and the source S also includes multi-layer metal layers and contact holes and via holes for connection between adjacent metal layers. The source S can also be the metal 110 on the back of the silicon wafer, and the gate polysilicon Between 108 and the gate G also includes multiple metal layers and contact holes and via holes for connection between adjacent metal layers.

After the P+ silicon substrate 101 is thinned, a back metal 110 is formed on the back, and the back metal 110 is connected to the source S through the P+ silicon substrate 101, the P+ sinker layer 103 or serves as a source pole.

Breakdown voltage is one of the most important static parameters of LDMOS, and good withstand voltage characteristics are an important manifestation of the reliability of LDMOS devices. The LDMOS device is manufactured by planar technology. Since the surface of the P-N junction is affected by the radius of curvature, the positive charge in the oxide layer, and the Si/SiO2 interface state, the electric field at the surface of the P-N junction increases, and the breakdown of the P-N junction occurs first on the surface. In order to improve the breakdown The technology of reducing the surface electric field taken at the edge of the P-N junction due to the crossing voltage is called junction termination technology. The invention provides a method for improving the breakdown voltage of radio frequency LDMOS by changing the implant dose in the drift region. The method can optimize the main parameters such as the threshold voltage, breakdown voltage and frequency characteristics of the device, so as to design a device with excellent performance. RF LDMOS device required by the specification.

Contents of the invention

The purpose of the embodiments of the present invention is to provide an LDMOS device with a shielding ring and a manufacturing method thereof, so as to solve the problem in the prior art that the breakdown voltage of a radio frequency device cannot be optimized.

The embodiment of the present invention is achieved in this way, an LDMOS device with a shielding ring, the device includes:

P+ silicon substrate;

A P-type epitaxial region formed epitaxially on the P+ silicon substrate;

a channel region consisting of a P well formed in the P-type epitaxial region;

a source region consisting of an N+ doped region formed in the P well;

a drift region consisting of an N-doped region formed in the P-type epitaxial region, the drift region adjacent to the channel region;

a drain region consisting of an N+ doped region formed in the drift region, the drain region being separated from the channel region by a lateral distance;

a gate polysilicon composed of polysilicon formed over the channel region, a gate oxide layer isolating the gate polysilicon from the channel region, one side of the gate polysilicon and the source region Self-alignment, the other side edge of the gate polysilicon is greater than or equal to the connecting edge of the channel region and the drift region;

Shielding ring made of tungsten silicon.

Another object of the embodiments of the present invention is to provide a method for manufacturing an LDMOS device with a shielding ring, the method comprising:

Prepare P+ silicon substrate;

forming a P-type epitaxial region by epitaxy on the P+ silicon substrate;

forming a channel region through a P well formed in the P-type epitaxial region;

forming a source region through an N+ doped region formed in the P well;

A drift region is formed by an N-doped region formed in the P-type epitaxial region, and the drift region is adjacent to the channel region;

A drain region is formed by an N+ doped region formed in the drift region, and the drain region is separated from the channel region by a lateral distance;

Gate polysilicon is composed of polysilicon formed above the channel region, a gate oxide layer is isolated between the gate polysilicon and the channel region, and one side of the gate polysilicon and the source region are formed from Alignment, the other side edge of the gate polysilicon is greater than or equal to the connecting edge of the channel region and the drift region;

Via a shielding ring made of tungsten silicon.

In the embodiment of the present invention, by adding a shielding ring to the LDMOS device, the breakdown voltage of the LDMOS device is changed, and the performance of the radio frequency LDMOS device is optimized.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the accompanying drawings that need to be used in the descriptions of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only of the present invention. For some embodiments, those of ordinary skill in the art can also obtain other drawings based on these drawings without paying creative efforts.

Fig. 1 is the structural diagram of the radio frequency LDMOS device that prior art provides;

Fig. 2 is the LDMOS device structure schematic diagram that obtains through ISE TCAD process simulation that the embodiment of the present invention provides;

FIG. 3 is a structural diagram of an LDMOS device with a shielding ring provided by an embodiment of the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

In order to illustrate the technical solutions of the present invention, specific examples are used below to illustrate.

Embodiment one

As shown in Figure 2, it is the schematic diagram of the structure of the LDMOS device obtained through the simulation of the ISE TCAD process provided by the embodiment of the present invention. section, including:

A P+ silicon substrate with a resistivity of 0.05-0.15Ω/cm ³ .

In an embodiment of the present invention, a radio frequency LDMOS (Lateral Double-diffused MOS, referred to as: lateral double-diffused field effect transistor) device is fabricated on a P+ silicon substrate, and the radio frequency LDMOS device first includes: a resistivity of 0.05 to 0.15Ω /cm ³ of P+ silicon substrate.

A P-type epitaxial region with a thickness of 9 μm and a doping concentration of 6*10 ¹⁴ cm ⁻³ to 8*10 ¹⁴ cm ⁻³ is epitaxially formed on the P+ silicon substrate.

In the embodiment of the present invention, there is a P-type epitaxial region formed by epitaxy on the P+ silicon substrate with a thickness of 9 μm and a doping concentration of 6*10 ¹⁴ cm ⁻³ to 8*10 ¹⁴ cm ⁻³ .

The B impurity implantation dose of the P well formed in the P-type epitaxial region is 2*10 ¹³ cm ^-2 ~ 4*10 ¹³ cm ^-2 , the energy is 40 ~ 60Kev, and the high temperature advance time of 1000 ~ 1100°C is 40-60min channel area.

In the embodiment of the present invention, the radio frequency LDMOS device further includes B impurity implantation dose of 2*10 ¹³ cm ^-2 to 4*10 ¹³ cm ^-2 , energy of 40-60Kev, and high temperature advance time of 1000-1100°C of 40- 60min channel zone.

A source region with a field oxygen thickness of 1.8-2.2 μm composed of an N+ doped region formed in the P well.

In an embodiment of the present invention, the radio frequency LDMOS device further includes a source region with a field oxygen thickness of 1.8-2.2 μm.

The dose of As impurity implanted in the N-doped region formed in the P-type epitaxial region is 1.1*10 ¹² cm ^-2 to 1.5*10 ¹² cm ^-2 , the energy is 140-160Kev, and the high temperature is 1000-1100°C A drift region with an advancing time of 40-70 minutes and a length of 2 μm-4 μm, the drift region is adjacent to the channel region.

In the embodiment of the present invention, the radio frequency LDMOS device further includes an As impurity implantation dose of 1.1*10 ¹² cm ^-2 to 1.5*10 ¹² cm ^-2 , an energy of 140 to 160Kev, and a high temperature advance time of 40 to 1000 to 1100°C. 70 min, a drift region with a length of 2 μm to 4 μm, wherein the drift region is adjacent to the above-mentioned channel region.

The AS impurity implantation dose composed of the N+ doped region formed in the drift region is 4*10 ¹⁵ cm ^-2 ~ 6*10 ¹⁵ cm ^-2 , the energy is 80 ~ 120Kev, 900 ~ 1000 ℃ rapid heat treatment for 30min a drain region, and the drain region is separated from the channel region by a lateral distance.

In the embodiment of the present invention, the radio frequency LDMOS device further includes a drain region with an AS impurity implantation dose of 4*10 ¹⁵ cm ^-2 to 6*10 ¹⁵ cm ^-2 , an energy of 80-120Kev, and a rapid heat treatment at 900-1000°C for 30 minutes. , wherein the drain region is separated from the above-mentioned channel region by a lateral distance.

The thickness of the gate oxide composed of polysilicon formed over the channel region is The polysilicon thickness is gate polysilicon, a gate oxide layer is isolated between the gate polysilicon and the channel region, one side of the gate polysilicon is self-aligned with the source region, and the other side of the gate polysilicon The side edge is greater than or equal to the adjoining edge of the channel region and the drift region.

In an embodiment of the present invention, the radio frequency LDMOS device further includes a gate oxide thickness of The polysilicon thickness is The gate polysilicon is isolated from the above-mentioned channel region by a gate oxide layer, one side of the gate polysilicon is aligned with the above-mentioned source region, and the edge of the other side of the gate polysilicon is greater than or equal to The adjoining edges of the channel region and the drift region.

A shielding ring made of tungsten silicon with a length of 0.7-0.8 μm.

In an embodiment of the present invention, the radio frequency LDMOS device further includes a shielding ring made of tungsten silicon with a length of 0.7-0.8 μm. In some preferred embodiments, the length of the shielding ring is 0.75 μm.

Through simulation processing, the breakdown voltage of the radio frequency LDMOS device provided by the invention is changed, so that the breakdown voltage of the radio frequency LDMOS device is optimized.

As a preferred embodiment of the present invention, the LDMOS device with a shielding ring includes:

P+ silicon substrate with a resistivity of 0.08Ω/cm ³ ;

A P-type epitaxial region with a thickness of 9 μm and a doping concentration of 7*10 ¹⁴ cm ⁻³ epitaxially formed on the P+ silicon substrate;

A channel region with a B impurity implantation dose of 3*10 ¹³ cm ^-2 , an energy of 50Kev, and a high temperature advance time of 1050°C for 40 to 60 minutes consisting of a P well formed in the P-type epitaxial region;

A source region with a field oxygen thickness of 2 μm consisting of an N+ doped region formed in the P well;

A drift region consisting of an N-doped region formed in the P-type epitaxial region with an As impurity implantation dose of 1.2*10 ¹² cm ^-2 , an energy of 150Kev, and a high temperature advance time of 60 minutes at 1050°C, the drift region adjacent to the channel region;

The drain region is composed of the N+ doped region formed in the drift region, the AS impurity implantation dose is 5*10 ¹⁵ cm ^-2 , the energy is 100Kev, and the drain region is rapidly heat-treated at 950°C for 30 minutes, the drain region and the channel zones are separated by a lateral distance;

The thickness of the gate oxide composed of polysilicon formed over the channel region is The polysilicon thickness is The gate polysilicon;

A shielding ring made of tungsten silicon with a length of 0.7 μm.

By implementing this embodiment, the breakdown voltage of the radio frequency LDMOS device can be 100V.

As another preferred embodiment of the present invention, the LDMOS device with a shielding ring includes:

P+ silicon substrate with a resistivity of 0.07Ω/cm ³ ;

A P-type epitaxial region with a thickness of 9 μm and a doping concentration of 8*10 ¹⁴ cm ⁻³ epitaxially formed on the P+ silicon substrate;

A channel region with a B impurity implantation dose of 4*10 ¹³ cm ^-2 , an energy of 40Kev, and a high-temperature advance time of 40 minutes at 1050°C consisting of a P well formed in the P-type epitaxial region;

A source region with a field oxygen thickness of 2.2 μm consisting of an N+ doped region formed in the P well;

A drift region consisting of an N-doped region formed in the P-type epitaxial region with an As impurity implantation dose of 1.3*10 ¹² cm ^-2 , an energy of 160Kev, and a high temperature advance time of 1100°C for 50 minutes, the drift region adjacent to the channel region;

The drain region is composed of the N+ doped region formed in the drift region, the AS impurity implantation dose is 6*10 ¹⁵ cm ^-2 , the energy is 120Kev, and the drain region is rapidly heat-treated at 1000°C for 30 minutes, the drain region and the channel zones are separated by a lateral distance;

The thickness of the gate oxide composed of polysilicon formed over the channel region is The polysilicon thickness is The gate polysilicon;

A shielding ring made of tungsten silicon with a length of 0.75 μm.

By implementing this embodiment, the breakdown voltage of the radio frequency LDMOS device can be 110V.

As another preferred embodiment of the present invention, the LDMOS device with a shielding ring includes:

P+ silicon substrate with a resistivity of 0.05Ω/cm ³ ;

A P-type epitaxial region with a thickness of 9 μm and a doping concentration of 6*10 ¹⁴ cm ^-3 epitaxially formed on the P+ silicon substrate;

A channel region with a B impurity implantation dose of 2*10 ¹³ cm ^-2 , an energy of 60Kev, and a high-temperature advance time of 60 minutes at 1000°C consisting of a P well formed in the P-type epitaxial region;

A source region with a field oxygen thickness of 1.8 μm consisting of an N+ doped region formed in the P well;

A drift region consisting of an N-doped region formed in the P-type epitaxial region with an As impurity implantation dose of 1.2*10 ¹² cm ^-2 , an energy of 150Kev, and a high temperature advance time of 50 minutes at 1000°C, the drift region adjacent to the channel region;

The drain region is composed of the N+ doped region formed in the drift region, the AS impurity implantation dose is 4*10 ¹⁵ cm ^-2 , the energy is 80Kev, and the drain region is rapidly heat-treated at 900°C for 30 minutes, the drain region and the channel zones are separated by a lateral distance;

The thickness of the gate oxide composed of polysilicon formed over the channel region is The polysilicon thickness is The gate polysilicon;

A shielding ring made of tungsten silicon with a length of 0.8 μm.

By implementing this embodiment, the breakdown voltage of the radio frequency LDMOS device can be 105V.

Embodiment two

A flowchart of a method for preparing a light-shielding device provided in an embodiment of the present invention, the method includes the following steps:

Prepare a P+ silicon substrate with a resistivity of 0.05-0.15Ω/ ^cm3 ;

Forming a P-type epitaxial region with a thickness of 9 μm and a doping concentration of 6*10 ¹⁴ cm ⁻³ to 8*10 ¹⁴ cm ⁻³ through epitaxy on the P+ silicon substrate;

The B impurity implantation dose is 2*10 ¹³ cm ^-2 to 4*10 ¹³ cm ^-2 through the P well formed in the P-type epitaxial region, the energy is 40-60Kev, and the high-temperature advance time of 1000-1100°C is 40 ~60min channel area;

forming a source region with a field oxygen thickness of 1.8-2.2 μm through the N+ doped region formed in the P well;

The As impurity implantation dose is 1.1*10 ¹² cm ^-2 to 1.5*10 ¹² cm ^-2 through the N-doped region formed in the P-type epitaxial region, the energy is 140-160Kev, and the high temperature is 1000-1100°C a drift region with a time of 40 to 70 minutes and a length of 2 μm to 4 μm, the drift region is adjacent to the channel region;

The N+ doped region formed in the drift region constitutes a drain with an AS impurity implantation dose of 4*10 ¹⁵ cm ^-2 to 6*10 ¹⁵ cm ^-2 , an energy of 80 to 120Kev, and rapid heat treatment at 900 to 1000°C for 30 minutes. region, the drain region is separated from the channel region by a lateral distance;

The gate oxide thickness formed by the polysilicon formed above the channel region is The polysilicon thickness is gate polysilicon, a gate oxide layer is isolated between the gate polysilicon and the channel region, one side of the gate polysilicon is self-aligned with the source region, and the other side of the gate polysilicon The side edge is greater than or equal to the adjoining edge of the channel region and the drift region;

A shielding ring with a length of 0.7-0.8 μm is formed by tungsten silicon.

By implementing this embodiment, the breakdown voltage of the radio frequency LDMOS device can be optimized.

Those of ordinary skill in the art can also understand that all or part of the steps in the method of the above embodiments can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium, so The storage medium mentioned above includes ROM/RAM, magnetic disk, optical disk, etc.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention should be included in the protection of the present invention. within range.

Claims (8)

1. A kind of LDMOS device with shielding ring, is characterized in that, described device comprises: P+ silicon substrate; A P-type epitaxial region formed epitaxially on the P+ silicon substrate; a channel region consisting of a P well formed in the P-type epitaxial region; a source region consisting of an N+ doped region formed in the P well; a drift region consisting of an N-doped region formed in the P-type epitaxial region, the drift region adjacent to the channel region; a drain region consisting of an N+ doped region formed in the drift region, the drain region being separated from the channel region by a lateral distance; a gate polysilicon composed of polysilicon formed over the channel region, a gate oxide layer isolating the gate polysilicon from the channel region, one side of the gate polysilicon and the source region Self-alignment, the other side edge of the gate polysilicon is greater than or equal to the connecting edge of the channel region and the drift region; Shielding ring made of tungsten silicon. 2. The LDMOS device of claim 1, wherein the device comprises: P+ silicon substrate with a resistivity of 0.05-0.15Ω/ ^cm3 ; A P-type epitaxial region with a thickness of 9 μm and a doping concentration of 6*10 ¹⁴ cm ⁻³ to 8*10 ¹⁴ cm ⁻³ epitaxially formed on the P+ silicon substrate; The B impurity implantation dose of the P well formed in the P-type epitaxial region is 2*10 ¹³ cm ^-2 ~ 4*10 ¹³ cm ^-2 , the energy is 40 ~ 60Kev, and the high temperature advance time of 1000 ~ 1100°C is 40-60min channel area; A source region with a field oxygen thickness of 1.8-2.2 μm consisting of an N+ doped region formed in the P well; The dose of As impurity implanted in the N-doped region formed in the P-type epitaxial region is 1.1*10 ¹² cm ^-2 to 1.5*10 ¹² cm ^-2 , the energy is 140-160Kev, and the high temperature is 1000-1100°C a drift region with an advancing time of 40 to 70 minutes and a length of 2 μm to 4 μm, the drift region is adjacent to the channel region; The AS impurity implantation dose composed of the N+ doped region formed in the drift region is 4*10 ¹⁵ cm ^-2 ~ 6*10 ¹⁵ cm ^-2 , the energy is 80 ~ 120Kev, 900 ~ 1000 ℃ rapid heat treatment for 30min a drain region separated from the channel region by a lateral distance; The thickness of the gate oxide composed of polysilicon formed over the channel region is The polysilicon thickness is gate polysilicon, a gate oxide layer is isolated between the gate polysilicon and the channel region, one side of the gate polysilicon is self-aligned with the source region, and the other side of the gate polysilicon The side edge is greater than or equal to the adjoining edge of the channel region and the drift region; A shielding ring made of tungsten silicon with a length of 0.7-0.8 μm. 3. The LDMOS device according to any one of claims 1-2, characterized in that the length of the shielding ring is 0.75 μm. 4. The LDMOS device according to any one of claims 1-2, characterized in that, the breakdown voltage of the LDMOS device is 110v. 5. A method for preparing an LDMOS device with a shielding ring, characterized in that the method comprises: Prepare P+ silicon substrate; forming a P-type epitaxial region by epitaxy on the P+ silicon substrate; forming a channel region through a P well formed in the P-type epitaxial region; forming a source region through an N+ doped region formed in the P well; A drift region is formed by an N-doped region formed in the P-type epitaxial region, and the drift region is adjacent to the channel region; A drain region is formed by an N+ doped region formed in the drift region, and the drain region is separated from the channel region by a lateral distance; Gate polysilicon is composed of polysilicon formed above the channel region, a gate oxide layer is isolated between the gate polysilicon and the channel region, and one side of the gate polysilicon and the source region are formed from Alignment, the other side edge of the gate polysilicon is greater than or equal to the connecting edge of the channel region and the drift region; Via a shielding ring made of tungsten silicon. 6. preparation method as claimed in claim 5, is characterized in that, described method comprises: Prepare a P+ silicon substrate with a resistivity of 0.05-0.15Ω/ ^cm3 ; Forming a P-type epitaxial region with a thickness of 9 μm and a doping concentration of 6*10 ¹⁴ cm ⁻³ to 8*10 ¹⁴ cm ⁻³ through epitaxy on the P+ silicon substrate; The B impurity implantation dose is 2*10 ¹³ cm ^-2 to 4*10 ¹³ cm ^-2 through the P well formed in the P-type epitaxial region, the energy is 40-60Kev, and the high-temperature advance time of 1000-1100°C is 40 ~60min channel area; forming a source region with a field oxygen thickness of 1.8-2.2 μm through the N+ doped region formed in the P well; The As impurity implantation dose is 1.1*10 ¹² cm ^-2 to 1.5*10 ¹² cm ^-2 through the N-doped region formed in the P-type epitaxial region, the energy is 140-160Kev, and the high temperature is 1000-1100°C a drift region with a time of 40 to 70 minutes and a length of 2 μm to 4 μm, the drift region is adjacent to the channel region; The N+ doped region formed in the drift region constitutes a drain with an AS impurity implantation dose of 4*10 ¹⁵ cm ^-2 to 6*10 ¹⁵ cm ^-2 , an energy of 80 to 120Kev, and rapid heat treatment at 900 to 1000°C for 30 minutes. region, the drain region is separated from the channel region by a lateral distance; The gate oxide thickness formed by the polysilicon formed above the channel region is The polysilicon thickness is gate polysilicon, a gate oxide layer is isolated between the gate polysilicon and the channel region, one side of the gate polysilicon is self-aligned with the source region, and the other side of the gate polysilicon The side edge is greater than or equal to the adjoining edge of the channel region and the drift region; A shielding ring with a length of 0.7-0.8 μm is formed by tungsten silicon. 7. The preparation method according to any one of claims 5-6, characterized in that the length of the shielding ring is 0.75 μm. 8. The preparation method according to any one of claims 5-6, characterized in that, the breakdown voltage of the LDMOS device is 110v.