CN112713149A

CN112713149A - Semiconductor device and forming method

Info

Publication number: CN112713149A
Application number: CN201911026033.2A
Authority: CN
Inventors: 范瑾瑜; 曾红林; 施平; 蔺黎; 冯高明
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2019-10-25
Filing date: 2019-10-25
Publication date: 2021-04-27
Anticipated expiration: 2039-10-25
Also published as: CN112713149B

Abstract

Embodiments of the present invention provide a semiconductor device and a method for forming the same. In the embodiment of the present invention, a bird's beak-shaped oxide layer is formed on the sidewall of the floating gate material layer. Therefore, after removing the barrier layer and the oxide layer at the same time, a sharpened floating gate cantilever angle is formed. Avoid situations where the floating gate cantilever corners are passivated. Concentrating the electric field at the cantilever corner of the floating gate is beneficial for electrons in the floating gate to tunnel into the erasing gate through the cantilever corner of the floating gate, thereby improving erasing efficiency. Thereby, the performance of the semiconductor device can be improved.

Description

Semiconductor device and forming method

Technical Field

The present invention relates to the field of semiconductor technology, and more particularly, to a semiconductor device and a method for forming the same.

Background

With the continuous development of semiconductor manufacturing processes, the integration level of semiconductor devices is higher and higher, and the feature size of semiconductor devices is also gradually reduced. However, the performance of semiconductor devices is also in need of improvement.

Disclosure of Invention

Embodiments of the present invention provide a semiconductor device and a method for forming the same, so as to improve the performance of the semiconductor device.

In a first aspect, an embodiment of the present invention provides a method for forming a semiconductor device, where the method includes:

providing a front-end device layer, wherein a floating gate material layer and a plurality of separated control gate stacking structures covering the floating gate material layer are formed in the front-end device layer;

removing the floating gate material layer of a first region, wherein the first region is positioned at a first side of the control gate stack structure;

thinning a floating gate material layer of a second region, wherein the second region is positioned at the second side of the control gate stack structure;

forming a barrier layer at least covering the floating gate material layer and the side wall of the control gate stacking structure;

etching the floating gate material layer by taking the control gate stack structure and the barrier layer on the side wall of the control gate stack structure as masks to expose the side wall of the floating gate material layer on the second side;

oxidizing the side wall of the floating gate material layer on the second side to form an oxide layer; and

and removing the oxide layer and the barrier layer to form the floating gate, so that the cantilever angle of the floating gate is sharpened.

Further, the floating gate cantilever angle is on top of the second side of the floating gate.

Further, after the forming the floating gate, the method further comprises:

forming an erasing gate structure in the second area;

and forming word lines in the first region.

Further, the oxidizing the sidewall of the floating gate material layer specifically includes:

and converting the floating gate material layer in the preset area into an oxide layer by adopting a thermal oxidation process.

Further, the predetermined region is a region extending from the sidewall of the floating gate material layer on the second side in the lateral and longitudinal directions by a predetermined dimension.

Further, the thinning of the floating gate material layer of the second region specifically includes:

and thinning the floating gate material layer on the second side of the control gate stack structure by 20-50 angstroms by adopting a self-aligned etching process.

Further, the material of the barrier layer is silicon oxide or silicon nitride, and the thickness of the barrier layer is 20-50 angstroms.

Further, the removing the oxide layer and the barrier layer specifically includes:

and etching the oxide layer and the barrier layer by adopting an isotropic etching process.

In a second aspect, an embodiment of the present invention provides a semiconductor device, including:

a front end device layer;

a floating gate having a sharpened cantilever angle at one side; and

and the control gate stack structure is formed on the floating gate.

Further, the semiconductor device further includes:

an erase gate on a side of the floating gate having a sharpened cantilever angle;

word lines on a side of the floating gate without sharpened cantilever corners.

In the embodiment of the invention, the bird's beak-shaped oxide layer is formed on the side wall of the floating gate material layer, so that after the barrier layer and the oxide layer are removed simultaneously, a sharpened floating gate cantilever angle is formed. The situation of floating gate cantilever angle passivation is avoided. The electric field at the corner of the floating gate cantilever is concentrated, so that electrons in the floating gate can penetrate into the erasing gate through the corner tunnel of the floating gate cantilever, and the erasing efficiency is improved. Thereby enabling to improve the performance of the semiconductor device.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

FIG. 1 is a schematic diagram of the basic structure of a split gate flash memory;

FIGS. 2-4 are schematic cross-sectional views of structures formed at various steps of a method of forming a semiconductor device of a comparative example;

fig. 5 is a flow chart of a method of forming a semiconductor device of an embodiment of the present invention;

fig. 6-13 are schematic cross-sectional views of structures formed at various steps of a method of forming a semiconductor device according to an embodiment of the present invention;

fig. 14 is a schematic sectional view of the structure of a semiconductor device of an embodiment of the present invention.

Detailed Description

The present invention will be described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. Well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.

Further, those of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.

Unless the context clearly requires otherwise, throughout the description, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, what is meant is "including, but not limited to".

In the description herein, it is to be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In addition, in the description of the present invention, "a plurality" means two or more unless otherwise specified.

In the description herein, it is to be understood that the term "layer" is used in its broadest sense to include a film, a cap layer, or the like, and a layer may include a plurality of sub-layers.

In the description herein, it is to be understood that reference throughout the specification to conventional etching techniques known in the semiconductor manufacturing art for selectively removing polysilicon, silicon nitride, silicon dioxide, metals, photoresists, polyimides, or similar materials includes, for example, wet Chemical etching, plasma etching (RIE), washing, wet cleaning, precleaning, spray cleaning, Chemical Mechanical Polishing (CMP), and the like. Specific embodiments are described herein with reference to examples of such processes. However, the present disclosure and reference to particular deposition techniques should not be limited to that described. In some examples, two such techniques may be interchanged. For example, stripping the photoresist may include soaking the sample in a wet chemical bath or alternatively spraying a wet chemical directly onto the sample.

Semiconductor devices are electronic devices that have electrical conductivity between a good electrical conductor and an insulator, and that use the special electrical properties of semiconductor materials to perform specific functions, and can be used to generate, control, receive, convert, amplify signals, and perform energy conversion. A commonly used semiconductor device includes a flash memory.

Flash Memory (FM) is a form of electrically erasable programmable read only Memory that allows Memory to be erased or written to multiple times during operation. Flash memories are widely used in Systems On Chip (SOC) as electrically programmable and erasable nonvolatile memory devices. Structurally, a flash memory device may be largely classified into a stacked gate structure and a split gate structure. The conventional stacked gate flash memory has the reliability problems of program/erase disturbance, over-erase, charge retention characteristics, erase endurance, and the like. The split gate flash memory can effectively avoid the reliability problem of the stacked gate flash memory by applying a two-tube unit structure.

Fig. 1 is a schematic diagram of a basic structure of a split gate flash memory. As shown in fig. 1, the split gate flash memory includes a front-end device layer 1. The floating gate oxide layer 101, the floating gate 102, the gate dielectric layer 103, the control gate 104, the control gate oxide layer 105 and the control gate silicon nitride 106 are sequentially formed on the front-end device layer by a stack self-alignment process. And further comprises a sidewall layer 107 formed on both sides of the control gate 104 and a sidewall oxide layer 108 formed on the surface of the sidewall layer 107 and on both sides of the floating gate 102. In which an active region 111 and a drain region (not shown in the figure) are formed in the front-end device layer 1 on both sides of the floating gate 102. An erase gate 110 is formed on the source region 111. A word line 109 is formed on the drain region.

The working principle of the split gate flash memory is as follows: when data writing operation is carried out on the flash memory, a high positive bias is applied to the control grid, so that hot electrons pass through the tunneling oxide layer from the source electrode and are injected into the floating grid. When erasing data from the flash memory, a high negative bias is applied to the control gate, so that hot electrons injected into the floating gate flow into the source through the sidewall oxide layer by means of Fowler-Nordheim (FN) tunneling. The erase time is longer than the program time, subject to fowler nordheim tunneling. Therefore, new methods are needed to improve flash erase efficiency.

Fig. 2 to 4 are schematic views of structures formed at respective steps of a method of forming a semiconductor device of a comparative example.

Referring to fig. 2, an oxide layer 2 is formed on the control gate sidewall layer 108 on the side near the erase gate. And etching the floating gate by using the control gate, the side wall layer and the oxide layer as masks.

Referring to fig. 3, the oxide layer 2 is removed, forming an oxide layer 3 covering the sidewall layer 108 and the floating gate 102.

The comparative example is to form an oxide layer on the sidewall layer adjacent to the erase gate, and then etch the floating gate with the control gate and sidewall layer and oxide layer as masks. The formed floating gate cantilever is longer, and an electric field at the corner of the floating gate cantilever is concentrated during the erasing operation, so that electrons in the floating gate can be conveniently tunneled into an erasing gate through the floating gate cantilever corner 4, and higher erasing efficiency is obtained.

However, during the removal of the oxide layer 2, a passivation of the floating gate cantilever corners 4 may result, as shown in fig. 4. Passivation directly affects erase efficiency, resulting in lower yields of semiconductor devices.

In view of this, the performance of the semiconductor device is improved. The embodiment of the invention provides a method for forming a semiconductor device. In the embodiments of the present invention, a flash memory is formed as an example, and further, the method of the embodiments of the present invention is used for forming a flash memory with a split gate structure. Furthermore, the method of the embodiment of the present invention may also be used to form other semiconductor devices such as a NAND Flash Memory (NAND Flash Memory) and a Static Random Access Memory (SRAM).

Fig. 5 is a flow chart of a method of forming a semiconductor device of an embodiment of the present invention. As shown in fig. 5, the method for forming a semiconductor device according to the embodiment of the present invention includes the steps of:

and step S100, providing a front-end device layer. A floating gate material layer and a plurality of discrete control gate stack structures overlying the floating gate material layer are formed in the front-end device layer.

Step S200, removing the floating gate material layer of a first region, wherein the first region is located at a first side of the control gate stack structure.

And S300, thinning the floating gate material layer of a second region, wherein the second region is positioned at the second side of the control gate stack structure.

And S400, forming a barrier layer at least covering the floating gate material layer and the side wall of the control gate stack structure.

And S500, etching the floating gate material layer by taking the control gate stack structure and the barrier layer on the side wall of the control gate stack structure as masks. So as to expose the sidewall of the floating gate material layer on the second side.

And S600, oxidizing the side wall of the floating gate material layer. To form an oxide layer.

And S700, removing the oxide layer and the barrier layer. To form the floating gate, making the floating gate cantilever angle sharp.

In an optional implementation, the method further includes:

and step S800, forming a floating gate oxide layer wrapping the floating gate.

And S900, forming an erasing gate structure in the second area.

Step S1000, forming a word line in the first area.

Fig. 6 to 13 are schematic views of structures formed at respective steps of a method of forming a semiconductor device according to an embodiment of the present invention.

Referring to fig. 6, in step S100, a front-end device layer is provided. In which a floating gate material layer 11 and a plurality of separate control gate stack structures 12 covering the floating gate material layer 11 are formed.

Specifically, the front-end device layer provided in step S100 may be a semiconductor substrate, or may be an intermediate structure of a semiconductor device. The intermediate structure of the semiconductor device may include a semiconductor substrate, an active device, a passive device, and the like. Further, the active devices and passive devices in the front-end device layer may be capacitors, inductors, resistors, various transistors, and the like. In this embodiment, the front-end device layer comprises a substrate 10, a floating gate material layer 11 and a plurality of discrete control gate stack structures 12 covering the floating gate material layer 11.

Wherein the semiconductor substrate may be a silicon single crystal substrate, a germanium single crystal substrate, or a silicon germanium single crystal substrate. Alternatively, the semiconductor substrate may also be a silicon-on-insulator (SOI) substrate, a silicon-on-insulator (SSOI), a silicon-on-insulator-stacked-germanium (S-SiGeOI), a silicon-on-insulator-germanium (SiGeOI), a germanium-on-insulator (GeOI), a substrate of an epitaxial layer structure on silicon, a compound substrate, or an alloy substrate. The compound substrate comprises silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, or indium dysprosium, the alloy substrate comprises SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof, and the SOI substrate comprises a semiconductor layer (e.g., a silicon layer, a silicon germanium layer, a carbon silicon layer, or a germanium layer) disposed on a layer of insulating material. The floating gate material layer 11 is made of polysilicon, and the floating gate material layer 11 is used for forming a floating gate in a subsequent process.

The control gate stack structure 12 includes a gate dielectric layer 21, a control gate 22, a control gate oxide layer 23 and a control gate silicon nitride 24 stacked in sequence. And also includes sidewall layers 25 formed on both sides of the control gate 22.

The material of the sidewall and the top of the control gate stack structure 12 is silicon oxide or silicon nitride, which is different from the material of the floating gate material layer, and the control gate stack structure can be used as a mask for etching the floating gate material layer in the subsequent process.

Referring to fig. 7, in step S200, the floating gate material layer 11 of the first region a is removed, and the first region a is located at the first side of the control gate stack structure 12.

Specifically, the floating gate material layer 11 in the first region a is removed by a photolithography process. And forming a photoresist pattern exposing the first region A on the floating gate material layer by adopting a mask used in the ion implantation process in the previous front-end device layer, removing the floating gate material layer 11 in the first region by adopting a dry etching or wet etching process, and then removing the photoresist.

In an alternative implementation, the floating gate material layer 11 is etched by using a plasma etching process. The dry etching process has the following process parameters: HBr flow rate of 50sccm-500sccm, NF₃The flow rate is 0sccm-50sccm, O₂The flow rate is 0sccm-50sccm, the He flow rate is 0sccm-200sccm, the Ar flow rate is 0sccm-500sccm, the chamber pressure is 2mTorr-100mTorr, the source power is 200W-1000W, and the bias power is 0W-200W.

Referring to fig. 8, in step S300, the floating gate material layer 11 of the second region B is thinned, and the second region B is located at the second side of the control gate stack structure 12.

And thinning the floating gate material layer in the second region by 20-50 angstroms by adopting a self-aligned etching process.

The self-aligned etching tool specifically uses the difference between the material of the control gate stack structure 12 and the material of the floating gate material layer 11, and selects an etching process with a high etching selection ratio to etch the floating gate material layer 11, so that a mask is not needed, and the cost can be saved.

In an alternative implementation, the second region B of the floating gate material layer 11 is etched by using a plasma etching process until the floating gate material layer 11 in the second region B is thinned by 30 angstroms.

In this step, the floating gate material layer 11 in the second region B is thinned, and in order to expose the upper end of the sidewall of the floating gate material layer on the second region B side in the subsequent process, the upper end of the sidewall of the floating gate material layer on the second region B side is covered with the barrier layer, so that in the subsequent oxidation process, a bird's beak-shaped oxide layer is formed in the upper end region of the sidewall of the floating gate material layer on the second region B side.

Referring to fig. 9, in step S400, a blocking layer 20 is formed to cover at least the sidewalls of the floating gate material layer 11 and the control gate stack structure 12.

Specifically, the barrier layer 20 may cover the entire intermediate structure formed in step S300.

The material of the barrier layer 20 may be silicon nitride or silicon oxide. The thickness of the barrier layer is 20-50 angstroms. The barrier layer 20 is used as a mask for etching the floating gate material layer 11 in a subsequent process.

In this embodiment, the material of the barrier layer 20 is silicon oxide, and the thickness of the barrier layer 20 is 30 angstroms.

Specifically, the barrier layer 20 may be formed by a Chemical Vapor Deposition (CVD) method, such as Low Temperature Chemical Vapor Deposition (LTCVD), Plasma Chemical Vapor Deposition (PCVD), Low Pressure Chemical Vapor Deposition (LPCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), and Fluid Chemical Vapor Deposition (FCVD).

Referring to fig. 10, in step S500, the floating gate material layer 11 is etched using the control gate stack structure 12 and the barrier layer 20 on the sidewall of the control gate stack structure 12 as a mask. To expose the sidewalls of the floating gate material layer 11 at the second side.

Specifically, the barrier layer 20 is etched by using an anisotropic etching process, and since the etching rate of the anisotropic etching in the vertical direction is greater than that in the horizontal direction, the barrier layer 20 on the sidewall of the control gate stack structure 12 is not completely etched after the barrier layer 20 on the floating gate material layer 11 is etched. Therefore, in this step, a self-aligned etching process is adopted, and the floating gate material layer 11 is etched by using the control gate stack structure 12 and the barrier layer 20 on the sidewall of the control gate stack structure 12 as masks without using a mask.

In this step, the sidewall of the floating gate material layer 11 on the second side is exposed for performing oxidation treatment on the sidewall of the second side in a subsequent process.

Referring to fig. 11, in step S600, sidewalls of the floating gate material layer 11 are oxidized to form an oxide layer 30.

The oxidation of the sidewall of the floating gate material layer 11 specifically includes: a thermal oxidation process is used to convert the floating gate material layer 11 in a predetermined region into an oxide layer 30.

The thermal oxidation process is to place the silicon wafer in an atmosphere of a gas containing an oxidant, and the oxidant molecules reach the surface of the silicon through a Boundary Layer (BL) and react with silicon atoms to form silicon oxide (SiO)₂). The formed silicon oxide layer prevents the oxidizing agent from directly contacting the silicon surface after the silicon oxide has grown from the original pure silicon surface. The oxidant reaches the silicon oxide/silicon interface through the silicon oxide layer in a diffusion mode to react with silicon atoms to generate a new silicon oxide layer, so that the silicon oxide layer is thickened continuously.

In an alternative implementation, the oxidizing gas (oxidant) used in the thermal oxidation process is oxygen (O)₂) And the flow rate of the oxygen is 1.5slm to 2.5 slm. The oxidation temperature is 800-810 ℃. The oxidation time is 800 s-1000 s.

The predetermined region is a region extending from the sidewall of the floating gate material layer 11 at the second side in the lateral and longitudinal directions by a predetermined dimension.

An oxide layer 30 is formed on the sidewall area of the second side of the floating gate not covered by the barrier layer 20 by a thermal oxidation process. Oxygen atoms diffuse in all directions after entering the polysilicon, and the oxygen atoms diffuse in the longitudinal direction while diffusing in the transverse direction during the process of growing the oxide layer 30 on the side wall, which means that slight oxidation growth also exists under the barrier layer 20, and the bird's beak effect is also called local oxidation.

In this step, the sidewall of the floating gate material layer 11 on the second side is oxidized to form the bird's beak-shaped oxide layer 30, so that in the subsequent process, the oxide layer is removed by using the selective etching process to form the sharpened floating gate cantilever angle by using the difference of the etching rates of the oxide layer 30 and the floating gate material layer 11.

Referring to fig. 12, in step S700, the oxide layer 30 and the barrier layer 20 are removed to form a floating gate 11a, so that a floating gate cantilever corner 11b is sharpened.

The removing of the oxide layer 30 and the barrier layer 20 specifically includes: the oxide layer 30 and the barrier layer 20 are etched using an isotropic etching process. In the etching process, the oxide layer 30 and the barrier layer 20 are etched at a rate greater than that of the floating gate 11 a.

Since a partial region of the oxide layer 30 is located under the floating gate 11a, the isotropic etching process can ensure that the oxide layer 30 is completely removed.

The floating gate cantilever angle 11b is less than 90 degrees, and further, the floating gate cantilever angle 11b is 60-80 degrees. In the present embodiment, the floating gate cantilever angle 11b is 78 degrees.

In the embodiment of the invention, because the bird's beak-shaped oxide layer is formed on the side wall of the floating gate material layer in advance, a sharpened floating gate cantilever angle is formed after the barrier layer and the oxide layer are removed simultaneously. The condition of floating gate cantilever angle passivation caused in the process of removing the oxide layer in the comparative example is avoided.

In an optional implementation manner, the barrier layer 20 and the oxide layer 30 are removed by a wet etching process, and specific parameters include: the adopted etching solution is hydrofluoric acid solution, the mass percent of hydrofluoric acid is 1:100-1:1000, and the etching temperature is 15-75 ℃.

Referring to fig. 12, in step S800, a floating gate oxide layer 20a wrapping the floating gate 11a is formed.

Referring to fig. 13, in step S900, an erase gate structure 40 is formed in the second region B.

The erase gate structure 40 includes an erase gate dielectric layer and an erase gate, and the process for forming the erase gate structure 40 may include a chemical vapor deposition process.

Referring to fig. 13, in step S1000, word lines 50 are formed in the first regions a.

The process of forming the word line 50 may include a chemical vapor deposition process.

In subsequent processes, an interconnect structure connected to the control gate stack, the erase gate, and the word line is formed. And packaging the formed semiconductor structure. To form a completed semiconductor device.

In another aspect, an embodiment of the present invention further provides a semiconductor device, where the semiconductor device includes: a front-end device layer, a floating gate and a control gate stack structure.

Fig. 14 is a schematic sectional view of a semiconductor device of an embodiment of the present invention. Referring to fig. 14, in an alternative implementation, the semiconductor device according to the embodiment of the present invention includes: front-end device layer, floating gate 11a ', control gate stack 12 ', floating gate oxide layer 20a ', erase gate 40 ' and word line 50 '.

The front end device layer includes a substrate 10'.

The floating gate 11a 'has a sharpened cantilever angle 11 b' on one side. The floating gate cantilever angle 11b 'is less than 90 degrees, and further the floating gate cantilever angle 11 b' is 60-80 degrees. In an embodiment of the present invention, the floating gate cantilever angle 11 b' is 78 degrees.

A control gate stack 12' is formed over the floating gate. The control gate stack structure 12 ' includes a gate dielectric layer 21 ', a control gate 22 ', a control gate oxide layer 23 ' and a control gate silicon nitride 24 ' stacked in sequence. And also includes sidewall layers 25' formed on both sides of the control gate.

The erase gate 40 ' is on the side of the floating gate 11a ' having a sharpened cantilever angle 11b ';

the word line 50 'is on the side of the floating gate that does not have a sharpened cantilever angle 11 b'.

The floating gate oxide layer 20a 'wraps the floating gate 11 a'.

In an embodiment of the invention, the floating gate has a sharpened floating gate cantilever angle. The electric field at the corner of the floating gate cantilever is concentrated, so that electrons in the floating gate can penetrate into the erasing gate through the corner tunnel of the floating gate cantilever, and the erasing efficiency is improved. Thereby enabling to improve the performance of the semiconductor device.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for forming a semiconductor device, wherein the method comprises:

providing a front-end device layer in which a floating gate material layer and a plurality of discrete control gate stack structures covering the floating gate material layer are formed;

removing the floating gate material layer in the first region, the first region being located on the first side of the control gate stack structure;

thinning the floating gate material layer in the second region, the second region being located on the second side of the control gate stack structure;

forming a barrier layer covering at least the floating gate material layer and the sidewalls of the control gate stack structure;

Using the control gate stack structure and the barrier layer of the sidewall of the control gate stack structure as a mask, etching the floating gate material layer to expose the sidewall of the floating gate material layer on the second side;

oxidizing the sidewall of the floating gate material layer on the second side to form an oxide layer; and

The oxide layer and the barrier layer are removed to form a floating gate, so that the cantilever angle of the floating gate is sharpened.

2 . The method of claim 1 , wherein the floating gate cantilever angle is at the top of the second side of the floating gate. 3 .

3 . The method for forming a semiconductor device according to claim 1 , wherein after the floating gate is formed, the method further comprises: 4 .

forming an erase gate structure in the second region;

A word line is formed in the first region.

4. The method for forming a semiconductor device according to claim 1, wherein the oxidizing the sidewall of the floating gate material layer is specifically:

A thermal oxidation process is used to convert the floating gate material layer in a predetermined area into an oxide layer.

5 . The method for forming a semiconductor device according to claim 4 , wherein the predetermined region is a region extending laterally and longitudinally with a predetermined size from the sidewall of the floating gate material layer on the second side. 6 .

6. The method for forming a semiconductor device according to claim 1, wherein the thinning of the floating gate material layer in the second region is specifically:

A self-aligned etching process is used to thin the floating gate material layer on the second side of the control gate stack structure by 20 angstroms to 50 angstroms.

7 . The method for forming a semiconductor device according to claim 1 , wherein the material of the barrier layer is silicon oxide or silicon nitride, and the thickness of the barrier layer is 20 angstroms to 50 angstroms. 8 .

8. The method for forming a semiconductor device according to claim 1, wherein the removing the oxide layer and the barrier layer is specifically:

The oxide layer and the barrier layer are etched using an isotropic etching process.

9. A semiconductor device, characterized in that the semiconductor device comprises:

Front-end device layer;

a floating gate with sharpened cantilever corners on one side; and

A control gate stack structure is formed on the floating gate.

10. The semiconductor device according to claim 9, wherein the semiconductor device further comprises:

an erase gate, on the side of the floating gate with a sharpened cantilever angle;

Word lines, on the side of the floating gate where the cantilever corners are not sharpened.