CN114005832A - NAND flash memory device and manufacturing method of NAND flash memory - Google Patents
NAND flash memory device and manufacturing method of NAND flash memory Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 91
- 230000003647 oxidation Effects 0.000 claims abstract description 44
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 44
- 239000000463 material Substances 0.000 claims abstract description 39
- 238000005530 etching Methods 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000000231 atomic layer deposition Methods 0.000 claims abstract description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims description 18
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 12
- 239000001301 oxygen Substances 0.000 claims description 12
- 229910052760 oxygen Inorganic materials 0.000 claims description 12
- 239000007789 gas Substances 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 238000001312 dry etching Methods 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- RJCRUVXAWQRZKQ-UHFFFAOYSA-N oxosilicon;silicon Chemical compound [Si].[Si]=O RJCRUVXAWQRZKQ-UHFFFAOYSA-N 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
- H01L21/76852—Barrier, adhesion or liner layers the layer covering a conductive structure the layer also covering the sidewalls of the conductive structure
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
- H10B41/44—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a control gate layer also being used as part of the peripheral transistor
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Abstract
The invention provides a manufacturing method of a NAND flash memory, which comprises the following steps: providing a substrate, forming at least two floating gate layers on the substrate, arranging an opening between every two adjacent floating gate layers, forming a first side wall on each floating gate layer, and covering the side wall and the top of each floating gate layer by the first side wall; forming a control gate material layer, wherein the control gate material layer fills the opening and covers the first side wall; performing an etching process on the control gate material layer to form a control gate layer, and forming a floating gate layer residue at the floating gate layer; performing an atomic layer deposition oxidation process to form a first oxide layer, wherein the first oxide layer covers the control gate layer and the opening; and performing a rapid thermal oxidation process to form a second oxide layer, wherein the process gas of the rapid thermal oxidation process penetrates through the first oxide layer to remove the residues of the floating gate layer. The problems of short circuit and electric leakage of adjacent floating gates caused by residues of the floating gates in the etching process of the control gates are solved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a NAND flash memory device and a manufacturing method of the NAND flash memory.
Background
NAND flash memory is a better storage device than hard disk drives, and is widely used in electronic products as people seek nonvolatile storage products with low power consumption, light weight and good performance.
During the control gate etch at NAND FLASH, the Floating Gate (FG) is surrounded by silicon oxide-silicon nitride-silicon oxide (ONO). The floating gate is made of polysilicon, and when the etching speed of the silicon oxide-silicon nitride-silicon oxide is different from that of the polysilicon, a fence (fence) of the silicon oxide-silicon nitride-silicon oxide is formed at the side edge of the floating gate, and a residue (residue) of the floating gate is formed at the side edge of the silicon oxide-silicon nitride-silicon oxide. The residue of the floating gate can cause shorting of adjacent floating gates and leakage.
Disclosure of Invention
The invention aims to provide a NAND flash memory device and a manufacturing method of the NAND flash memory device, and aims to solve the problems of short circuit and electric leakage of adjacent floating gates caused by residues of the floating gates in the etching process of control gates.
In order to solve the above technical problem, the present invention provides a method for manufacturing a NAND flash memory, including:
providing a substrate, forming at least two floating gate layers on the substrate, arranging an opening between every two adjacent floating gate layers, forming a first side wall on each floating gate layer, and covering the side wall and the top of each floating gate layer by the first side wall;
forming a control gate material layer, wherein the control gate material layer fills the opening and covers the first side wall;
performing an etching process on the control gate material layer to form a control gate layer, and forming a floating gate layer residue at the floating gate layer;
performing an atomic layer deposition oxidation process to form a first oxide layer, wherein the first oxide layer covers the control gate layer and the opening;
and carrying out a rapid thermal oxidation process to form a second oxidation layer, wherein the process gas of the rapid thermal oxidation process penetrates through the first oxidation layer to remove the residues of the floating gate layer.
Optionally, the floating gate layer is made of polysilicon.
Optionally, the process gas in the rapid thermal oxidation process includes oxygen, and the oxygen reacts with the floating gate layer residue to form a silicon oxide layer.
Optionally, the thickness of the floating gate layer residue removed in the rapid thermal oxidation process is not more than 1 nm.
Optionally, the process temperature of the rapid thermal oxidation process is 850 ℃ to 950 ℃.
Optionally, the thickness of the first oxide layer formed by the atomic layer deposition oxidation process is 10 angstroms to 40 angstroms.
Optionally, before the control gate material layer is subjected to the etching process, a hard mask layer is further formed on the control gate material layer.
Optionally, before the control gate material layer is subjected to the etching process, a patterned photoresist is formed on the hard mask layer.
Optionally, the control gate material layer is etched by a dry etching process.
Based on the same inventive concept, the present invention also provides a NAND flash memory device, comprising:
the floating gate structure comprises a substrate, wherein at least two floating gate layers are formed on the substrate, an opening is formed between every two adjacent floating gate layers, a first side wall is formed on each floating gate layer, and the top of each floating gate layer is covered by each first side wall;
the control gate layer is positioned on the upper part of the first side wall;
the first oxide layer covers the control gate layer;
and the second oxide layer is formed by rapid thermal oxidation of the floating gate layer residues and oxygen, and covers the first oxide layer.
Compared with the prior art, the invention has the following beneficial effects:
in the NAND flash memory device and the manufacturing method of the NAND flash memory, provided by the invention, an etching process is carried out on a control gate material layer, when a control gate layer is formed, a floating gate layer residue is formed at the floating gate layer, a first oxide layer is formed by adopting an atomic layer deposition oxidation process, the first oxide layer covers the control gate layer and an opening, through a rapid thermal oxidation process, process gas of the rapid thermal oxidation process penetrates through the first oxide layer to remove the floating gate layer residue, the control gate layer is a control gate, and the floating gate layer is a floating gate; therefore, the problems of short circuit and electric leakage of adjacent floating gates caused by residues of the floating gates in the etching process of the control gates can be solved.
Drawings
FIG. 1 is a flow chart of a method of fabricating a NAND flash memory according to an embodiment of the present invention;
FIGS. 2-5 are cross-sectional views of structures formed in a method of fabricating a NAND flash memory according to an embodiment of the present invention;
in the figure, the position of the upper end of the main shaft,
100-a substrate; 101-a gate oxide layer; 102-a floating gate layer; 103-a first side wall; 104-a control gate material layer, 104 a-a control gate layer; 105-a second hard mask layer; 106-a second patterned photoresist; 107-floating gate layer residue; 108-a first oxide layer; 109-second oxide layer.
Detailed Description
The following describes a NAND flash memory device and a method for manufacturing a NAND flash memory according to the present invention in detail with reference to the accompanying drawings and embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Specifically, referring to fig. 1, fig. 1 is a flowchart of a method for manufacturing a NAND flash memory according to an embodiment of the invention. As shown in fig. 1, the present embodiment provides a method for manufacturing a NAND flash memory, including:
step S10, providing a substrate, forming at least two floating gate layers on the substrate, arranging an opening between every two adjacent floating gate layers, forming a first side wall on each floating gate layer, and covering the side wall and the top of each floating gate layer with the first side wall.
Step S20, forming a control gate material layer, wherein the control gate material layer fills the opening and covers the first sidewall;
step S30, carrying out etching process on the control gate material layer to form a control gate layer, and forming a floating gate layer residue at the floating gate layer;
step S40, performing an atomic layer deposition oxidation process to form a first oxide layer, wherein the first oxide layer covers the control gate layer and the opening;
step S50, performing a rapid thermal oxidation process to form a second oxide layer, wherein the process gas of the rapid thermal oxidation process penetrates the first oxide layer to remove the residue of the floating gate layer.
FIGS. 2-5 are cross-sectional views of structures formed in a method of fabricating a NAND flash memory according to an embodiment of the present invention; the method for manufacturing the NAND flash memory provided in the present embodiment will be described in more detail with reference to fig. 2 to 5.
First, step S10 is executed, as shown in fig. 2, a substrate 100 is provided, where the substrate 100 may be monocrystalline silicon or polycrystalline silicon, or a semiconductor material such as silicon, germanium, silicon germanium, gallium arsenide, or a composite structure such as silicon-on-insulator. A person skilled in the art may select the type of the semiconductor substrate 100 according to the semiconductor devices formed on the semiconductor substrate 100, and therefore the type of the semiconductor substrate 100 should not limit the scope of the present invention. At least two floating gate layers 102 are formed on the substrate 100, an opening (not shown in the figure) is arranged between adjacent floating gate layers 102, a first side wall 103 is formed on the floating gate layer 102, and the first side wall 103 covers the side wall and the top of the floating gate layer 102.
Before forming the floating gate layer 102, a gate oxide layer 101 is formed on the substrate 100, and the gate oxide layer 101 may be formed through a thermal oxidation process. Forming a floating gate material layer on the gate oxide layer 101, and depositing a first hard mask layer (not shown in the figure) on the floating gate material layer, wherein the first hard mask layer is, for example, silicon nitride, and can be deposited in a chemical vapor deposition manner, forming a patterned photoresist layer on the first hard mask layer, and etching the first hard mask layer by using the patterned photoresist layer as a mask to form a first patterned hard mask layer; the first patterned hard mask layer and the first patterned photoresist layer form a mask pattern. And etching the floating gate layer material layer by using the first patterned hard mask layer and the first patterned photoresist layer as a mask, forming an opening in the floating gate layer material layer, and etching the floating gate layer material layer into the floating gate layer 102. After the step of forming the floating gate layer, if the first patterned photoresist is not consumed, a photoresist removing process is also required, and an ashing process or a stripping process is generally used to remove the residual first patterned photoresist. The first sidewall 103 deposited on the top and the sidewall of the floating gate layer 102 can be formed by chemical vapor deposition, and in this embodiment, the first sidewall 103 is, for example, an ONO stack, i.e., a silicon oxide-silicon nitride-silicon oxide layer. The floating gate layer 102 is a floating gate.
Next, step S20 is performed, as shown in fig. 2, a control gate material layer 104 is formed, and the control gate material layer 104 fills the opening and covers the first sidewall 103. The control gate material layer 104 is, for example, polysilicon, and the control gate material layer 104 may be formed by chemical vapor deposition.
After step S20, before step S30, a second hard mask layer 105 and a second patterned photoresist 106 are formed on the control gate material layer 104. The second hard mask layer 105 is, for example, silicon nitride, and may be deposited by chemical vapor deposition to form a second patterned photoresist layer 106 on the second hard mask layer 105.
Next, step S30 is executed, as shown in fig. 3, an etching process is performed on the control gate material layer 104 to form a control gate layer 104a, and a floating gate layer residue 107 is formed at the floating gate layer 102.
In step S30, the second patterned photoresist layer 106 is used as a mask to etch the second hard mask layer 105, so as to form a second patterned hard mask layer 105 a; the second patterned hard mask layer 105a and the second patterned photoresist layer 106 constitute a mask pattern. And etching the control gate material layer 104 by using the second patterned hard mask layer 105a and the second patterned photoresist layer 106 as a mask to form a control gate layer 104 a. After the step of forming the control gate layer 104a, if the second patterned photoresist 106 is not consumed, a photoresist removing process is further performed, and the residual second patterned photoresist 106 is removed by an ashing process or a stripping process.
The etching process is for example a dry etching process. During the etching process for the control gate material layer 104, the floating gate layer 102 is surrounded by the first sidewall 103. The material of the first sidewall 103 is, for example, ONO, the material of the floating gate layer 102 is, for example, polysilicon, and the ONO etching rate is different from the poly etching rate, so that ONO barriers (fense) are formed at the side edges of the floating gate layer 102, and floating gate layer residues (residue)107 are formed at the side edges of the ONO. In this embodiment, the control gate layer 104a is a control gate.
Next, step S40 is executed, as shown in fig. 4, an Atomic Layer Deposition (ALD) oxidation process is performed to form a first oxide layer 108, wherein the first oxide layer 108 covers the control gate layer 104 a; the atomic layer deposition oxidation process forms the first oxide layer 108 to a thickness of, for example, 10-40 angstroms.
Next, in step S50, as shown in fig. 5, a Rapid Thermal Oxidation (RTO) process is performed to form the second oxide layer 109, and the rapid thermal oxidation process penetrates the first oxide layer 108 to remove the floating gate layer residue 107.
In the present embodiment, the process temperature of the rapid thermal oxidation process is, for example, 850 ℃ to 950 ℃. The process gas in the rapid thermal oxidation process includes oxygen, the oxygen reacts with the floating gate layer residue 107 to generate the second oxide layer 109, and the floating gate layer residue 107 is polysilicon, that is, the oxygen in the rapid thermal oxidation process passes through the first oxide layer 108 and reacts with the floating gate layer residue 107 to generate the second oxide layer 109, so as to remove the floating gate layer residue 107, thereby avoiding the short circuit and electric leakage phenomena of the adjacent floating gate layer due to the floating gate layer residue 107. The thickness of the floating gate layer 102 removed in the rapid thermal oxidation process does not exceed 1 nanometer. The first oxide layer 108 can control the reaction amount of oxygen and the floating gate layer residue 107 in the rapid thermal oxidation process, and prevent the oxygen from continuing to react with the floating gate layer 102. The second oxide layer 109 formed by the rapid thermal oxidation process is denser, improving the performance of the NAND flash memory device. The first oxide layer 108 and the second oxide layer 109 constitute a sidewall of the control gate layer 104 a.
With continuing reference to fig. 5, based on the same inventive concept, the present embodiment also provides a NAND flash memory device, including:
the floating gate structure comprises a substrate 100, wherein at least two floating gate layers 102 are formed on the substrate 100, an opening is formed between every two adjacent floating gate layers 102, a first side wall 103 is formed on each floating gate layer 102, and the top of each floating gate layer 102 is covered by the first side wall 103;
a control gate layer 104a, wherein the control gate layer 104a is positioned at the upper part of the first side wall 103;
a first oxide layer 108, wherein the first oxide layer 108 covers the control gate layer 104 a;
and a second oxide layer 109 formed by rapid thermal oxidation of the floating gate layer residue and oxygen, the second oxide layer 109 covering the first oxide layer 108.
In this embodiment, the floating gate layer 102 is a floating gate, the control gate layer 104a is a control gate, and the first oxide layer 108 and the second oxide layer 109 form a sidewall of the control gate layer 104 a.
In summary, in the NAND flash memory device and the method for manufacturing the NAND flash memory provided by the embodiment of the present invention, the control gate material layer is subjected to an etching process, when the control gate layer is formed, a floating gate layer residue is formed at the floating gate layer, a first oxide layer is formed by using an atomic layer deposition oxidation process, the first oxide layer covers the control gate layer, and through a rapid thermal oxidation process, a process gas of the rapid thermal oxidation process penetrates through the first oxide layer to remove the floating gate layer residue, the control gate layer is a control gate, and the floating gate layer is a floating gate; therefore, the problems of short circuit and electric leakage of adjacent floating gates caused by residues of the floating gates in the etching process of the control gates can be solved.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (10)
1. A method for manufacturing a NAND flash memory is characterized by comprising the following steps:
providing a substrate, forming at least two floating gate layers on the substrate, arranging an opening between every two adjacent floating gate layers, forming a first side wall on each floating gate layer, and covering the side wall and the top of each floating gate layer by the first side wall;
forming a control gate material layer, wherein the control gate material layer fills the opening and covers the first side wall;
performing an etching process on the control gate material layer to form a control gate layer, and forming a floating gate layer residue at the floating gate layer;
performing an atomic layer deposition oxidation process to form a first oxide layer, wherein the first oxide layer covers the control gate layer and the opening;
and carrying out a rapid thermal oxidation process to form a second oxidation layer, wherein the process gas of the rapid thermal oxidation process penetrates through the first oxidation layer to remove the residues of the floating gate layer.
2. The method of claim 1, wherein the floating gate layer is made of polysilicon.
3. The method of claim 1, wherein a process gas in the rapid thermal oxidation process comprises oxygen, and wherein the oxygen reacts with the floating gate layer residue to form a second oxide layer.
4. The method of claim 1, wherein the thickness of the floating gate layer residue removed in the rapid thermal oxidation process is no more than 1 nm.
5. The method of claim 1, wherein the process temperature of the rapid thermal oxidation process is 850 ℃ to 950 ℃.
6. The method of claim 1, wherein the atomic layer deposition oxidation process forms the first oxide layer to a thickness of 10-40 angstroms.
7. The method of claim 1, wherein a hard mask layer is further formed on the control gate material layer before the etching process is performed on the control gate material layer.
8. The method of claim 7, wherein a patterned photoresist is formed on the hard mask layer before the etching process is performed on the control gate material layer.
9. The method of claim 1, wherein the etching process for the control gate material layer is a dry etching process.
10. A NAND flash memory device, comprising:
the floating gate structure comprises a substrate, wherein at least two floating gate layers are formed on the substrate, an opening is formed between every two adjacent floating gate layers, a first side wall is formed on each floating gate layer, and the top of each floating gate layer is covered by each first side wall;
the control gate layer is positioned on the upper part of the first side wall;
the first oxide layer covers the control gate layer;
and the second oxide layer is formed by rapid thermal oxidation of the floating gate layer residues and oxygen, and covers the first oxide layer.
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