CN112652715A - Memory cell, capacitor structure and preparation method thereof - Google Patents
Memory cell, capacitor structure and preparation method thereof Download PDFInfo
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- CN112652715A CN112652715A CN201910961668.5A CN201910961668A CN112652715A CN 112652715 A CN112652715 A CN 112652715A CN 201910961668 A CN201910961668 A CN 201910961668A CN 112652715 A CN112652715 A CN 112652715A
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- 239000003990 capacitor Substances 0.000 title claims abstract description 82
- 238000002360 preparation method Methods 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims abstract description 93
- 238000000034 method Methods 0.000 claims abstract description 43
- 238000004519 manufacturing process Methods 0.000 claims abstract description 14
- 238000002955 isolation Methods 0.000 claims description 27
- 238000005530 etching Methods 0.000 claims description 20
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 5
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 238000011049 filling Methods 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 252
- 238000010586 diagram Methods 0.000 description 24
- 239000007772 electrode material Substances 0.000 description 21
- 239000000463 material Substances 0.000 description 21
- 229910052721 tungsten Inorganic materials 0.000 description 10
- 239000010937 tungsten Substances 0.000 description 10
- 239000007787 solid Substances 0.000 description 8
- 238000007740 vapor deposition Methods 0.000 description 8
- 238000000231 atomic layer deposition Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 5
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 229910052707 ruthenium Inorganic materials 0.000 description 5
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 5
- 229910052719 titanium Inorganic materials 0.000 description 5
- 239000010936 titanium Substances 0.000 description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 5
- -1 tungsten nitride Chemical class 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 239000005388 borosilicate glass Substances 0.000 description 2
- 239000002355 dual-layer Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/01—Manufacture or treatment
- H10D1/041—Manufacture or treatment of capacitors having no potential barriers
- H10D1/042—Manufacture or treatment of capacitors having no potential barriers using deposition processes to form electrode extensions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H10D1/692—Electrodes
- H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
- H10D1/716—Electrodes having non-planar surfaces, e.g. formed by texturisation having vertical extensions
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Abstract
The present disclosure provides a memory cell, a capacitor structure and a method of fabricating the same. The method comprises the following steps: forming a first dielectric layer on a substrate; forming a plurality of first electrode holes on the first dielectric layer, wherein the first electrode holes comprise a first hole section and a second hole section which are distributed and communicated along the extension direction of the first electrode holes, and the cross section of the first hole section is larger than that of the second hole section; forming a first lower electrode in the first electrode hole; forming a second dielectric layer on one side of the first dielectric layer far away from the substrate; forming a second electrode hole in a region corresponding to the first electrode hole on the second dielectric layer; and forming a second lower electrode in the second electrode hole, wherein the second lower electrode is in contact with the first lower electrode. The height of the capacitor structure can be improved.
Description
Technical Field
The present disclosure relates to the field of integrated circuit technologies, and in particular, to a memory cell, a capacitor structure, and a method for manufacturing a capacitor structure.
Background
With the rapid development of integrated circuit technology, memory cells are attracting more and more attention.
A capacitor is an essential structure for storing charges in a dram, and in order to make the capacitor structure have a high amount of stored charges, the height of the capacitor structure needs to be increased. How to prepare a capacitor structure to increase the height of the capacitor structure has been a problem to be solved in the art.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
The present disclosure is directed to a memory cell, a capacitor structure and a method for manufacturing the capacitor structure, which can increase the height of the capacitor structure.
According to one aspect of the present disclosure, there is provided a method of making a capacitor structure, comprising:
providing a substrate;
forming a first dielectric layer on the substrate;
forming a plurality of first electrode holes in the first dielectric layer, wherein each first electrode hole comprises a first hole section and a second hole section, the first hole sections and the second hole sections are distributed and communicated along the extending direction of the first electrode hole, the first hole sections are positioned on one sides, far away from the substrate, of the second hole sections, and the cross sections of the first hole sections are larger than those of the second hole sections;
filling a first lower electrode in each first electrode hole;
forming a second dielectric layer on one side of the first dielectric layer far away from the substrate;
forming a second electrode hole in a region corresponding to the first electrode hole on the second dielectric layer;
and forming a second lower electrode in each second electrode hole, wherein the second lower electrode is in contact with the first lower electrode.
In one exemplary embodiment of the present disclosure, forming a first dielectric layer on the substrate includes:
forming a preset dielectric layer on the substrate;
forming a first dielectric layer on one side of the preset dielectric layer far away from the substrate;
the preset dielectric layer is provided with a conductive plug, the first electrode holes are formed in the first dielectric layer and correspond to the regions of the conductive plug, each first electrode hole further comprises a third hole section, the third hole sections and the second hole sections are distributed and communicated along the extending direction of the first electrode hole, the third hole sections are located on one side, close to the substrate, of the second hole sections, and the cross sections of the third hole sections are larger than the cross sections of the second hole sections.
In one exemplary embodiment of the present disclosure, forming a first dielectric layer on the substrate includes:
forming an isolation layer on the substrate;
forming a first sacrificial layer on one side of the isolation layer, which is far away from the substrate;
forming a first support layer on one side of the first sacrificial layer, which is far away from the substrate, wherein the isolation layer, the first sacrificial layer and the first support layer form a first dielectric layer;
forming a plurality of first electrode holes on the first dielectric layer includes:
patterning the first dielectric layer to form a plurality of first through holes on the first dielectric layer;
etching the first dielectric layer to enable the first through hole to form a first electrode hole, wherein the etching rate of the first sacrificial layer is smaller than that of the first support layer;
the first electrode hole is located on the first support layer and is the first hole section, and the first electrode hole is located on the first sacrificial layer and is the second hole section.
In an exemplary embodiment of the present disclosure, the first sacrificial layer is silicon oxide, and the first support layer is silicon nitride.
In an exemplary embodiment of the present disclosure, etching the first dielectric layer includes:
and etching the first dielectric layer by using phosphoric acid.
In one exemplary embodiment of the present disclosure, forming the isolation layer on the substrate includes:
forming a preset dielectric layer on the substrate;
forming an isolation layer on one side of the preset dielectric layer, which is far away from the substrate;
the preset dielectric layer is provided with a conductive plug, the first electrode hole is formed in a region, corresponding to the conductive plug, on the first dielectric layer, the etching rate of the first sacrificial layer is smaller than that of the isolation layer, the part, located on the isolation layer, of the first electrode hole is a third hole section, and the cross section of the third hole section is larger than that of the second hole section.
In an exemplary embodiment of the present disclosure, forming a second dielectric layer on a side of the first dielectric layer away from the substrate includes:
forming a second sacrificial layer on one side of the first support layer far away from the substrate;
forming a second supporting layer on one side, far away from the first supporting layer, of the second sacrificial layer, wherein the second supporting layer and the second sacrificial layer form a second dielectric layer;
the preparation method of the capacitor structure further comprises the following steps:
forming a second via hole on the second support layer, the second via hole penetrating through the first support layer and the second support layer to expose the first sacrificial layer and the second sacrificial layer;
removing the second sacrificial layer and the first sacrificial layer;
depositing a third dielectric layer on the surface of the first lower electrode and the surface of the second lower electrode;
and forming an upper electrode on the surface of the third dielectric layer.
According to an aspect of the present disclosure, there is provided a capacitor structure including:
a substrate;
the first lower electrode is arranged on the substrate and comprises a main body part and a first connecting part which are connected with each other along the direction vertical to the substrate, the first connecting part is positioned on one side of the main body part away from the substrate, and the cross-sectional area of the first connecting part in the direction parallel to the substrate is larger than that of the main body part in the direction parallel to the substrate;
and the second lower electrode is arranged on one side of the first lower electrode, which is far away from the substrate, and is in contact with the first connecting part.
In an exemplary embodiment of the present disclosure, the capacitor structure further includes:
the preset dielectric layer is arranged on the substrate and provided with a conductive plug;
the first lower electrode is arranged on the preset dielectric layer and further comprises a second connecting portion along the direction perpendicular to the substrate, the second connecting portion is connected to one side, away from the first connecting portion, of the main body portion, the cross-sectional area of the second connecting portion in the direction parallel to the substrate is larger than that of the main body portion in the direction parallel to the substrate, and the second connecting portion is in contact with the conductive plug.
According to an aspect of the present disclosure, there is provided a memory cell comprising the capacitor structure of any one of the above.
According to the memory cell, the capacitor structure and the preparation method of the capacitor structure, the first lower electrode is formed in the first electrode hole, the second lower electrode is formed in the second electrode hole, and the cross section of the first hole section is larger than that of the second hole section, so that the cross section of the first lower electrode in the first hole section is increased, the second lower electrode is more easily contacted with the first lower electrode, and the height of the capacitor structure is further improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The above and other features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.
Fig. 1 is a flow chart of a method of making a capacitor structure according to an embodiment of the present disclosure;
fig. 2 is a flowchart of step S110 in a method for manufacturing a capacitor structure according to an embodiment of the present disclosure;
fig. 3 is a schematic diagram of the capacitor structure according to the embodiment of the disclosure after step S110 is completed;
fig. 4 is a flowchart of step S120 in a method of manufacturing a capacitor structure according to an embodiment of the present disclosure;
fig. 5 is a schematic diagram of the capacitor structure according to the embodiment of the disclosure after step S12011 is completed;
fig. 6 is a schematic diagram of the capacitor structure according to the embodiment of the disclosure after step S12012 is completed;
fig. 7 is a schematic diagram of the capacitor structure according to the embodiment of the disclosure after step S12013 is completed;
fig. 8 is a schematic diagram of the capacitor structure according to the embodiment of the disclosure after step S12014 is completed;
fig. 9 is a schematic diagram of the capacitor structure according to the embodiment of the disclosure after step S12015 is completed;
fig. 10 is a schematic diagram of the capacitor structure according to the embodiment of the disclosure after step S12016 is completed;
FIG. 11 is a schematic view of the structure of FIG. 10 from another perspective;
fig. 12 is a schematic diagram of the capacitor structure according to the embodiment of the disclosure after step S1202 is completed;
fig. 13 is a flowchart of step S130 in a method of manufacturing a capacitor structure according to an embodiment of the present disclosure;
fig. 14 is a schematic diagram of the capacitor structure according to the embodiment of the disclosure after step S1301 is completed;
fig. 15 is a schematic diagram of the capacitor structure according to the embodiment of the disclosure after step S1302 is completed;
fig. 16 is a flowchart of step S140 in the method of manufacturing a capacitor structure according to the embodiment of the present disclosure;
fig. 17 is a schematic view of the capacitor structure according to the embodiment of the disclosure after step S140 is completed;
fig. 18 is a schematic view of the capacitor structure according to the embodiment of the disclosure after step S150 is completed;
fig. 19 is a schematic diagram after completion of step S160 in the process of fabricating a solid capacitor using the method of the present disclosure;
fig. 20 is a schematic diagram of a hybrid capacitor manufactured by the method of the present disclosure after completion of step S1601;
fig. 21 is a schematic diagram of a hybrid capacitor manufactured by the method of the present disclosure after completion of step S1602;
FIG. 22 is a flow chart of a method of making a capacitor structure in another embodiment;
fig. 23 is a schematic diagram after completion of step S170 in the process of fabricating a solid capacitor using the method of the present disclosure;
fig. 24 is a schematic diagram of a hybrid capacitor manufactured using the method of the present disclosure after completion of step S170;
fig. 25 is a schematic diagram after completion of step S180 in the process of making a solid capacitor using the method of the present disclosure;
fig. 26 is a schematic diagram after completion of step S180 in the process of fabricating a hybrid capacitor using the method of the present disclosure;
fig. 27 is a schematic diagram after completion of step S190 in the process of fabricating a solid capacitor using the method of the present disclosure;
fig. 28 is a schematic diagram of a hybrid capacitor manufactured using the method of the present disclosure after completion of step S190;
fig. 29 is a schematic diagram after completion of step S200 in the process of fabricating a solid capacitor using the method of the present disclosure;
fig. 30 is a schematic diagram of a hybrid capacitor manufactured using the method of the present disclosure after completion of step S200;
fig. 31 is a schematic diagram after completion of step S210 in the process of fabricating a solid capacitor using the method of the present disclosure;
fig. 32 is a schematic diagram of a hybrid capacitor manufactured using the method of the present disclosure after completion of step S210;
fig. 33 is a schematic diagram of a first lower electrode in a capacitor structure according to an embodiment of the disclosure.
In the figure: 1. presetting a dielectric layer; 2. a conductive plug; 3. a first dielectric layer; 301. an isolation layer; 302. a first sacrificial layer; 303. a first support layer; 4. a hard mask layer; 5. an anti-reflection layer; 6. a photoresist layer; 7. a first through hole; 8. a first electrode hole; 801. a first bore section; 802. a second bore section; 803. a third bore section; 9. a first electrode material layer; 10. a first lower electrode; 11. a second dielectric layer; 1101. a second support layer; 1102. a second sacrificial layer; 12. a second electrode hole; 13. a second lower electrode; 14. a second electrode material layer; 15. a second through hole; 16. a third dielectric layer; 17. an upper electrode; 18. a polysilicon layer.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the subject matter of the present disclosure can be practiced without one or more of the specific details, or with other methods, materials, devices, etc. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.
Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus their repetitive description will be omitted. The terms "a" and "the" are used to indicate the presence of one or more elements/components/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.
The embodiment of the disclosure provides a preparation method of a capacitor structure. As shown in fig. 1, the method for manufacturing the capacitor structure may include steps S100 to S160, wherein:
step S100, providing a substrate.
Step S110 is to form a first dielectric layer on the substrate.
Step S120, forming a plurality of first electrode holes in the first dielectric layer, where each first electrode hole includes a first hole section and a second hole section, the first hole section and the second hole section are distributed and communicated along an extending direction of the first electrode hole, the first hole section is located on one side of the second hole section, which is far away from the substrate, and a cross section of the first hole section is larger than a cross section of the second hole section.
Step S130, filling the first electrode hole with a first lower electrode.
Step S140 is to form a second dielectric layer on the side of the first dielectric layer away from the substrate.
Step S150, forming a second electrode hole on the second dielectric layer in a region corresponding to the first electrode hole.
Step S160, forming a second lower electrode in each second electrode hole, wherein the second lower electrode is in contact with the first lower electrode.
According to the preparation method of the capacitor structure, the first lower electrode is formed in the first electrode hole, the second lower electrode is formed in the second electrode hole, and the cross section of the first hole section is larger than that of the second hole section, so that the cross section of the first lower electrode located in the first hole section is increased, the second lower electrode is more easily contacted with the first lower electrode, and the height of the capacitor structure is further increased.
The following is a detailed description of the steps of the method of making the capacitor structure of the embodiments of the present disclosure:
in step S100, a substrate is provided.
The substrate may be a single crystal silicon substrate, a single crystal germanium substrate, a silicon-on-insulator (SOI) substrate, or the like, and the substrate may be doped or undoped, which is not limited in this disclosure. Structures such as word lines, bit lines, etc. may be formed on the substrate. As shown in fig. 3, a predetermined dielectric layer 1 is formed above the substrate, and a conductive plug 2 is formed in the predetermined dielectric layer 1, but the embodiment of the present disclosure is not limited thereto.
In step S110, a first dielectric layer is formed on a substrate.
For example, as shown in fig. 2, step S110 may include steps S1101 to S1103, wherein:
step S1101 is to form an isolation layer on the substrate.
As shown in fig. 3, the isolation layer 301 may be formed on a side of the predetermined dielectric layer 1 away from the substrate. The isolation layer 301 may be prepared by vapor deposition, but the embodiments of the present disclosure are not limited thereto. The material of the isolation layer 301 may be silicon nitride, but may also be other materials.
Step S1102, forming a first sacrificial layer on a side of the isolation layer away from the substrate.
As shown in fig. 3, the first sacrificial layer 302 may be prepared by vapor deposition, but the embodiments of the disclosure are not limited thereto. The material of the first sacrificial layer 302 may be silicon oxide, and of course, the material of the first sacrificial layer 302 may also be BPSG (borophosphosilicate glass), BSG (borosilicate glass), PSG (phosphosilicate glass), or the like.
Step S1103, forming a first support layer on a side of the first sacrificial layer away from the substrate, where the isolation layer, the first sacrificial layer, and the first support layer form a first dielectric layer.
As shown in fig. 3, the first support layer 303 may be prepared by vapor deposition, but the embodiments of the present disclosure are not limited thereto. The material of the first support layer 303 may be silicon nitride, but may also be silicon oxynitride (SiON), silicon carbon nitride (SiCN), or the like.
In step S120, a plurality of first electrode holes are formed in the first dielectric layer, each first electrode hole includes a first hole section and a second hole section, the first hole section and the second hole section are distributed and communicated along an extending direction of the first electrode hole, the first hole section is located on one side of the second hole section away from the substrate, and a cross section of the first hole section is larger than a cross section of the second hole section.
As shown in fig. 12, the first electrode hole 8 penetrates the isolation layer 301, the first sacrificial layer 302, and the first support layer 303. The first electrode hole 8 is formed in a region of the first dielectric layer 3 corresponding to the conductive plug 2 on the predetermined dielectric layer 1 to expose the conductive plug 2 on the predetermined dielectric layer 1, so that the first lower electrode formed in the first electrode hole 8 is connected to the conductive plug 2. The cross-section of the first bore section 801 is larger than the cross-section of the second bore section 802. Furthermore, each first electrode hole 8 comprises a third hole section 803. The third hole segments 803 and the second hole segments 802 are distributed and communicate along the extension direction of the first electrode hole 8. The third hole section 803 is located at one side of the second hole section 802 close to the predetermined dielectric layer 1, and the cross section of the third hole section 803 is larger than that of the second hole section 802, so that the first lower electrode in the first electrode hole 8 is more easily contacted with the conductive plug 2.
Taking the first dielectric layer including the isolation layer, the first sacrificial layer and the first support layer as an example, as shown in fig. 4, step S120 may include step S1201 and step S1202, where:
step S1201, patterning the first dielectric layer to form a plurality of first through holes on the first dielectric layer.
As shown in fig. 10, the first via 7 penetrates the isolation layer 301, the first sacrificial layer 302 and the first support layer 303. The first through hole 7 is formed in the first dielectric layer 3 in a region corresponding to the conductive plug 2 on the predetermined dielectric layer 1. Patterning the first dielectric layer 3 may include: step S12011, as shown in fig. 5, forming a hard mask layer 4, an anti-reflection layer 5, and a photoresist layer 6 in sequence on a side of the first support layer 303 away from the preset dielectric layer 1; step S12012, as shown in fig. 6, defining a pattern for forming the first via hole 7 by a process such as exposure, development, etc.; step S12013, as shown in fig. 7, etching the anti-reflection layer 5 and the hard mask layer 4 with the photoresist layer 6 as a mask, and transferring the pattern to the hard mask layer 4; step S12014, as shown in fig. 8, removing the photoresist layer 6 and the anti-reflection layer 5; step S12015, as shown in fig. 9, etching the first dielectric layer 3 with the hard mask layer 4 as a mask, thereby forming a plurality of first through holes 7; in step S12016, as shown in fig. 10, the hard mask layer 4 is removed. Further, the structure of removing the hard mask layer 4 may be as shown in fig. 11, and the structure shown in fig. 10 is a cross-sectional view a-a of the structure shown in fig. 11.
Step S1202, the first dielectric layer is etched, so that the first through hole forms a first electrode hole, and the etching rate of the first sacrificial layer is smaller than that of the first support layer.
As shown in fig. 12, a portion of the first electrode hole 8 located on the first support layer 303 is a first hole section 801, a portion of the first electrode hole 8 located on the first sacrificial layer 302 is a second hole section 802, and since the etching rate of the first sacrificial layer 302 is smaller than that of the first support layer 303, the cross section of the first hole section 801 is larger than that of the second hole section 802. In one embodiment, the material of the first sacrificial layer 302 is silicon oxide, the material of the first support layer 303 is silicon nitride, and phosphoric acid is used for etching, so that the etching rate of the first sacrificial layer 302 is less than that of the first support layer 303. In other embodiments of the present disclosure, the first sacrificial layer 302, the first support layer 303 and the etching solution may be other substances as long as the etching rate of the first sacrificial layer 302 is lower than that of the first support layer 303. The part of the first electrode hole 8 located in the isolation layer 301 is a third hole segment 803. Wherein the etch rate of the first sacrificial layer 302 is also smaller than the etch rate of the isolation layer 301, so that the cross section of the third hole segment 803 is larger than the cross section of the second hole segment 802.
In step S130, the first electrode hole is filled with a first lower electrode.
As shown in fig. 12 and 15, since the cross-section of the first hole section 801 is larger than that of the second hole section 802, the cross-section of the first lower electrode 10 at the first hole section 801 is increased. The material of the first lower electrode 10 may be titanium nitride, titanium, tungsten, ruthenium, tantalum nitride, tungsten nitride, etc., but the disclosed embodiments are not limited thereto. For example, as shown in fig. 13, step S130 may include step S1301 and step S1302, wherein:
step S1301, forming a first electrode material layer on a side of the first dielectric layer away from the substrate, where the first electrode material layer fills each first electrode hole.
As shown in fig. 14, the first electrode material may be titanium nitride, titanium, tungsten, ruthenium, tantalum nitride, tungsten nitride, etc., but the embodiments of the present disclosure are not limited thereto. The first electrode material layer 9 may be formed by atomic layer deposition, but may also be formed by vapor deposition or the like. Wherein an air gap may be present at the portion of the first electrode material layer 9 located at the first electrode hole.
Step S1302, removing the first electrode material layer outside each first electrode hole to form a first lower electrode in each first electrode hole.
As shown in fig. 15, in an embodiment, the present disclosure removes portions of the first electrode material layer 9 located outside the respective first electrode holes 8 by etching to form the first lower electrodes 10. Wherein the etching may be dry etching. In another embodiment, the present disclosure removes portions of the first electrode material layer 9 located outside the respective first electrode holes 8 by grinding. Wherein the polishing may be chemical mechanical polishing.
In step S140, a second dielectric layer is formed on the side of the first dielectric layer away from the substrate.
For example, as shown in fig. 16, step S140 may include steps S1401 to S1402, in which:
step 1401, a second sacrificial layer is formed on the side of the first support layer far away from the substrate.
As shown in fig. 17, the second sacrificial layer 1102 may be prepared by vapor deposition, but the embodiments of the present disclosure are not limited thereto. The material of the second sacrificial layer 1102 may be the same as the material of the first sacrificial layer 302, for example, both materials are silicon oxide. In other embodiments of the present disclosure, the material of the second sacrificial layer 1102 may also be different from the material of the first sacrificial layer 302, and the present disclosure will not be described in detail herein.
Step S1402 is to form a second support layer on a side of the second sacrificial layer away from the substrate, where the second support layer and the second sacrificial layer form a second dielectric layer.
As shown in fig. 17, the second support layer 1101 may be prepared by vapor deposition, but the disclosed embodiments are not limited thereto. The material of the second support layer 1101 may be the same as the material of the first support layer 303, but may be different. For example, the material of the second support layer 1101 may be silicon nitride.
In step S150, a second electrode hole is formed on the second dielectric layer in a region corresponding to the first electrode hole.
As shown in fig. 18, the second electrode hole 12 penetrates the second support layer 1101 and the second sacrificial layer 1102. Wherein, the forming process of the second electrode hole 12 may include: sequentially forming a hard mask, an anti-reflection layer and a photoresist layer on one side of the second supporting layer 1101 far away from the preset dielectric layer 1; a pattern for forming the second electrode holes 12 is defined through processes of exposure, development, etc., and then the anti-reflection layer and the hard mask are etched using the photoresist layer as a mask, the pattern is transferred to the hard mask, and then the second dielectric layer 11 is etched using the hard mask as a mask, thereby forming a plurality of second electrode holes 12.
In step S160, a second lower electrode is formed in each second electrode hole, and the second lower electrode is in contact with the first lower electrode.
As shown in fig. 18 and 19, for a double-layer solid capacitor or a multilayer solid capacitor, the forming process of the second lower electrode 13 may include: forming a second electrode material layer on one side of the second sacrificial layer 1102 far away from the preset dielectric layer 1, wherein the second electrode material layer fills each second electrode hole 12; portions of the second electrode material layer outside the second electrode holes 12 are removed to form second lower electrodes 13 within the second electrode holes 12, the second lower electrodes 13 being in contact with the first lower electrodes 10. The second electrode material may be titanium nitride, titanium, tungsten, ruthenium, tantalum nitride, tungsten nitride, etc., but the disclosed embodiments are not limited thereto. The second electrode material layer may be formed by atomic layer deposition, or may be formed by vapor deposition or the like.
For a dual-layer hybrid capacitor (dual-layer hybrid capacitor) or a multi-layer hybrid capacitor (multi-layer hybrid capacitor), the forming of the second lower electrode may include: step S1601, as shown in fig. 20, forming a second electrode material layer 14, wherein the second electrode material layer 14 covers the second sacrificial layer 1102 and the inner surface of the second electrode hole 12; in step S1602, as shown in fig. 21, the second electrode material layer 14 is removed outside each second electrode hole 12 to form a second lower electrode 13 in each second electrode hole 12, and the second lower electrode 13 is in contact with the first lower electrode 10. The second electrode material may be titanium nitride, titanium, tungsten, ruthenium, tantalum nitride, tungsten nitride, etc., but the disclosed embodiments are not limited thereto. The second electrode material layer 14 may be formed by atomic layer deposition, but may also be formed by vapor deposition or the like. The thickness of the second electrode material layer 14 may be 5-15nm, such as 5nm, 7nm, 12nm, 15nm, etc.
In another embodiment, as shown in fig. 22, the method for manufacturing a capacitor structure may further include:
step S170, forming a second through hole on the second support layer, wherein the second through hole penetrates through the first support layer and the second support layer to expose the first sacrificial layer and the second sacrificial layer.
As shown in fig. 11, 23 and 24, the forming process of the second via hole 15 may include: forming a hard mask layer 4 on one side of the second support layer 1101 far away from the preset dielectric layer 1; defining a pattern for forming the second via hole 15 on the hard mask layer 4 by a patterning process; using the patterned hard mask layer 4 as a mask, the second support layer 1101, the second sacrificial layer 1102 and the first support layer 303 are etched to form a second via hole 15, so as to expose the first sacrificial layer 302 and the second sacrificial layer 1102.
And step S180, removing the second sacrificial layer and the first sacrificial layer.
As shown in fig. 23 to 26, the second sacrificial layer 1102 and the first sacrificial layer 302 may be removed by a wet process. In one embodiment, the isolation layer 301, the first support layer 303, and the second support layer 1101 are made of silicon nitride, and the second sacrificial layer 1102 and the first sacrificial layer 302 are made of silicon oxide, and the wet process includes: second sacrificial layer 1102 and first sacrificial layer 302 are removed by a hydrofluoric acid solution. In other embodiments of the present disclosure, the second sacrificial layer 1102 and the first sacrificial layer 302 may also be removed by other methods, which are not described in detail herein.
Step S190, depositing a third dielectric layer on the surface of the first lower electrode and the surface of the second lower electrode.
As shown in fig. 27 and 28, the third dielectric layer 16 may be prepared by atomic layer deposition, but the disclosure is not limited thereto. The material of the third dielectric layer 16 may include one or more of aluminum oxide, silicon nitride, silicon oxide, zirconium oxide, and hafnium oxide.
And S200, forming an upper electrode on the surface of the third dielectric layer.
As shown in fig. 29 and 30, the upper electrode 17 may be prepared by atomic layer deposition, but the disclosure is not limited thereto. The material of the upper electrode 17 may be titanium nitride, titanium, tungsten, ruthenium, tantalum nitride, tungsten nitride, or other materials.
Step S210 is to form a polysilicon layer on the surface of the upper electrode.
As shown in fig. 31 and 32, the polysilicon layer 18 may be prepared by atomic layer deposition, but the disclosure is not limited thereto. The material of the polysilicon layer 18 may be silane or disilane, and may be doped with one or more of arsenic, phosphorus, and germanium. The polysilicon layer 18 not only has conductive properties, but also stabilizes the columnar capacitance.
The disclosed embodiments also provide a capacitor structure. The capacitor structure is prepared by the preparation method of the capacitor structure according to any one of the above embodiments. As shown in fig. 31 to 33, the capacitor structure may include a substrate (not shown), a first lower electrode 10, and a second lower electrode 13, wherein:
the first lower electrode 10 is provided on a substrate. The first lower electrode 10 includes a main body portion 1001 and a first connection portion 1002 connected to each other along a direction perpendicular to the substrate. The first connection portion 1002 is located on a side of the main body portion 1001 away from the substrate, and a cross-sectional area of the first connection portion 1002 in a direction parallel to the substrate is larger than a cross-sectional area of the main body portion 1001 in the direction parallel to the substrate. The second lower electrode 13 is disposed on a side of the first lower electrode 10 away from the substrate, and is in contact with the first connection portion 1002.
The capacitor structure of the embodiment of the present disclosure is prepared by the method for preparing the capacitor structure according to any one of the above embodiments, and therefore, the same advantageous effects are obtained, and no further description is given here.
As shown in fig. 31 to 33, a predetermined dielectric layer 1 may be provided on the substrate of the present disclosure. In the embodiment of the present disclosure, the direction perpendicular to the substrate is a direction perpendicular to the predetermined dielectric layer 1, and the direction parallel to the substrate is a direction parallel to the predetermined dielectric layer 1. The first lower electrode 10 may be disposed on the predetermined dielectric layer 1. The predetermined dielectric layer 1 may be provided with a conductive plug 2. The first lower electrode 10 may further include a second connection portion 1003 in a direction perpendicular to the substrate. The second connecting portion 1003 is connected to a side of the main body portion 1001 away from the first connecting portion 1002, and a cross-sectional area of the second connecting portion 1003 in a direction parallel to the substrate is larger than a cross-sectional area of the main body portion 1001 in the direction parallel to the substrate. The second connection portion 1003 is in contact with the conductive plug 2. In addition, the capacitor structure of the disclosed embodiment further includes a third dielectric layer 16 and an upper electrode 17. The third dielectric layer 16 covers the surface of the first bottom electrode 10 and the surface of the second bottom electrode 13, and the top electrode 17 is disposed on the surface of the third dielectric layer 16.
The embodiment of the disclosure also provides a storage unit. The memory cell may include the capacitor structure described in any of the above embodiments. The storage unit can be used for mobile phones, computers, cameras and other equipment. The capacitor structure of the memory cell in the embodiment of the present disclosure is the same as that of the capacitor in the embodiment of the capacitor structure, and therefore, the same advantageous effects are obtained, and are not described herein again.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
Claims (10)
1. A method of making a capacitor structure, comprising:
providing a substrate;
forming a first dielectric layer on the substrate;
forming a plurality of first electrode holes in the first dielectric layer, wherein each first electrode hole comprises a first hole section and a second hole section, the first hole sections and the second hole sections are distributed and communicated along the extending direction of the first electrode hole, the first hole sections are positioned on one sides, far away from the substrate, of the second hole sections, and the cross sections of the first hole sections are larger than those of the second hole sections;
filling a first lower electrode in each first electrode hole;
forming a second dielectric layer on one side of the first dielectric layer far away from the substrate;
forming a second electrode hole in a region corresponding to the first electrode hole on the second dielectric layer;
and forming a second lower electrode in each second electrode hole, wherein the second lower electrode is in contact with the first lower electrode.
2. The method of claim 1, wherein forming a first dielectric layer on the substrate comprises:
forming a preset dielectric layer on the substrate;
forming a first dielectric layer on one side of the preset dielectric layer far away from the substrate;
the preset dielectric layer is provided with a conductive plug, the first electrode holes are formed in the first dielectric layer and correspond to the regions of the conductive plug, each first electrode hole further comprises a third hole section, the third hole sections and the second hole sections are distributed and communicated along the extending direction of the first electrode hole, the third hole sections are located on one side, close to the substrate, of the second hole sections, and the cross sections of the third hole sections are larger than the cross sections of the second hole sections.
3. The method of claim 1, wherein forming a first dielectric layer on the substrate comprises:
forming an isolation layer on the substrate;
forming a first sacrificial layer on one side of the isolation layer, which is far away from the substrate;
forming a first support layer on one side of the first sacrificial layer, which is far away from the substrate, wherein the isolation layer, the first sacrificial layer and the first support layer form a first dielectric layer;
forming a plurality of first electrode holes on the first dielectric layer includes:
patterning the first dielectric layer to form a plurality of first through holes on the first dielectric layer;
etching the first dielectric layer to enable the first through hole to form a first electrode hole, wherein the etching rate of the first sacrificial layer is smaller than that of the first support layer;
the first electrode hole is located on the first support layer and is the first hole section, and the first electrode hole is located on the first sacrificial layer and is the second hole section.
4. The method of claim 3, wherein the first sacrificial layer is silicon oxide and the first support layer is silicon nitride.
5. The method of claim 4, wherein etching the first dielectric layer comprises:
and etching the first dielectric layer by using phosphoric acid.
6. The method of claim 3, wherein forming an isolation layer on the substrate comprises:
forming a preset dielectric layer on the substrate;
forming an isolation layer on one side of the preset dielectric layer, which is far away from the substrate;
the preset dielectric layer is provided with a conductive plug, the first electrode hole is formed in a region, corresponding to the conductive plug, on the first dielectric layer, the etching rate of the first sacrificial layer is smaller than that of the isolation layer, the part, located on the isolation layer, of the first electrode hole is a third hole section, and the cross section of the third hole section is larger than that of the second hole section.
7. The method of claim 3, wherein forming a second dielectric layer on a side of the first dielectric layer away from the substrate comprises:
forming a second sacrificial layer on one side of the first support layer far away from the substrate;
forming a second supporting layer on one side, far away from the first supporting layer, of the second sacrificial layer, wherein the second supporting layer and the second sacrificial layer form a second dielectric layer;
the preparation method of the capacitor structure further comprises the following steps:
forming a second via hole on the second support layer, the second via hole penetrating through the first support layer and the second support layer to expose the first sacrificial layer and the second sacrificial layer;
removing the second sacrificial layer and the first sacrificial layer;
depositing a third dielectric layer on the surface of the first lower electrode and the surface of the second lower electrode;
and forming an upper electrode on the surface of the third dielectric layer.
8. A capacitor structure, comprising:
a substrate;
the first lower electrode is arranged on the substrate and comprises a main body part and a first connecting part which are connected with each other along the direction vertical to the substrate, the first connecting part is positioned on one side of the main body part away from the substrate, and the cross-sectional area of the first connecting part in the direction parallel to the substrate is larger than that of the main body part in the direction parallel to the substrate;
and the second lower electrode is arranged on one side of the first lower electrode, which is far away from the substrate, and is in contact with the first connecting part.
9. The capacitor structure of claim 8, further comprising:
the preset dielectric layer is arranged on the substrate and provided with a conductive plug;
the first lower electrode is arranged on the preset dielectric layer and further comprises a second connecting portion along the direction perpendicular to the substrate, the second connecting portion is connected to one side, away from the first connecting portion, of the main body portion, the cross-sectional area of the second connecting portion in the direction parallel to the substrate is larger than that of the main body portion in the direction parallel to the substrate, and the second connecting portion is in contact with the conductive plug.
10. A memory cell comprising the capacitor structure of any one of claims 8-9.
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040072086A (en) * | 2003-02-08 | 2004-08-18 | 삼성전자주식회사 | Method for fabricating cell capacitor of DRAM |
| US20040175884A1 (en) * | 2003-03-05 | 2004-09-09 | Kang Jae Il | Method for fabricating capacitor in semiconductor device |
| CN1612348A (en) * | 2003-08-18 | 2005-05-04 | 三星电子株式会社 | Semiconductor device and manufacturing method |
| KR20070120245A (en) * | 2006-06-19 | 2007-12-24 | 삼성전자주식회사 | How to Form Capacitors in Semiconductor Devices |
| CN103155098A (en) * | 2010-10-05 | 2013-06-12 | 国际商业机器公司 | 3D via capacitor with a floating conductive plate for improved reliability |
| CN103489831A (en) * | 2012-06-11 | 2014-01-01 | 爱思开海力士有限公司 | Semiconductor device with multi-layered storage node and method for fabricating the same |
| CN209087833U (en) * | 2018-11-26 | 2019-07-09 | 长鑫存储技术有限公司 | Array of capacitors structure and semiconductor memory comprising it |
| CN210296415U (en) * | 2019-10-11 | 2020-04-10 | 长鑫存储技术有限公司 | Memory cell and capacitor structure |
-
2019
- 2019-10-11 CN CN201910961668.5A patent/CN112652715A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040072086A (en) * | 2003-02-08 | 2004-08-18 | 삼성전자주식회사 | Method for fabricating cell capacitor of DRAM |
| US20040175884A1 (en) * | 2003-03-05 | 2004-09-09 | Kang Jae Il | Method for fabricating capacitor in semiconductor device |
| CN1612348A (en) * | 2003-08-18 | 2005-05-04 | 三星电子株式会社 | Semiconductor device and manufacturing method |
| KR20070120245A (en) * | 2006-06-19 | 2007-12-24 | 삼성전자주식회사 | How to Form Capacitors in Semiconductor Devices |
| CN103155098A (en) * | 2010-10-05 | 2013-06-12 | 国际商业机器公司 | 3D via capacitor with a floating conductive plate for improved reliability |
| CN103489831A (en) * | 2012-06-11 | 2014-01-01 | 爱思开海力士有限公司 | Semiconductor device with multi-layered storage node and method for fabricating the same |
| CN209087833U (en) * | 2018-11-26 | 2019-07-09 | 长鑫存储技术有限公司 | Array of capacitors structure and semiconductor memory comprising it |
| CN210296415U (en) * | 2019-10-11 | 2020-04-10 | 长鑫存储技术有限公司 | Memory cell and capacitor structure |
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