CN110970403B - Capacitor array structure and forming method thereof, and semiconductor device - Google Patents
Capacitor array structure and forming method thereof, and semiconductor device Download PDFInfo
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- CN110970403B CN110970403B CN201811151407.9A CN201811151407A CN110970403B CN 110970403 B CN110970403 B CN 110970403B CN 201811151407 A CN201811151407 A CN 201811151407A CN 110970403 B CN110970403 B CN 110970403B
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- 239000003990 capacitor Substances 0.000 title claims abstract description 167
- 238000000034 method Methods 0.000 title claims abstract description 60
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 230000002093 peripheral effect Effects 0.000 claims abstract description 56
- 239000000758 substrate Substances 0.000 claims description 113
- 238000002955 isolation Methods 0.000 claims description 52
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 8
- 239000000463 material Substances 0.000 abstract description 16
- 230000008021 deposition Effects 0.000 abstract description 7
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 238000005137 deposition process Methods 0.000 description 10
- 230000008569 process Effects 0.000 description 10
- 239000007772 electrode material Substances 0.000 description 8
- 238000000151 deposition Methods 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005019 vapor deposition process Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
本发明提供一种电容器阵列结构及其形成方法、半导体器件，通过在器件区上形成有一周边包裹式的主体支撑层，获得平整的电容阵列边界，避免后续沉积填充材料时由于电容阵列边界处不平整而形成裂缝，进而避免裂缝造成的插塞与电容阵列边界间的短路问题，在增加阵列区域的稳定性的同时提高了电容器件的可靠性。
The present invention provides a capacitor array structure and a method for forming the same, as well as a semiconductor device. A peripheral wrapping main body support layer is formed on a device region to obtain a flat capacitor array boundary, thereby avoiding the formation of cracks due to uneven capacitor array boundaries during subsequent deposition of filling materials, thereby avoiding the short circuit problem between a plug and the capacitor array boundary caused by the cracks, thereby increasing the stability of the array region and improving the reliability of the capacitor device.
Description
Technical Field
The present invention relates to semiconductor devices and fabrication, and more particularly, to a capacitor array structure and a method for forming the same.
Background
With the continued development of semiconductor technology, the performance requirements of capacitors in semiconductor integrated circuits are increasing, for example, it is desirable that capacitors formed in a limited area have a greater capacitance. One solution is to increase the contact area between the bottom electrode and the capacitive dielectric layer by increasing the height of the bottom electrode in the capacitor, thereby providing the resulting capacitor with a larger capacitance.
However, as the height of the lower electrode increases, the aspect ratio of the lower electrode also increases, which is very likely to cause bending deformation or collapse of the lower electrode, and affects the reliability of the array region. At present, the stability is increased by adding a transverse continuous supporting layer of the electrode, but the continuous supporting layer can form an uneven capacitor array boundary, and cracks are easily formed at the capacitor array boundary when filling materials are deposited later, so that the plugs and the capacitor array boundary are short-circuited. Therefore, protection of the capacitor array boundary is necessary.
Disclosure of Invention
The invention aims to provide a capacitor array structure, a forming method thereof and a semiconductor device, which avoid the problem of short circuit caused by crack formation at the boundary of a capacitor array when filling materials are deposited, thereby improving the reliability of the capacitor.
The invention provides a method for forming a capacitor array structure, which comprises the following steps:
Providing a substrate, wherein the substrate is provided with a device region for forming a capacitor and a peripheral region positioned at the periphery of the device region;
forming a sacrificial layer and a main body supporting layer in the device region, wherein the main body supporting layer comprises a transverse supporting layer and a longitudinal supporting layer, the transverse supporting layer covers the upper surface of the sacrificial layer, the longitudinal supporting layer covers the side surface, close to the peripheral region, of the sacrificial layer, and the longitudinal supporting layer is connected with the transverse supporting layer and the substrate;
forming a plurality of through holes in the device region, wherein the through holes sequentially penetrate through the transverse supporting layer and the sacrificial layer to expose the substrate;
Forming a lower electrode, wherein the lower electrode covers the side wall and the bottom of the through hole to form a plurality of cylindrical structures;
And removing the sacrificial layer, and sequentially forming a capacitance dielectric layer and an upper electrode on the inner surface and the outer surface of the lower electrode to form a capacitor.
Preferably, at least one lower support layer is formed between the lateral support layer and the substrate, the lower support layer is parallel to the lateral support layer, and one end of the lower support layer is connected with the longitudinal support layer.
Preferably, the forming method of the lower support layer includes:
forming a lower laminated structure in which a sacrificial layer and a lower supporting layer are alternately arranged on the substrate;
Forming a main body supporting layer, wherein the transverse supporting layer covers the upper surface of the lower laminated structure, and the longitudinal supporting layer covers the side surface, close to the peripheral area, of the lower laminated structure;
forming a plurality of through holes which sequentially penetrate through the transverse supporting layer and the lower laminated structure and expose the substrate;
Forming a lower electrode, wherein the lower electrode covers the side wall and the bottom of the through hole to form a plurality of cylindrical structures;
And removing the sacrificial layer, wherein the transverse supporting layer and the lower supporting layer are connected with the outer wall of the lower electrode cylindrical structure.
Preferably, the lateral support layer has at least one upper support layer formed thereon, the upper support layer being parallel to the lateral support layer, and one end of the upper support layer being flush with the longitudinal support layer in a direction perpendicular to the substrate.
Preferably, the forming method of the upper support layer includes:
Forming an upper laminated structure in which a sacrificial layer and an upper supporting layer are alternately arranged on the transverse supporting layer;
Forming a plurality of through holes which sequentially penetrate through the upper laminated structure, the transverse supporting layer and the sacrificial layer to expose the substrate;
Forming a lower electrode, wherein the lower electrode covers the side wall and the bottom of the through hole to form a plurality of cylindrical structures, and the lower electrode also covers the side surface of the longitudinal supporting layer close to the peripheral area and the side surface of the upper laminated structure close to the peripheral area;
And removing the sacrificial layer, wherein the upper supporting layer and the transverse supporting layer are connected with the outer wall of the lower electrode cylindrical structure.
Preferably, at least one lower supporting layer is formed between the transverse supporting layer and the substrate, and at least one upper supporting layer is formed on the transverse supporting layer, wherein the upper supporting layer and the lower supporting layer are parallel to the transverse supporting layer, one end of the lower supporting layer is connected with the longitudinal supporting layer, and one end of the upper supporting layer is kept flush with the longitudinal supporting layer in the direction perpendicular to the substrate.
Preferably, the forming method of the upper support layer and the lower support layer includes:
forming a lower laminated structure in which a sacrificial layer and a lower supporting layer are alternately arranged on the substrate;
Forming a main body supporting layer, wherein the transverse supporting layer covers the upper surface of the lower laminated structure, and the longitudinal supporting layer covers the side surface, close to the peripheral area, of the lower laminated structure;
Forming an upper laminated structure in which a sacrificial layer and an upper supporting layer are alternately arranged on the transverse supporting layer;
forming a plurality of through holes which sequentially penetrate through the upper laminated structure, the transverse supporting layer and the lower laminated structure to expose the substrate;
Forming a lower electrode, wherein the lower electrode covers the side wall and the bottom of the through hole to form a plurality of cylindrical structures, and the lower electrode also covers the side surface of the longitudinal supporting layer close to the peripheral area and the side surface of the upper laminated structure close to the peripheral area;
And removing the sacrificial layer, wherein the upper supporting layer and the transverse supporting layer are connected with the outer wall of the lower electrode cylindrical structure.
Preferably, the lower electrode further covers a side of the longitudinal support layer near the peripheral region and a side of the upper laminated structure near the peripheral region.
Preferably, an isolation layer is further formed between the sacrificial layer and the substrate, and the isolation layer is disposed at the periphery of the bottom of the lower electrode cylindrical structure.
Preferably, a plurality of node contacts are formed in the substrate, the through holes expose the node contacts, and the lower electrodes are connected with the node contacts at bottoms of the through holes.
Preferably, the main body supporting layer, the upper supporting layer, the lower supporting layer and the isolation layer are all made of silicon nitride.
Further, the present invention provides a capacitor array structure, comprising:
The capacitors are arranged in the substrate device area and distributed in an array mode, and each capacitor comprises a lower electrode, a capacitance medium layer and an upper electrode; the capacitive touch screen comprises a substrate, a lower electrode, a capacitive medium layer, an upper electrode, a capacitive medium layer and a conductive electrode, wherein the lower electrode is arranged on the substrate and is provided with a plurality of cylindrical structures;
The device comprises a device region, a main body supporting layer, a longitudinal supporting layer, a lower electrode and a lower electrode, wherein the main body supporting layer comprises a transverse supporting layer and a longitudinal supporting layer, the transverse supporting layer is arranged on the device region and connected with the outer wall of the lower electrode tubular structure, the longitudinal supporting layer is arranged at one end of the transverse supporting layer and connected with the transverse supporting layer and the substrate, and one side surface of the longitudinal supporting layer, which is different from the transverse supporting layer, is provided with the lower electrode.
Preferably, at least one lower supporting layer is arranged between the transverse supporting layer and the substrate, the lower supporting layer is connected with the outer wall of the lower electrode tubular structure, and one end of the lower supporting layer is connected with the longitudinal supporting layer.
Preferably, the transverse supporting layer is provided with at least one upper supporting layer, the upper supporting layer is connected with the outer wall of the lower electrode cylindrical structure, and one end of the upper supporting layer is kept flush with the longitudinal supporting layer in the direction perpendicular to the substrate.
Preferably, at least one lower support layer is disposed between the lateral support layer and the substrate, and at least one upper support layer is disposed on the lateral support layer.
Preferably, the lower support layer and the upper support layer are connected to the outer wall of the lower electrode cylindrical structure, one end of the lower support layer is connected to the longitudinal support layer, and one end of the upper support layer is kept flush with the longitudinal support layer in a direction perpendicular to the substrate.
Preferably, the lower electrode disposed on a side of the longitudinal support layer different from the lateral support layer is extended to connect with the upper support layer.
Preferably, the substrate is further provided with an isolation layer, the isolation layer is arranged on the periphery of the bottom of the lower electrode cylindrical structure, the capacitor array structure further comprises a plurality of node contacts, the node contacts are positioned in the substrate, and the bottom of the lower electrode cylindrical structure is connected with the node contacts.
Preferably, the main body supporting layer, the upper supporting layer and the lower supporting layer all comprise silicon nitride, and the sacrificial layer comprises silicon oxide.
Furthermore, the invention also provides a semiconductor device which comprises the capacitor array structure.
Preferably, the semiconductor device is applied to a dynamic random access memory.
In summary, in the method for forming a capacitor array structure provided by the invention, a peripheral wrapped main body supporting layer is formed on the device region, so as to obtain a flat capacitor array boundary, avoid forming cracks due to uneven capacitor array boundary during subsequent deposition of filling materials, further avoid the problem of short circuit between the plug and the capacitor array boundary caused by the cracks, and improve the reliability of the capacitor device while increasing the stability of the array region.
Drawings
FIG. 1 is a schematic cross-sectional view of a capacitor in the prior art during its fabrication;
FIG. 2 is a flow chart illustrating a method for forming a capacitor array structure according to an embodiment of the present invention;
Fig. 3 to 9 are schematic cross-sectional views corresponding to corresponding steps in a method for forming a capacitor array structure according to a first embodiment of the present invention;
fig. 10 to 15 are schematic cross-sectional views corresponding to corresponding steps in a method for forming a capacitor array structure according to a second embodiment of the present invention;
Fig. 16 to 20 are schematic cross-sectional views corresponding to corresponding steps in a method for forming a capacitor array structure according to a third embodiment of the present invention;
Fig. 21 to 23 are schematic cross-sectional views corresponding to corresponding steps in a method for forming a capacitor array structure according to a fourth embodiment of the present invention.
Wherein, the reference numerals are as follows:
10/100-substrate, 10A/100A-device region;
10B/100B-peripheral region, 100A-device region edge portion;
11-crack, 12-plug;
101-contact, 102-isolation layer;
103-sacrificial layer, 120-main body supporting layer;
104-a transverse support layer, 105-a longitudinal support layer;
130-through hole 106-lower electrode;
107-a capacitance dielectric layer, 108-an upper electrode;
109-upper electrode filling layer, 110-upper electrode connecting layer;
200-a lower laminate structure 201-a first lower support layer;
202-a second lower support layer 210-a first lower sacrificial layer;
220-a second lower sacrificial layer, 300-an upper lamination mechanism;
301-a first upper support layer, 302-a second upper support layer;
310-a first upper sacrificial layer 320-a second upper sacrificial layer;
Detailed Description
Fig. 1 is a schematic cross-sectional view of a capacitor in the prior art during the manufacturing process thereof, as shown in fig. 1, in the conventional capacitor forming process, after the process of completing the capacitor device in the device region (ARRAY AREA) 10A, a filling material layer is deposited, and because the boundary of the capacitor array in the device region 10A is uneven, cracks 11 (Crack) easily occur in the uneven area (shown by circles), and in the subsequent plug 12 (CT) forming process, both the dry etching and wet cleaning of the plug hole can aggravate the cracks, and then when filling metal, the metal also drills into the cracks, so that the plug and the capacitor array boundary or the plug and the plug directly short-circuit, thereby affecting the reliability of the capacitor device.
The invention provides a capacitor array structure, a forming method thereof and a semiconductor device, wherein a peripheral wrapping type supporting structure is formed in a device area to obtain a flat capacitor array boundary, so that cracks formed by uneven capacitor array boundaries during subsequent filling material deposition are avoided, the problem of short circuit between plugs and the capacitor array boundary caused by the cracks is further avoided, and the reliability of the capacitor device is improved while the stability of the array area is improved.
The capacitor array, the method for forming the capacitor array and the semiconductor device according to the present invention are described in further detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
Example 1
Fig. 2 is a flow chart of a method for forming a capacitor array structure according to an embodiment of the present invention, and as shown in fig. 2, the method for forming a capacitor array structure provided by the present invention includes:
s01, providing a substrate, wherein the substrate is provided with a device region for forming a capacitor and a peripheral region positioned at the periphery of the device region;
s02, forming a sacrificial layer and a main body supporting layer in the device region, wherein the main body supporting layer comprises a transverse supporting layer and a longitudinal supporting layer, the transverse supporting layer covers the upper surface of the sacrificial layer, the longitudinal supporting layer covers the side surface, close to the peripheral region, of the sacrificial layer, and the longitudinal supporting layer is connected with the transverse supporting layer and the substrate;
S03, forming a plurality of through holes in the device region, wherein the through holes sequentially penetrate through the transverse supporting layer and the sacrificial layer to expose the substrate;
s04, forming a lower electrode, wherein the lower electrode covers the side wall and the bottom of the through hole to form a plurality of cylindrical structures;
and S05, removing the sacrificial layer, and sequentially forming a capacitance dielectric layer and an upper electrode on the inner surface and the outer surface of the lower electrode to form a capacitor.
Fig. 3 to 9 are schematic cross-sectional views corresponding to corresponding steps in a method for forming a capacitor array structure according to an embodiment of the invention. The method for forming the capacitor array in this embodiment is further explained below in conjunction with the corresponding structural schematic diagrams of the respective steps.
In step S01, referring to fig. 3, a substrate 100 is provided, wherein the substrate 100 includes a device region 100A for forming a capacitor and a peripheral region 100B located at the periphery of the device region 100A, and the device region 100A is isolated from the peripheral region 100B by a trench isolation structure. In the following schematic cross-sectional structure of the capacitor array, only a portion of the capacitor device region 100A is shown.
The substrate 100 may be made of monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium compound, silicon On Insulator (SOI), or the like, or other materials known to those skilled in the art, and a plurality of node contacts 101 are formed in the substrate 100, and the node contacts 101 are electrically connected to the lower electrodes of the capacitors to be formed later. Of course, other device structures such as an isolation structure may be formed in the substrate 100, which is not limited in the present invention.
In step S02, first, referring to fig. 3, an isolation layer 102 and a sacrificial layer 103 are sequentially formed on the substrate 100. Then, referring to fig. 4, a mask layer (not shown) is formed on the sacrificial layer 102, the mask layer is patterned, the patterned mask layer covers the region of the device region 100A where the capacitor array is formed, the peripheral region 100B and the edge portion 100A' of the device region 100A connected to the peripheral region 100B are exposed, and then the sacrificial layer 103 is etched with the patterned mask layer as a mask until the isolation layer 102 is exposed, and the patterned mask layer is removed.
Next, referring to fig. 5, a body supporting layer 120 is formed on the sacrificial layer 102, the body supporting layer 120 includes a lateral supporting layer 104 and a longitudinal supporting layer 105, the lateral supporting layer 104 covers the upper surface of the sacrificial layer 103, the longitudinal supporting layer 105 covers a side surface of the sacrificial layer 103 and the isolation layer 102 on the device region edge portion 100A', the side surface is a surface of the longitudinal supporting layer 105 close to the peripheral region 100B, and the longitudinal supporting layer 105 connects the lateral supporting layer 104 and the isolation layer 102.
The material of the body support layer 120 and the isolation layer 102 may include, but is not limited to, silicon nitride, and the material of the sacrificial layer may include, but is not limited to, silicon oxide, and the body support layer 120 and the sacrificial layer 103 may be formed by a deposition process, such as a chemical vapor deposition process. The body support layer 120 may be formed in a one-step deposition process, or the lateral support layer 104 and the longitudinal support layer 105 may be formed in a two-step deposition process, respectively. Preferably, in this embodiment, the body support layer 120 may be formed in a one-step deposition process. The thickness of the sacrificial layer 103 defines the height of the lateral support layer 104 to be formed later, and thus, the thickness of the sacrificial layer 103 can be adjusted according to the height position of the lateral support layer 104 to be formed.
In step S03, referring to fig. 6, a plurality of through holes 130 are formed in the device region 100A, and the through holes 130 sequentially penetrate through the lateral support layer 104, the sacrificial layer 103 and the isolation layer 102 to expose the substrate 100.
Specifically, a mask layer is formed on the lateral support layer 104, the mask layer is patterned to expose a region where a through hole is formed, then the patterned mask layer is used as a mask to sequentially etch the lateral support layer 104, the sacrificial layer 103 and the isolation layer 102, so as to form a plurality of through holes 130, and then the patterned mask layer is removed. The through holes 130 expose the node contacts 101, and optionally, the through holes 130 are arranged in a hexagonal shape. It will be appreciated that by forming the through hole 130 in the lateral support layer 104 and the sacrificial layer 103, a lower electrode having a cylindrical structure may be formed at the bottom and the sidewall of the through hole 130, and thus, the total height of the lateral support layer 104 and the sacrificial layer 103 may define the height of the cylindrical structure in the lower electrode formed later, and thus, the height of the capacitor formed later may be increased by increasing the thickness of the sacrificial layer 103, so that the electrode surface area of the capacitor may be increased, and thus, the capacitance value of the formed capacitor may be increased.
In step S04, referring to fig. 7, a lower electrode 106 is formed in the through hole 130, and the lower electrode 106 covers the sidewall and the bottom of the through hole 130 to form a plurality of cylindrical structures.
The shape of the portion of the lower electrode 106 located in the through hole 130 is consistent with the shape of the through hole 130, so that the portion of the lower electrode 106 located in the through hole 130 forms a cylindrical structure. Further, the lower electrode 106 may be a polysilicon electrode or a metal electrode. When the lower electrode 106 is a metal electrode, it may be formed using titanium nitride (TiN), for example.
Specifically, the lower electrode 106 may be formed in conjunction with a planarization process on the basis of a deposition process, for example, first, an electrode material layer is formed on the substrate 100, the electrode material layer covering the bottom and the sidewalls of the via hole 130 and covering the lateral support layer 104, and then, a planarization process (for example, a chemical mechanical polishing process) is performed to remove a portion of the electrode material layer above the lateral support layer 104, so that the remaining electrode material layer is formed only in the via hole 130 to form a lower electrode of a cylindrical structure.
Preferably, the lower electrode 106 is also formed on the side of the longitudinal support layer 104 near the peripheral region 100B and the isolation layer on the device region edge portion 100A'.
Further, in the present embodiment, the node contact 101 is exposed through the through hole 130, so that the bottom of the cylindrical structure of the formed lower electrode 106 can be electrically connected to the node contact 101.
In step S05, referring to fig. 8 to 9, the sacrificial layer 103 is removed, and a capacitor dielectric layer 107 and an upper electrode 108 are sequentially formed on the inner and outer surfaces of the lower electrode 106 to form a capacitor.
Specifically, first, a first opening is formed in the lateral support layer 104 and exposes the sacrificial layer 103, and the sacrificial layer 103 is etched to form a structure as shown in fig. 8. Wherein one of the first openings overlaps only one of the through holes 130, or one of the first openings overlaps a plurality of the through holes 130 at the same time. After the sacrificial layer 103 is removed, the lateral support layer 104 is connected to the outer wall of the cylindrical structure of the lower electrode 106, and the longitudinal support layer 105 is connected to the lateral support layer 104 and the isolation layer 102, so that a peripheral wrapping support structure is formed on the device region 100A.
Then, referring to fig. 9, a capacitor dielectric layer 107 is formed on the inner and outer surfaces of the bottom electrode 106 and the exposed surface of the lateral support layer 104. The capacitor dielectric layer 107 covers the inner surface of the cylindrical structure of the lower electrode 106, which is located inside the cylinder, and the outer surface of the cylindrical structure, which is located outside the cylinder, so as to make full use of the two opposite surfaces of the lower electrode 106, thereby forming an integrated circuit capacitor with a larger electrode surface area. Specifically, the capacitive dielectric layer 107 may be formed by a vapor deposition process. Preferably, the capacitor dielectric layer 107 may be a high-K dielectric layer. Further, the capacitance dielectric layer 107 has a multi-layer structure, for example, a two-layer structure of a silicon oxide layer/a silicon nitride layer, and the silicon oxide layer and the silicon nitride layer may be sequentially formed when the capacitance dielectric layer 107 is formed.
Further, in the present embodiment, the bottom of the cylindrical outer portion of the cylindrical structure of the lower electrode 106 is connected to the node contact 101 formed in the device region 100A, and the outer wall of the cylindrical structure of the lower electrode 106 is connected to the lateral support layer 104 and the isolation layer 102, so that the capacitance medium layer 107 does not cover the portion of the cylindrical bottom of the lower electrode 106 and does not cover the portion of the outer wall of the cylindrical structure of the lower electrode 106 to which the lateral support layer 104 is connected.
Next, as shown in fig. 9, an upper electrode 108 is formed on the inner surface and the outer surface of the capacitor dielectric layer 107. The upper electrode 108 can form a capacitance with the capacitance medium layer 106 and the lower electrode 106 at the inside of the cylindrical structure and the outside of the cylindrical structure.
Finally, as shown in fig. 9, an electrode filling layer 109 and an electrode connecting layer 110 are sequentially formed on the upper electrode 108. The upper electrode filling layer 109 covers the upper electrodes 108 and fills the gaps between the upper electrodes 108, the upper electrode filling layer 109 is made of boron doped polysilicon, the upper electrode connecting layer 110 covers the outer surface of the upper electrode filling layer 109, and the upper electrode connecting layer 110 is made of tungsten.
In the method for forming the capacitor array structure provided by the embodiment of the invention, the main body supporting layer with a wrapped periphery is formed on the device region, compared with the single transverse supporting layer in the prior art, the capacitor array boundary is of a flat structure, so that cracks are prevented from being formed due to uneven positions of the capacitor array boundary during subsequent deposition of filling materials, the problem of short circuit between a plug and the capacitor array boundary caused by the cracks is further avoided, and the reliability of a capacitor device is improved while the stability of the array region is improved.
Example two
In comparison with the first embodiment, the present embodiment forms at least one lower support layer between the lateral support layer 104 of the main support layer and the isolation layer 102, the lower support layer is parallel to the lateral support layer 104, and one end of the lower support layer is connected to the longitudinal support layer 104. The specific forming steps comprise:
S11, forming a lower laminated structure with a sacrificial layer and a lower supporting layer alternately arranged on the substrate;
S12, forming a main body supporting layer, wherein the transverse supporting layer covers the upper surface of the lower laminated structure, and the longitudinal supporting layer covers the side surface, close to the peripheral area, of the lower laminated structure;
s13, forming a plurality of through holes, wherein the through holes sequentially penetrate through the transverse supporting layer, the lower laminated structure and the substrate;
S14, forming a lower electrode, wherein the lower electrode covers the side wall and the bottom of the through hole to form a plurality of cylindrical structures;
and S15, removing the sacrificial layer, wherein the transverse supporting layer and the lower supporting layer are connected with the outer wall of the lower electrode cylindrical structure.
Fig. 10 to 15 are schematic cross-sectional views corresponding to corresponding steps in a method for forming a capacitor array structure according to a second embodiment of the present invention. In step S11, referring to fig. 10, a first lower sacrificial layer 210, a first lower supporting layer 201 and a second lower sacrificial layer 220 are sequentially formed on the substrate 100 to form a lower laminated structure 200 with alternately arranged sacrificial layers and lower supporting layers. Preferably, an isolation layer 102 is further formed between the first lower sacrificial layer 210 and the substrate 100, for isolating the memory transistor and the capacitor device above the memory transistor in the substrate 100.
In step S12, referring to fig. 11, a main body supporting layer 120 is formed, the lateral supporting layer 104 covers the upper surface of the lower stacked structure 200, and the longitudinal supporting layer 105 covers the side surface of the lower stacked structure 200 near the peripheral region 100B.
First, a mask layer (not shown) is formed on the second lower sacrificial layer 220, the mask layer is patterned, the patterned mask layer covers the area of the device area 100A where the capacitor array is formed, the peripheral area 100B and the edge portion 100A' of the device area 100A connected to the peripheral area 100B are exposed, then the patterned mask layer is used as a mask to etch the second lower sacrificial layer 220, the first lower supporting layer 201 and the first lower sacrificial layer 210 in sequence until the isolation layer 102 is exposed, and the patterned mask layer is removed.
Next, a body support layer 120 is formed on the second lower sacrificial layer 220, the body support layer 120 includes a lateral support layer 104 and a longitudinal support layer 105, the lateral support layer 104 covers the upper surface of the second lower sacrificial layer 220, the longitudinal support layer 105 covers a side of the lower stacked structure 200 and the isolation layer 102 on the device region edge portion 100A', the side is a side of the longitudinal support layer 105 near the peripheral region 100B, and the longitudinal support layer 105 connects the lateral support layer 104 and the isolation layer 102.
The material of the body support layer 120 and the isolation layer 102 may include, but is not limited to, silicon nitride, and the material of the sacrificial layer may include, but is not limited to, silicon oxide, and the body support layer 120 and the sacrificial layer may be formed by a deposition process, such as a chemical vapor deposition process. The thickness of the first lower sacrificial layer 210 defines the height of the first lower support layer 201 to be formed later, and thus, the thickness of the first lower sacrificial layer 210 can be adjusted according to the height position of the first lower support layer 201 to be formed. The thickness of the second lower sacrificial layer 220 defines the height of the subsequently formed lateral support layer 105, and thus, the thickness of the second lower sacrificial layer 220 may be adjusted according to the desired height position of the formed lateral support layer 105.
In step S13, referring to fig. 12, a plurality of through holes 130 are formed, and the through holes 130 sequentially penetrate through the lateral support layer 104 and the lower stacked structure 200 to expose the substrate 100.
Specifically, a mask layer is formed on the lateral support layer 104, the mask layer is patterned to expose a region where a through hole is predetermined to be formed, then the patterned mask layer is used as a mask to sequentially etch the lateral support layer 104, the second lower sacrificial layer 220, the first lower support layer 201, the first lower sacrificial layer 210 and the isolation layer 102, so as to form a plurality of through holes 130, and then the patterned mask layer is removed. The through holes 130 expose the node contacts 101, and optionally, the through holes 130 are arranged in a hexagonal shape. It will be appreciated that by forming the via hole 130 in the lateral support layer 104 and the lower stacked structure 200, a lower electrode having a cylindrical structure may be formed at the bottom and the sidewall of the via hole 130, and thus, the total height of the lateral support layer 104 and the lower stacked structure 200 may define the height of the cylindrical structure in the lower electrode to be formed later, and thus, the height of the capacitor to be formed later may be increased by increasing the thicknesses of the first lower sacrificial layer 210 and the second lower sacrificial layer 220, and thus, the electrode surface area of the capacitor may be increased, and thus, the capacitance value of the capacitor to be formed may be increased.
In step S14, as shown in fig. 12, a lower electrode 106 is formed in the through hole 130, and the lower electrode 106 covers the sidewall and the bottom of the through hole 130 to form a plurality of cylindrical structures.
The shape of the portion of the lower electrode 106 located in the through hole 130 is consistent with the shape of the through hole 130, so that the portion of the lower electrode 106 located in the through hole 130 forms a cylindrical structure. Further, the lower electrode 106 may be a polysilicon electrode or a metal electrode. When the lower electrode 106 is a metal electrode, it may be formed using titanium nitride (TiN), for example.
Specifically, the lower electrode 106 may be formed in conjunction with a planarization process on the basis of a deposition process, for example, first, an electrode material layer is formed on the substrate 100, the electrode material layer covering the bottom and the sidewalls of the via hole 130 and covering the lateral support layer 104, and then, a planarization process (for example, a chemical mechanical polishing process) is performed to remove a portion of the electrode material layer above the lateral support layer 104, so that the remaining electrode material layer is formed only in the via hole 130 to form a lower electrode of a cylindrical structure.
Preferably, the lower electrode 106 is also formed on the side of the longitudinal support layer 105 near the peripheral region 100B and the isolation layer on the device region edge portion 100A'.
Further, in the present embodiment, the node contact 101 is exposed through the through hole 130, so that the bottom of the cylindrical structure of the formed lower electrode 106 can be electrically connected to the node contact 101.
In step S15, referring to fig. 13, the sacrificial layer is removed, and the lateral support layer 104 and the first lower support layer 201 are connected to the outer wall of the cylindrical structure of the lower electrode 106.
Specifically, first, a first opening is formed in the lateral support layer 104 and exposes the second lower sacrificial layer 220, the second lower sacrificial layer 220 is etched and removed, a second opening is formed in the first lower support layer 201 and exposes the first lower sacrificial layer 210, the first lower sacrificial layer 210 is etched and removed, one of the first openings overlaps only one of the through holes 130 or one of the first openings overlaps a plurality of the through holes 130 at the same time, and one of the second openings overlaps only one of the through holes 130 or one of the second openings overlaps a plurality of the through holes 130 at the same time. After the sacrificial layer 103 is removed, the lateral support layer 104 and the first lower support layer 201 are connected to the outer wall of the cylindrical structure of the lower electrode 106, and the longitudinal support layer 105 is connected to the lateral support layer 104 and the first lower support layer 201 and the isolation layer 102, so that a peripheral wrapping support structure is formed on the device region 100A.
Then, as shown in fig. 14, a capacitor dielectric layer 107 and an upper electrode 108 are sequentially formed on the inner and outer surfaces of the lower electrode 106 to form a capacitor. Finally, an electrode filling layer 109 and an electrode connecting layer 110 are sequentially formed on the upper electrode 108. The specific forming method and the first embodiment are described.
In addition, a plurality of lower support layers 200 may be formed between the lateral support layer 104 and the isolation layer 102, as shown in fig. 15, and a first lower support layer 201 and a second lower support layer 202 may be formed between the lateral support layer 104 and the isolation layer 102, and the specific forming method is not described again.
Example III
In comparison with the first embodiment, the embodiment forms at least one upper support layer on the lateral support layer 104 of the main support layer, the upper support layer is parallel to the lateral support layer 104, and one end of the upper support layer is level with the longitudinal support layer 104 in the direction perpendicular to the substrate. The specific forming steps comprise:
S21, forming an upper laminated structure with a sacrificial layer and an upper supporting layer alternately arranged on the transverse supporting layer;
S22, forming a plurality of through holes, wherein the through holes sequentially penetrate through the upper laminated structure, the transverse supporting layer and the sacrificial layer to expose the substrate;
S23, forming a lower electrode, wherein the lower electrode covers the side wall and the bottom of the through hole to form a plurality of cylindrical structures, and the lower electrode also covers the side surface of the longitudinal supporting layer close to the peripheral area and the side surface of the upper laminated structure close to the peripheral area;
And S24, removing the sacrificial layer, wherein the upper supporting layer and the transverse supporting layer are connected with the outer wall of the lower electrode cylindrical structure.
Fig. 16 to 20 are schematic cross-sectional views corresponding to corresponding steps in a method for forming a capacitor array structure according to a third embodiment of the present invention. In step S21, please refer to fig. 16, first, referring to steps S01-S02 in the first embodiment, the lateral main body supporting layer 120 is formed. Then, a first upper sacrificial layer 310 and a first upper support layer 301 are sequentially formed on the lateral support layer 104, constituting an upper laminated structure 300.
In step S21, referring to fig. 17, a plurality of through holes 130 are formed, and the through holes 130 sequentially penetrate through the upper stacked structure 300, the lateral support layer 104 and the sacrificial layer 103 to expose the substrate 100.
Specifically, a mask layer is formed on the first upper supporting layer 301, the mask layer is patterned to expose a region where a through hole is predetermined to be formed, then the patterned mask layer is used as a mask to sequentially etch the first upper supporting layer 301, the first upper sacrificial layer 310, the lateral supporting layer 104, the sacrificial layer 103 and the isolation layer 102, so as to form a plurality of through holes 130, and then the patterned mask layer is removed. The through holes 130 expose the node contacts 101, and optionally, the through holes 130 are arranged in a hexagonal shape.
In step S23, as shown in fig. 17, a lower electrode 106 is formed, and covers the sidewall and the bottom of the through hole 130 to form a plurality of cylindrical structures. Preferably, the lower electrode 106 is also formed on the side of the longitudinal support layer 105 near the peripheral region 100B and the side of the upper stacked structure 300 near the peripheral region.
In step S23, referring to fig. 18, the sacrificial layer is removed, and the upper support layer 300 and the lateral support layer 104 are connected to the outer wall of the cylindrical structure of the lower electrode 106.
Specifically, first, a first opening is formed in the first upper supporting layer 301 and exposes the first upper sacrificial layer 310, the first upper sacrificial layer 310 is etched and removed, a second opening is formed in the lateral supporting layer 104 and exposes the sacrificial layer 103, and the sacrificial layer 103 is etched and removed, wherein one first opening is overlapped with only one through hole 130 or one first opening is overlapped with a plurality of through holes 130 at the same time, one second opening is overlapped with only one through hole 130 or one second opening is overlapped with a plurality of through holes 130 at the same time.
After the sacrificial layer is removed, the first upper support layer 301 and the lateral support layer 104 are connected to the outer wall of the cylindrical structure of the lower electrode 106, and the longitudinal support layer 105 is connected to the lateral support layer 104 and the isolation layer 102, so that a peripheral wrapped support structure is formed on the device region 100A. Further, in this embodiment, one end of the first upper supporting layer 301 and the longitudinal supporting layer 105 are kept flush in the direction perpendicular to the substrate, and the lower electrode 106 is formed on the side of the longitudinal supporting layer 105 close to the peripheral region 100B and extends to connect the first upper supporting layer 301 in the direction perpendicular to the substrate 100, so that the flatness of the capacitor array boundary is ensured, the crack formed due to the uneven capacitor array boundary during the subsequent deposition of the filling material is avoided, the problem of short circuit between the plug and the capacitor array boundary caused by the crack is further avoided, and the reliability of the capacitor device is improved while the stability of the array region is increased.
Then, as shown in fig. 19, a capacitor dielectric layer 107 and an upper electrode 108 are sequentially formed on the inner and outer surfaces of the lower electrode 106 to form a capacitor. Finally, an electrode filling layer 109 and an electrode connecting layer 110 are sequentially formed on the upper electrode 108. The specific forming method is shown in the first embodiment.
In addition, a plurality of upper support layers may be formed on the lateral support layer 104, as shown in fig. 20, and a first upper support layer 301 and a second upper support layer 302 may be formed on the lateral support layer 104, and a specific forming method is not described herein.
Example IV
In comparison with the first embodiment, in the present embodiment, at least one lower support layer is formed between the lateral support layer 104 of the main support layer 120 and the substrate 100, and at least one upper support layer is formed on the lateral support layer 105. The specific forming method comprises the following steps:
S31, forming a lower laminated structure 200 with a sacrificial layer and a lower supporting layer alternately arranged on the substrate 100;
S32, forming a main body supporting layer 120, wherein the lateral supporting layer 104 covers the upper surface of the lower laminated structure 200, and the longitudinal supporting layer 105 covers the side surface of the lower laminated structure 200 close to the peripheral area;
S33, forming an upper laminated structure 300 with a sacrificial layer and an upper supporting layer alternately arranged on the transverse supporting layer 104;
S34 forming a plurality of through holes 130 penetrating through the upper stacked structure 300, the lateral support layer 105 and the lower stacked structure 300 in order to expose the substrate 100;
S35, forming a lower electrode 106, wherein the lower electrode 106 covers the side wall and the bottom of the through hole 130 to form a plurality of cylindrical structures, and the lower electrode also covers the side surface of the longitudinal supporting layer close to the peripheral area and the side surface of the upper laminated structure close to the peripheral area;
And S36, removing the sacrificial layer, wherein the upper support layer, the transverse support layer 104 and the lower support layer 200 are connected with the outer wall of the lower electrode tubular structure.
Fig. 21 to 23 are schematic cross-sectional views corresponding to corresponding steps in a method for forming a capacitor array structure according to a fourth embodiment of the present invention. Please refer to fig. 21 in combination with the second embodiment of the present invention, step S31 and step S32 are performed. In step S31, a first lower sacrificial layer 210, a first lower supporting layer 201, and a second lower sacrificial layer 220 are sequentially formed on the substrate 100 to form a lower stacked structure 200 in which the sacrificial layers and the lower supporting layers are alternately arranged. Preferably, an isolation layer 102 is further formed between the first lower sacrificial layer 210 and the substrate 100, for isolating the memory transistor and the capacitor device above the memory transistor in the substrate 100.
In step S32, a body support layer 120 is formed, the lateral support layer 104 covers the upper surface of the lower stacked structure 210, and the longitudinal support layer 105 covers the side of the lower stacked structure 210 near the peripheral region 100B.
Please refer to fig. 21 and 22 in combination with the third embodiment of the present invention, steps S33 to S36 are performed. First, in step S33, a first upper sacrificial layer 310 and a first upper support layer 301 are sequentially formed on the lateral support layer 104 to form an upper laminated structure 300.
In step S34, a plurality of through holes 130 are formed, and the through holes 130 sequentially penetrate through the upper stacked structure 300, the lateral support layer 104, the lower stacked structure 200, and the isolation layer 102 to expose the substrate 100.
In step S35, a lower electrode 106 is formed, which covers the sidewall and the bottom of the through hole 130, to form a plurality of cylindrical structures. Preferably, a lower electrode 106 is also formed on the side of the longitudinal support layer 105 near the peripheral region 100B and the side of the upper stacked structure 300 near the peripheral region, and further, the lower electrode 106 also covers the isolation layer 102 on the device region edge portion 100A'.
In step S36, the sacrificial layer is removed, and the upper support layer, the lateral support layer 104, and the lower support layer are connected to the outer wall of the cylindrical structure of the lower electrode 106, as shown in fig. 22.
Then, a capacitor dielectric layer 107 and an upper electrode 108 are sequentially formed on the inner and outer surfaces of the lower electrode 106 to form a capacitor. Finally, an electrode filling layer 109 and an electrode connecting layer 110 are sequentially formed on the upper electrode 108.
In addition, a plurality of lower support layers may be formed between the lateral support layer 104 of the body support layer 120 and the substrate 100, and a plurality of upper support layers may be formed on the lateral support layer 104. As shown in fig. 23, a first lower support layer 201 and a second lower support layer 202 are formed between the lateral support layer 104 of the main support layer 120 and the substrate 100, and a first upper support layer 301 and a second upper support layer 302 are formed on the lateral support layer 104, and a specific forming method is not described herein.
Example five
The invention also provides a capacitor array structure as shown in FIG. 9, which comprises a plurality of capacitors arranged in a substrate device region and distributed in an array, wherein each capacitor comprises a lower electrode 106, a capacitance medium layer 107 and an upper electrode 108, wherein the lower electrode 106 is arranged on the substrate 100, and the lower electrode 106 is provided with a plurality of cylindrical structures, the capacitance medium layer 107 is arranged on the inner surface and the outer surface of the lower electrode 106, and the upper electrode 108 is arranged on the outer surface of the capacitance medium layer 107;
The main body support layer 120 comprises a transverse support layer 104 and a longitudinal support layer 105, wherein the transverse support layer 104 is arranged on the device region 100A, the transverse support layer 104 is connected with the outer wall of the cylindrical structure of the lower electrode 106, the longitudinal support layer 105 is arranged at one end of the transverse support layer 104, the longitudinal support layer 105 is connected with the transverse support layer 104 and the substrate 100, and the lower electrode 106 is arranged on one side surface of the longitudinal support layer 105 different from the transverse support layer 104.
Preferably, as shown in fig. 14, at least one lower support layer (a first lower support layer 201) is disposed between the lateral support layer 104 and the substrate 100, the lower support layer is connected to the outer wall of the cylindrical structure of the lower electrode 106, and one end of the lower support layer is connected to the longitudinal support layer 104. And a lower electrode is provided on a side of the longitudinal support layer 105 different from the lateral support layer 104.
Preferably, as shown in fig. 19, at least one upper support layer (a first upper support layer 301) is disposed on the lateral support layer 104, the upper support layer is connected to the outer wall of the cylindrical structure of the lower electrode 106, and one end of the upper support layer is flush with the longitudinal support layer 105 in a direction perpendicular to the substrate 100.
Preferably, the side of the longitudinal support layer 105 near the peripheral region 100B is provided with a lower electrode 106, which extends to connect the upper support layer in a direction perpendicular to the substrate 100, and since the upper support layer and the longitudinal support layer 105 are kept flush in a direction perpendicular to the substrate 100, the flatness of the boundary of the capacitor array is ensured. ,
Preferably, at least one lower support layer is disposed between the lateral support layer 104 and the substrate 100, and at least one upper support layer is disposed on the lateral support layer. The lower support layer and the upper support layer are connected with the outer wall of the cylindrical structure of the lower electrode 106, one end of the lower support layer is connected with the longitudinal support layer 105, and one end of the upper support layer and the longitudinal support layer 105 are kept flush in the direction perpendicular to the substrate. Preferably, the longitudinal support layer 105 is provided with a lower electrode 106 on a side surface different from the lateral support layer 104, and the lower electrode 106 is connected to the upper support layer in an extending manner.
Preferably, an isolation layer 102 is further disposed on the substrate 100, and the isolation layer 102 is disposed on the bottom periphery of the cylindrical structure of the lower electrode 106 and covers the device region edge portion 100A'. The capacitor array structure further comprises a plurality of node contacts 101 positioned in the substrate 100, and the bottom of the cylindrical structure of the lower electrode 106 is connected with the node contacts.
Preferably, the materials of the main body supporting layer 120, the upper supporting layer, the lower supporting layer and the isolation layer 102 include, but are not limited to, silicon nitride, and the main body supporting layer 120 may be formed by a deposition process, such as a chemical vapor deposition process. The body support layer 120 may be formed in a one-step deposition process, or the lateral support layer 104 and the longitudinal support layer 105 may be formed in a two-step deposition process, respectively.
Preferably, the capacitor array structure further includes an electrode filling layer 109 and an electrode connecting layer 110. The upper electrode filling layer 109 covers the upper electrodes 108 and fills the gaps between the upper electrodes 108, the upper electrode filling layer 109 is made of boron doped polysilicon, the upper electrode connecting layer 110 covers the outer surface of the upper electrode filling layer 109, and the upper electrode connecting layer 110 is made of tungsten.
In the embodiment of the invention, the main body supporting layer is arranged, so that a peripheral wrapped supporting structure is formed on the device region, compared with a single transverse supporting layer in the prior art, the capacitor array boundary is of a flat structure, cracks formed due to uneven capacitor array boundary positions during subsequent filling material deposition are avoided, the problem of short circuit between plugs and capacitor array boundaries caused by the cracks is further avoided, and the reliability of the capacitor device is improved while the stability of the array region is improved.
Further, the invention also provides a semiconductor device comprising the capacitor array mechanism. The semiconductor device is applied to a dynamic random access memory.
In summary, the present invention provides a capacitor array structure, a method for forming the same, and a semiconductor device, wherein a main body supporting layer with a wrapped periphery is formed on a device region to obtain a flat capacitor array boundary, so as to avoid forming cracks due to uneven capacitor array boundary during subsequent deposition of filling material, and further avoid the problem of short circuit between a plug and the capacitor array boundary caused by the cracks, and improve the reliability of the capacitor device while increasing the stability of the array region.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
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