CN1126378C - Message receiver - Google Patents

Abstract

In a message receiving device, radio paging signals are demodulated into baseband signals, and the baseband signals are decoded into corresponding data. Address information is restored from the data, and message information is restored from the data. The restored message information is subjected to error code correction processing, and on the other hand, that the restored address information is subjected to the error code correction processing is prevented.

Description

message receiver

technical field

The present invention relates to message (message) receivers such as paging receivers or selective paging receivers.

Background technique

In a typical radio paging communication network, each paging receiver is assigned a different identification (ID) signal. Any paging receiver can be called using the assigned ID signal. Typically, a signal representing the message is sent to the paging receiver being called and the message is displayed on the display of the paging receiver.

In this wireless paging communication network, as the length of the processed message increases, the number of bit errors in the message signal restored by the paging receiver increases, and the electric power consumed by the paging receiver also increases.

Usually paging receivers each include a radio wave receiving section and a CPU. The CPU generates radio noise, which interferes with the radio wave receiving unit. As the CPU's effective operating steps per unit time (that is, the CPU's activity rate) increases, the radio noise level generated by the CPU also increases.

US Patent No. 5,142,699 demonstrates a method of suppressing a radio noise level generated during operation of a radio wave receiving section by a CPU-driven clock signal. Specifically, the radio paging receiver disclosed in U.S. Patent 5,142,699 includes a receiving unit, a decoding unit, and distinguishes a specific call signal from a plurality of call signals, and processes a specific message signal after the specific call signal into a The CPU that processed the message signal. The receiving department is put into work intermittently. The decoding part is put into operation according to the first clock signal provided by the first clock generator. A switch circuit selectively connects the CPU with the first clock generator and the second clock generator. The CPU is put into operation according to the second clock signal provided by the second clock generator when the receiving part is not working. The frequency of the second clock signal is much higher than the frequency of the first clock signal. Therefore, when the receiving unit is not in operation, the CPU processes the specific message signal at a rapid processing speed according to the second clock signal, making it a processed message signal. In short, the CPU is driven by the first clock signal when the receiving unit is in operation.

Contents of the invention

It is an object of the present invention to provide an improved message receiver.

One aspect of the present invention provides a message receiving device, including: a first device for demodulating a radio paging signal into a baseband signal; a second device for decoding the baseband signal into corresponding data; alternately performing the data processing and The CPU of other operations; the first clock generator that generates the first clock signal; the second clock generator that generates the second clock signal, the frequency of the first clock signal is higher than the frequency of the second clock signal; the CPU performs the data processing A third device that makes the CPU act in response to the first clock signal; a fourth device that makes the CPU act in response to the second clock signal when the CPU executes the other tasks; wherein when the data is interleaved in units of m bits/word×n words Where the CPU has an error correction capability of α bits, the CPU activated by the first clock signal receives α data units and processes a data block of m×n bits within a time interval of storing the α data units in the buffer.

Description of drawings

FIG. 1 is a block diagram of a wireless message receiver according to a first embodiment of the present invention.

Fig. 2 is a schematic diagram of a paging signal format.

Fig. 3 is a schematic diagram of two-dimensional representation of data in a data block.

FIG. 4 is a flow chart of a program segment controlling the CPU in FIG. 1. FIG.

FIG. 5 is a flowchart of the functional blocks in FIG. 4 .

FIG. 6 schematically shows a conversion table of the relationship between 8-bit error code pattern data and the number of error indication bits.

Fig. 7 is a block diagram of a wireless message receiver according to a second embodiment of the present invention.

FIG. 8 is a flowchart of a program segment controlling the CPU in FIG. 7. FIG.

Fig. 9 is a block diagram of a wireless message receiver according to a third embodiment of the present invention.

FIG. 10 is a flow chart of a program segment controlling the CPU in FIG. 9. FIG.

Fig. 11 is a block diagram of a wireless message receiver according to a fourth embodiment of the present invention.

Fig. 12 is a schematic diagram of a paging signal format.

Fig. 13 is a schematic diagram of two-dimensional representation of data in a data block.

FIG. 14 is a flow chart of a program segment controlling the CPU in FIG. 11. FIG.

FIG. 15 is a flowchart of the functional blocks in FIG. 14 .

Fig. 16 schematically shows a conversion table of the relationship between 8-bit error code pattern data and the number of error indication bits.

Fig. 17 is a block diagram of a wireless message receiver according to a fifth embodiment of the present invention.

FIG. 18 is a flow chart of program segments controlling the CPU in FIG. 17. FIG.

FIG. 19 is a time domain diagram of the reception processing status and data processing status of the wireless message receiver in FIG. 17. FIG.

Fig. 20 is a block diagram of a wireless message receiver according to a sixth embodiment of the present invention.

21 and 22 are flowcharts of program segments controlling the CPU in FIG. 20 .

Detailed ways

first embodiment

Referring to FIG. 1 , a radio message receiver (radio paging receiver) includes an antenna 21 and a subsequent receiving section 22 . The antenna 21 is used to capture radio wave signals as transmitted by the base station. Typically radio wave signals include paging signals with synchronization information, address information and message information. The synchronization information is in front of the address information and message information. The address information is located in front of the message information. The address information includes identification code information. The radio wave signal captured by the antenna 21 is fed to the receiving section 22 . The receiving section 22 demodulates the radio wave signal into a corresponding baseband signal. The decoder 23 following the receiving unit 22 receives the baseband signal, and decodes the baseband signal into corresponding data.

The decoder 23 is connected to a CPU 24 having an I/O port (interface), a processing unit, a combination of RAM and ROM. The CPU 24 may be replaced by a microcomputer, DSP (Digital Signal Processor) or other similar devices. CPU 24 receives the data that decoder 23 outputs. The CPU 24 restores the identification code information (address information) from the received data. CPU 24 is connected with display 25. The CPU 24 is also connected to the receiving unit 22. The CPU 24 works according to the programs stored in the internal ROM.

The wireless message receiver of FIG. 1 stores previously allocated identification code information (predetermined identification code information or predetermined address information) in the ROM within the CPU 24. Predetermined identification code information (predetermined address information) may be stored in a ROM outside the CPU 24.

The CPU 24 compares the restored identification code information (restored address information) with predetermined identification code information (predetermined address information) according to a program. When the restored identification code information (restored address information) actually matches the predetermined identification code information (predetermined address information), the CPU 24 restores the message information from the received data. The CPU 24 then sends the restored message information to the display 25, and controls the display 25 so that the display 25 will display the restored message information.

When the restored identification code information (restored address information) is obviously inconsistent with the predetermined identification code information (predetermined address information), the CPU 24 does not restore the message information from the received data to prevent the CPU 24 from increasing its activity rate. Thus, there is an advantage in suppressing the radio noise level generated by the CPU 24. In addition, the CPU 24 suspends the activity of the receiving unit 22 to save power. Moreover, CPU 24 also keeps display 25 inactive. In this case, no message information is displayed on the display 25 .

FIG. 2 shows the format of the paging signal 121. Referring to FIG. The paging signal 121 is preceded by a synchronization signal (bit synchronization signal) 122 followed by a data block 123 . The sync signal 122 has a bit sequence whose predetermined logic state corresponds to a given pattern (sync pattern). Data in each data block 123 is interleaved in units of "n" words, where "n" represents a given integer. The total number of data blocks 123 is equal to a given number "j". Generally, one or more preceding data blocks 123 represent identification code information (address information), while subsequent data blocks 123 represent message information.

FIG. 3 shows a two-dimensional representation of the data in a data block 123 . As shown in FIG. 3, the capacity of each data block is "m" bits x "n" words, where "m" represents a given integer. Each word has bits 124 representing main information and bits 125 representing error correction information. The main information includes identification code information (address information) or message information. The error correction code used has an error correction capability corresponding to "α" bits, where "α" represents a given integer. In FIG. 3, reference numeral 126 denotes an n-bit data unit subjected to interleaving processing and composed of bits of the same number in each word. In the base station (sending station), the data in each data block 123 is divided into "m" data units. The base station sequentially transmits "m" data units per data block 123 .

The decoder 23 includes a bit synchronization part, and a sampling clock signal is generated from the output signal of the receiving part 22 , corresponding to the bit synchronization signal 122 in the paging signal 121 . The decoder 23 includes a sampling part, which periodically samples the output signal of the receiving part 22 in response to the sampling clock signal, and decodes the output signal of the receiving part 22 into first data bit by bit. The decoder 23 includes a de-interleaving unit for de-interleaving the first data into the second data. Decoder 23 includes a pair of buffer memories, each having a capacity corresponding to a data block 123 in paging signal 121 . Parts of the second data corresponding to each data block 123 in the paging signal 121 are sequentially and alternately written into the buffer memory.

Usually, when a certain buffer memory in the decoder 23 is subjected to data writing processing, another buffer memory is accessed by the CPU 24, so that the CPU 24 reads data (second data) therefrom.

The CPU 24 works according to the programs stored in the internal ROM. FIG. 4 is a flowchart of program segments executed each time a paging signal 121 is received.

As shown in FIG. 4 , the first step 31 of the program segment reads out one block of latest data in a certain buffer memory in the decoder 23 .

Step 32 following step 31 determines whether the read 1 block of data represents address information (identification code information) or message information. When the read 1 piece of data represents address information (identification code information), the program enters step 33 from step 32 . When the read 1 piece of data represents message information, the program enters step 34 from step 32 .

Step 33 determines whether the address information (identification code information) represented by the read 1 block of data is actually consistent with the predetermined address information (predetermined identification code information) stored in the ROM in the CPU 24. When the address information (identification code information) represented by the read 1 block of data actually does not coincide with the predetermined address information (predetermined identification code information), the program proceeds from step 33 to step 37. When the address information (identification code information) represented by the read 1 piece of data actually coincides with the predetermined address information (predetermined identification code information), the program proceeds to step 36 from step 33 .

Step 37 causes the receiving section 22 to suspend activity for a given time interval (predetermined time interval) to save power. After step 37, the current execution cycle of the program segment ends.

Step 34 subjects the message information in the read 1 block of data to error correction processing in response to the error correction code information in the read 1 block of data. In this way, step 34 restores the message information of the correction result from the read block of data.

The next step 35 of the step 34 stores the correction result message information in the CPU24 internal RAM as a piece of message information. After step 35, the program goes to step 36.

Step 36 determines whether all data blocks 123 in paging signal 121 have been processed. When all data blocks 123 in the paging signal 121 have been processed, the program proceeds from step 36 to step 38. Otherwise, the program returns to step 31 by step 36.

Step 38 starts display 25, and all pieces of message information in RAM in CPU 24 are sent to display 25. All pieces of message information form the restored complete message information. Step 38 controls the display 25 so that the display 25 will display the complete message information. After step 38, the current execution cycle of the program segment ends.

As can be understood from the foregoing description, the CPU 24 does not subject 1 block of data representing addresses to error correction processing. Thus, the number of effective work steps of the CPU 24 decreases (ie, the activity rate of the CPU 24 decreases). After finding that the address information (identification code information) represented by the read 1 block of data is actually different from the predetermined address information (predetermined identification code information), the CPU 24 makes the receiving unit 22 suspend the activity for a given time interval to save power. Also, in this case, the CPU 24 does not execute the steps in FIG. 4 except step 37. Therefore, the number of effective work steps of the CPU 24 decreases (ie, the activity rate of the CPU 24 decreases).

As shown in FIG. 5, step 33 has sub-steps 33A, 33B and 33C. The first sub-step 33A following step 32 in FIG. 4 performs an "exclusive OR" operation between the address information (identification code information) represented by the read 1 block of data and the predetermined address information (predetermined identification code information). Address information represented by 1 block of data read out has a given number of bits. Predetermined address information also has this given number of bits. For example the given number of bits is equal to 8, 32 or 64. Assume now that the given number of bits is eight. Execute the result of the "exclusive OR" operation to generate 8-bit error pattern data. In the 8-bit error code pattern data, the "0" bit indicates that the address information represented by the read 1 block of data is consistent with the logic state of the corresponding bit of the predetermined address information, and the "1" bit indicates that the read 1 block of data The logical states of the corresponding bits of the represented address information and predetermined address information are inconsistent (error).

Then sub-step 33B of sub-step 33A, by referring to the conversion table stored in the ROM in the CPU 24, calculate the number of error indication bits in the 8-bit error code pattern data. As shown in FIG. 6, the conversion table provides the relationship between 8-bit code pattern data and the number of error indication bits.

Sub-step 33C following sub-step 33B compares the number of error indication bits with a preset number. When the error indicates that the number of bits is greater than the preset number, the program enters step 37 in Fig. 4 from substep 33C. When the number of error indication bits does not exceed the preset number, the program enters step 36 in FIG. 4 from substep 33C. The preset number is preferably equal to a given integer "α", which is related to the error correction capability of the error correction code.

second embodiment

Referring to FIG. 7 , a radio message receiver (radio paging receiver) includes an antenna 221 and a subsequent receiving section 222 . The antenna 221 is used to capture, for example, radio wave signals transmitted by the base station. Typically radio wave signals include paging signals with synchronization information, address information and message information. The synchronization information is in front of the address information and message information. The address information is located in front of the message information. The address information includes identification code information. The radio wave signal captured by the antenna 221 is fed to the receiving section 222 . The receiving section 222 demodulates the radio wave signal into a corresponding baseband signal.

The subsequent decoder 223 of the receiving unit 222 receives the baseband signal, and decodes the baseband signal into corresponding data.

The decoder 223 is connected to a CPU 224 having an I/O port (interface), a processing unit, and a combination of RAM and ROM. The CPU 224 may be replaced by a microcomputer, DSP (Digital Signal Processor) or other similar devices. CPU 224 receives the data that decoder 223 outputs. The CPU 224 deinterleaves the received data into second data. The CPU 224 restores the identification code information (address information) from the second data. CPU 224 is connected with display 225. The CPU 224 is also connected to the receiving unit 222. CPU 224 is of the type that operates in response to an external clock signal. The CPU 224 is connected to generators 226 and 227 which generate clock signals of a predetermined higher frequency and a predetermined lower frequency, respectively. The frequencies of the two clock signals are, for example, equal to 1.2288 MHz and 76.8 kHz, respectively. The CPU 224 works according to the programs stored in the internal ROM.

Typically, the high frequency clock generator 226 is inactive while the low frequency clock generator 227 is active. Thus, CPU 224 generally operates in response to the low frequency clock signal generated by generator 227, and the activity rate of CPU 224 is relatively low. This advantage resides in suppressing the radio noise level generated by the CPU 224. As will be described later, the CPU 224 activates the high frequency clock signal generator 226 and disables the low frequency clock signal generator 227 in response to the block sync signal. For a given short period of time thereafter, the high frequency clock signal generator 226 and the low frequency clock signal generator 227 remain active and inactive, respectively, and the CPU 224 responds to the high frequency clock signal generated by generator 226 rather than generator 227 generated by a low frequency clock signal.

The work of CPU 224 can be changed between high-speed mode and low-speed mode. When the high-frequency clock signal generator 226 was inactive and the low-frequency clock signal generator 227 was active, the CPU 224 was in a low-speed operating mode. When the high-frequency clock signal generator 226 is active and the low-frequency clock signal generator 227 is inactive, the CPU 224 is in a high-speed operating mode. During the period when the CPU 224 works in the low speed mode, the radio noise level generated by the CPU 224 is effectively suppressed.

The wireless message receiver of FIG. 7 stores previously assigned identification code information (predetermined identification code information or predetermined address information) in the ROM within the CPU 224. Predetermined identification code information (predetermined address information) may be stored in a ROM outside the CPU 224.

The CPU 224 deinterleaves the output data of the decoder 223 into the second data according to a program. And, the CPU 224 restores the identification code information (address information) from the second data. Next, the CPU 224 compares the restored identification code information (restored address information) with predetermined identification code information (predetermined address information). When the restored identification code information (restored address information) actually matches the predetermined identification code information (predetermined address information), the CPU 224 restores the message information from the second data. The CPU 224 then sends the restored message information to the display 225, and controls the display 225 so that the display 225 displays the restored message information.

When the restored identification code information (the restored address information) is obviously inconsistent with the predetermined identification code information (predetermined address information), the CPU 224 does not restore the message information from the second data, so as to prevent the activity rate of the CPU 224 from increasing. This advantage resides in suppressing the radio noise level generated by the CPU 224. In addition, the CPU 224 suspends the activities of the receiving unit 222 to save power. Moreover, CPU 224 also keeps display 225 inactive. In this case, the display 225 does not display any message information.

As shown in FIG. 2 , the paging signal 121 is preceded by a synchronization signal (bit synchronization signal) 122 followed by a data block 123 . The sync signal 122 has a bit sequence whose predetermined logic state corresponds to a given pattern (sync pattern). Data in each data block 123 is interleaved in units of "n" words, where "n" represents a given integer. The total number of data blocks 123 is equal to a given number "j". Generally, one or more preceding data blocks 123 represent identification code information (address information), while subsequent data blocks 123 represent message information.

As shown in FIG. 3, the capacity of each data block is "m" bits x "n" words, where "m" represents a given integer. Each word has bits 124 representing main information and bits 125 representing error correction information. The main information includes identification code information (address information) or message information. The error correction code used has an error correction capability corresponding to "α" bits, where "α" represents a given integer. In FIG. 3, reference numeral 126 denotes an n-bit data unit subjected to interleaving processing and composed of bits of the same number in each word. In the base station (sending station), the data in each data block 123 is divided into "m" data units. The base station sequentially transmits "m" data units per data block 123 .

The decoder 223 includes a bit synchronization part, and a sampling clock signal is generated from the output signal of the receiving part 222 , corresponding to the bit synchronization signal 122 in the paging signal 121 . The decoder 223 includes a sampling part, which periodically samples the output signal of the receiving part 222 in response to the sampling clock signal, and decodes the output signal of the receiving part 222 into first data bit by bit. Decoder 223 includes a pair of buffer memories 223A and 223B, each having a capacity corresponding to one data block 123 in paging signal 121 . Parts of the first data corresponding to each data block 123 in the paging signal 121 are sequentially and alternately written into the buffer memories 223A and 223B. Usually, when a certain buffer memory 223A or 223B in the decoder 223 is subjected to data writing processing, the other buffer memory is accessed by the CPU 224, so that the CPU 224 reads out the first data therefrom.

The decoder 223 also includes a block synchronization section that generates a block synchronization signal in response to the sampling clock signal. A pulse in the block synchronizing signal occurs every time the writing of the first data portion of 1 block to one of the buffer memories 223A and 223B is completed. The decoder 223 outputs the block synchronization signal to the CPU 224.

The CPU 224 works according to the programs stored in the internal ROM. FIG. 8 is a flowchart of program segments executed each time a paging signal 121 is received.

As shown in FIG. 8, the program segment first step 251 determines whether a pulse occurs in the block sync signal. When a pulse occurs in the block sync signal, the program goes from step 251 to step 252 . Otherwise, repeat step 251 .

Step 252 starts the high-frequency clock signal generator 226, makes the low-frequency clock signal generator 227 suspend activities, and makes the CPU 224 enter a high-speed working mode. The next step 253 of step 252 is to read out one block of data from a certain buffer memory 223A or 223B in the decoder 223 that is not currently subjected to data writing processing. Step 254 following step 253 deinterleaves the read 1-block data into a second 1-block data.

Step 255 following step 254 determines whether the second 1 block of data represents address information (identification code information) or message information. When the second block of data represents address information (identification code information), the program enters step 256 from step 255 . When the second block of data represents message information, the program enters step 257 from step 255 .

Step 256 determines whether the address information (identification code information) represented by the second 1 piece of data is actually consistent with the predetermined address information (predetermined identification code information) stored in the ROM in the CPU 224. When the address information (identification code information) represented by the second 1 piece of data actually does not match the predetermined address information (predetermined identification code information), the program proceeds from step 256 to step 260. When the address information (identification code information) represented by the second 1 piece of data actually coincides with the predetermined address information (predetermined identification code information), the program then proceeds to step 259 from step 256 . Step 256 is similar to step 33 in FIGS. 4 and 5 .

Step 260 causes the receiving unit 222 to suspend activity for a given time interval (predetermined time interval) to save power. After step 260, the program goes to step 263.

Step 257 subjects the message information in the second 1 block of data to an error correction process in response to the error correction code information in the second 1 block of data. In this way, step 257 restores the message information of the correction result from the second block of data.

The next step 258 of the step 257 is to store the correction result message information in the RAM in the CPU 224 as a piece of message information. After step 258, the program enters into step 259.

Step 259 determines whether all data blocks 123 in paging signal 121 have been processed. When all the data blocks 123 in the paging signal 121 have been processed, the program enters step 261 from step 259 . Otherwise, program just enters step 262 by step 259.

Step 262 makes the high-frequency clock signal generator 226 suspend activity, starts the low-frequency clock signal generator 227, makes CPU 224 enter the low-speed working mode. After step 262, the program returns to step 251.

Step 261 starts the display 225, and transmits all pieces of message information in the RAM in the CPU 224 to the display 225. All pieces of message information form the restored complete message information. Step 261 controls the display 225 such that the display 225 will display the complete message information. After step 261, the program goes to step 263.

Step 263 makes the high-frequency clock signal generator 226 suspend activity, and starts the low-frequency clock signal generator 227, so that the CPU 224 enters the low-speed working mode. After step 263, the current execution cycle of the program segment ends.

third embodiment

Referring to FIG. 9, a radio message receiver (radio paging receiver) includes an antenna 321 followed by a receiving section 322. Referring to FIG. The antenna 321 is used to catch radio wave signals transmitted by, for example, a base station. Radio wave signals usually include paging signals and information signals with bit synchronization signal sequences. The bit synchronization signal comprises a sequence of bits whose logic states are predetermined to correspond to a given bit pattern (synchronous bit pattern). The information signal represents address information and message information. Address information precedes message information. The address information includes identification code information. The radio wave signal captured by the antenna 321 is input to the receiving section 322 . The receiving section 322 demodulates the radio wave signal into a corresponding baseband signal.

The decoder 323 following the receiving part 322 receives the baseband signal and decodes it into corresponding data.

The decoder 323 is connected to a CPU 324 having an I/O port (interface), a processing section, RAM and ROM combined. CPU 324 can be replaced with microprocessor, DSP or other similar devices. The CPU 324 receives the data generated by the decoder 323. The CPU 324 detects or calculates a bit error rate related to a portion of data generated by the decoder 323 corresponding to the bit synchronization signal. CPU 324 handles the rest of the data generated by decoder 323. The CPU 324 switches the data processing mode between two different types according to the detected bit error rate. The basic task of the CPU 324 is to de-interleave the received data into the second data. The CPU 324 restores the identification code information (address information) from the second data. The CPU 324 is connected to a display 325. The CPU 324 is also connected to the receiving section 322. The CPU 324 operates according to programs stored in the built-in ROM.

The wireless message receiver of FIG. 9 stores previously assigned identification code information (predetermined identification code information or predetermined address information) in the ROM of the CPU 324. Predetermined identification code information (predetermined address information) may also be stored in a ROM outside the CPU 324.

According to the program, the CPU 324 deinterleaves the output data of the decoder 323 into the second data. In addition, the CPU 324 restores the identification code information (address information) from the second data. Furthermore, the CPU 324 compares the restored identification code information (restored address information) with predetermined identification code information (predetermined address information). When the restored identification code information (restored address information) is basically consistent with the predetermined identification code information (predetermined address information), the CPU 324 restores the message information from the second data. Subsequently, the CPU 324 inputs the restored message information to the display 325 and controls the display 325 so as to visually display the restored message data on the display 325.

When the restored identification code information (restored address information) is obviously inconsistent with the predetermined identification code information (predetermined address information), the CPU 324 will not restore the message information from the second data, thereby avoiding the activity of the CPU 324 exacerbated. This helps suppress the wireless noise level generated by the CPU 324. In addition, the CPU 324 usually puts the receiving section 322 in a sleep state to save power. Moreover, CPU 324 also keeps display 325 in a sleep state. In this case, therefore, no message information is displayed on the display 325 .

As shown in FIG. 2 , the header of the paging signal 121 is a synchronization signal (bit synchronization signal) 122 followed by a data block 123 successively. Synchronization signal 122 comprises a sequence of bits whose logic states are predetermined to correspond to a given bit pattern (synchronization bit pattern). Data in each block 123 is interleaved in units of "n" words, where "n" represents a given integer. The total number of blocks 123 is equal to a given number "j". Typically, one or more blocks 123 in the front represent identification code information (address information) and the following blocks 123 represent message information.

As shown in FIG. 3, a block has a capacity of "n" words of "m" bits, where "m" represents a given integer. Each word contains bits 124 representing main information and bits 125 representing error correction code information. The main information includes identification code information (address information) or message information. The error correcting code used is capable of correcting "α" bit errors, where "α" is an integer. In FIG. 3, reference numeral 126 denotes an n-bit data unit subjected to interleave processing and composed of an equal number of bits in each word. At the base station (transmitting station), the data in block 123 is divided into "m" data units. The base station transmits "m" data units of each block 123 sequentially.

The decoder 323 includes a bit synchronization section which generates a sampling clock signal from the output signal of the receiving section 322 corresponding to the first half of the bit synchronization signal 122 in the paging signal 121 . The decoder 323 includes a sampling section which periodically samples the output signal of the receiving section 322 in response to a sampling clock signal to decode the output signal of the receiving section 322 into first data bit by bit. The decoder 323 supplies the first half of the first data corresponding to the second half of the bit synchronization signal 122 in the paging signal 121 to the CPU 324 . Therefore, the first half of the first data is bit synchronization data. The decoder 323 includes a large-capacity buffer memory 323A. The first half of the first data corresponding to each block 123 in the paging signal 123 is sequentially written into different areas of the buffer memory 323A. The buffer memory 323A can be accessed by the CPU 324 so that the first data can be read by the CPU 324.

The CPU 324 operates according to programs stored in the built-in ROM. FIG. 10 shows a flowchart of program segments executed each time a paging signal 121 is received. As shown in FIG. 10 , the first step 351 is to calculate the bit error rate by using the bit synchronization data output by the decoder 323 . Specifically, step 351 compares the bit synchronization data with the preset reference data bit by bit. The preset reference data has a given bit pattern corresponding to the usual bit synchronization data. Bits in the bit synchronization data whose logical state is equivalent to the corresponding bit in the preset reference data are regarded as correct bits. Bits in the bit synchronization data whose logic states are different from the corresponding bits in the preset reference data are regarded as error bits. Step 351 counts each error bit to determine the number of error bits. Step 351 calculates the bit error rate from the ratio of the number of erroneous bits to the total number of bits.

Step 352 following step 351 determines whether the calculated bit error rate is greater than a predetermined reference rate. When the calculated bit error rate is greater than the predetermined reference rate, the program proceeds from step 352 to step 353 . Otherwise, the program jumps from step 352 to step 354.

Step 353 waits for a given time during which the used first data is written into the buffer memory 323A in the decoder 323 . After step 353, the program goes to step 354.

Waiting for the execution of step 353 reduces the activity of the CPU 324. This helps suppress the wireless noise level generated by the CPU 324. Therefore, if the calculated bit error rate is greater than the predetermined reference rate, the CPU 324 less adversely affects the reception section 322 and decoder 323 operations during the writing of the used first data into the buffer memory 323A in the decoder 323.

Step 354 reads one block of data from the buffer memory in the decoder 323 . Each time step 354 is executed, the read data of one block changes sequentially. Step 355 following step 354 deinterleaves the read 1-block data into a second 1-block data.

Step 356 following step 355 determines whether the second 1 block of data represents address information (identification code information) or message information. When the second 1 block of data represents address information (identification code information), the program proceeds from step 356 to step 357 . When the second block of data represents message information, the program proceeds from step 356 to step 358.

Step 357 determines whether the address information (identification code information) represented by the second 1 block of data is substantially the same as the preset address data (preset identification code information) stored in the ROM of the CPU 324. When the address information (identification code information) represented by the second block of data is basically different from the preset address data (preset identification code information), the program proceeds from step 357 to step 361. When the address information (identification code information) represented by the second block of data is basically the same as the preset address data (preset identification code information), the program proceeds from step 357 to step 360 . Step 357 is similar to step 33 in FIGS. 4 and 5 .

Step 361 makes the receiving section 322 sleep for a given interval (a predetermined time interval) to save power. After step 361, the execution loop of the current program segment ends.

Step 358 performs error correction processing on the message information in the second block of data in response to the error correction information in the second block of data. Therefore, step 358 restores the error-corrected final message information from the second block of data.

Following the step 359 after the step 358, the final message information after the error correction is stored in the RAM in the CPU 324 as a message information piece. After step 359, the program goes to step 360.

Step 360 determines whether all blocks 123 in paging signal 121 have been processed. After all blocks 123 in the paging signal 121 have been processed, the program proceeds from step 360 to step 362. Otherwise, the program returns from step 360 to step 354 .

Step 362 activates display 325 and transmits all message information of RAM in CPU 324 to display 325. All message information pieces are composed of restored complete message information. Step 362 controls the display 325 so as to visually display the complete message information on the display 325 . After step 362, the execution cycle of the current program segment is ended.

If the calculated bit error rate is not greater than the predetermined reference rate, the program directly enters step 354 from step 352 . In this case, therefore, data of 1 block is transferred from the buffer memory 323A in the decoder 323 to the CPU 324 and then processed while the first data is continuously written in the buffer memory 323A of the decoder 323. In this way, the CPU 324 processes one block of data and writes the first data into the buffer memory 323A synchronously. This is conducive to rapidly restoring the complete message information.

Fourth embodiment

A fourth embodiment of the present invention will now be described. According to the fourth embodiment of the present invention, a radio paging signal is demodulated into a baseband signal, and the baseband signal is decoded into corresponding data (final decoded data). The address information is recovered from the final decoded data. Message information is restored from the final decoded data. The restored message information is subjected to error correction processing. The restored address information avoids error correction processing.

The fourth embodiment is now described in detail. Referring to FIG. 11, a radio message receiver (radio paging receiver) includes an antenna 421 followed by a receiving section 422. Referring to FIG. The antenna 421 is used to catch radio wave signals transmitted by, for example, a base station. Radio wave signals usually contain paging signals with synchronization information, address information and message information. Synchronization information precedes address information and message information. Address information precedes message information. The radio wave signal captured by the antenna 421 is input to the receiving section 422 . The address information includes identification code information. The receiving section 422 demodulates the radio wave signal into a corresponding baseband signal.

The decoder 423 following the receiving part 422 receives the baseband signal and decodes it into corresponding data.

The decoder 423 is connected to a CPU 424 having an I/O port (interface), a processing section, a combination of RAM and ROM. CPU 424 can be replaced with microprocessor, DSP or other similar devices. The CPU 424 restores the identification code information (address information) from the received data. The CPU 424 is connected to peripherals including a display and sound generator. The sound generator is, for example, a loudspeaker. The CPU 424 is connected to the receiving section 422. The CPU 424 operates according to programs stored in the built-in ROM. Also, the ROM within the CPU 424 holds information represented by codewords, and error correction check bits are added to the codewords.

FIG. 12 shows the format of the paging signal 521. Referring to FIG. The header of the paging signal 521 is a synchronization signal (bit synchronization signal) 522 followed by a data block 523 successively. Synchronization signal 522 comprises a sequence of bits whose logic states are predetermined to correspond to a given bit pattern (synchronization bit pattern). Data in each block 523 is interleaved in units of "n" words, where "n" represents a given integer. The total number of blocks 523 is equal to the given number "j". Normally, one or more blocks 523 in the front represent identification code information (address information) and the following blocks 523 represent message information.

FIG. 13 is a two-dimensional representation of the data in block 523. As shown in FIG. 13, the capacity of one block is "n" words of "m" bits, where "m" represents a given integer. The length of each word is fixed at "m" bits. Each word contains bits 524 representing main information and bits 525 representing error correction code information. The main information includes identification code information (address information) or message information. The error correcting code used is capable of correcting "α" bit errors, where "α" is an integer. In FIG. 13, reference numeral 526 denotes an n-bit data unit subjected to interleave processing and composed of an equal number of bits in each word. At the base station (transmitting station), the data in block 523 is divided into "m" data units. The base station transmits "m" data units of each block 523 sequentially.

The decoder 423 includes a bit synchronization section which generates a sampling clock signal from the output signal of the receiving section 422 corresponding to the first half of the bit synchronization signal 522 in the paging signal 521 . The decoder 323 includes a sampling section which periodically samples the output signal of the receiving section 422 in response to the sampling clock signal to decode the output signal of the receiving section 422 into first data bit by bit. The decoder 423 includes a deinterleave section for deinterleaving the first data into the second data. Decoder 423 includes a pair of buffer memories, each having a capacity equal to one block 523 in paging signal 521 . The parts of the second data corresponding to the blocks 523 in the paging signal 521 are sequentially and alternately written into the buffer memory.

One of the buffer memories of the decoder 423 is usually subjected to data writing processing and the other buffer memory is accessed by the CPU 424 to read data (second data). When the writing of each buffer memory in the decoder 424 reaches a given value, the decoder 423 outputs a specific signal to the CPU 424. Here, the given value corresponds to a data block.

The CPU 424 operates according to programs stored in the built-in ROM. The processing unit of the CPU 424 is a codeword ("m" bits) in a block. When the CPU 424 receives the address assigned to the relevant wireless message receiver, the CPU 424 recognizes the location and the length of the message transmitted to the relevant wireless message receiver. The CPU 424 identifies the number of codewords in the block.

FIG. 14 shows a flowchart of program segments executed each time a paging signal 521 is received. As shown in Fig. 14, the first step 431 of the program segment is to turn off the message receiving flag. The packet reception flag is hereinafter referred to as the flag for short. After step 431, the program goes to step 432. Step 432 determines if the buffer is full. When the buffer is full, the program goes to step 433. Otherwise, step 432 is repeated.

Step 433 determines if the flag is on. When the flag is on, the program goes from step 433 to step 434 . Otherwise, the program proceeds from step 433 to step 435 . Step 434 determines whether the message for the associated wireless message receiver is located within the current block. From step 434, the program proceeds to step 435 when the message sent to the associated wireless message receiver is within the current block. Otherwise the program returns to step 432 from step 434 .

Step 435 reads a block. Step 436 following step 435 sets the variable P to "0". The variable P represents the order of the codeword. After step 436, the program goes to step 437. Step 437 increments the number P by one. Step 438 following step 437 determines whether data processing for 1 block is complete. When the data processing of one block is completed, the program returns from step 438 to step 432 . Otherwise, the program enters step 439 from step 438 .

Step 439 determines if the flag is off. When the flag is off, the program goes from step 439 to step 440. Otherwise, the program proceeds from step 439 to step 441 .

Step 440 extracts codewords with order P. Step 442 determines whether the addresses are consistent with each other. When the addresses coincide with each other, the program proceeds from step 442 to step 443 . Otherwise, the program enters step 444 from step 442 . Step 443 turns the flag on. After step 443, the program returns to step 437.

Step 444 determines whether all address information has been checked. After all address information has been checked, program enters step 445 from step 444. Otherwise, the program returns to step 437 from step 444 . Step 445 suspends the operation of the receiving section. After step 445, the execution loop of the current program segment ends.

Step 441 determines whether the number P corresponds to a message code word passed to the associated wireless message receiver. From step 441, the program proceeds to step 446 when the number P corresponds to the message code word transmitted to the associated wireless message receiver. Otherwise, the program returns to step 437 from step 441 .

Step 446 fetches codewords with order P. Step 447 following step 446 performs error correction operations. Step 448 following step 447 saves the message. A step 449 following step 448 determines whether the entire message is available for delivery to the associated wireless message receiver. From step 449, the program proceeds to step 450 when the entire message to the associated wireless message receiver is available. Otherwise, the program returns to step 437 from step 449 .

Step 450 closes the flag. Step 451 following step 450 outputs a signal to the peripheral. After step 451, the execution loop of the current program segment ends.

It can be seen from the foregoing description that the CPU 424 does not perform error correction processing on one block of data representing the address. This reduces the number of steps in which the CPU 424 effectively operates (i.e., reduces CPU 424 activity). When it is found that the address information (identification code information) represented by read 1 piece of data is substantially different from the predetermined address information (predetermined identification code information), the CPU 424 causes the receiving section 422 to perform an operation at a given time. sleeps between intervals to save power. Also, in this case, the CPU 424 does not perform other steps in FIG. 14 except for performing step 445. This reduces the number of steps in which the CPU 424 effectively operates (i.e., reduces CPU 424 activity).

Address information (codeword) relevant to the wireless message receiver is stored in the ROM of the CPU 424. The address information in the ROM of CPU 424 is a code word, and is " m " bit, is generally equal to 32 bits. Address information (code words) in the ROM of the CPU 424 is divided into four 8-bit segments of "A", "B", "C" and "D". The received m-bit codeword representing address information is also divided into four 8-bit segments "A", "B", "C" and "D".

As shown in Figure 15, step 442 includes sub-steps 442A, 442B and 442C. For each 8-bit segment of "A", "B", "C" and "D", a first sub-step 442A following step 440 of FIG. 14 in the received address information and associated wireless message receiver address information Execute an XOR operation between them. Executing an exclusive OR operation produces 8 bits of error pattern data for each 8-bit segment of "A", "B", "C" and "D". In each 8-bit error pattern data, a bit "0" indicates that the received address information is consistent with the logical state of the corresponding bit of the receiver address information of the relevant wireless message and a bit "1" indicates that the received address information is consistent with the relevant wireless message receiver address information. The logical state of the corresponding bit of the receiver address information is inconsistent (error).

Substep 442B following substep 442A calculates the number of indicated error bits for each 8-bit error data with reference to a conversion table stored in the ROM of CPU 424. As shown in FIG. 16, the conversion table provides the relationship between the 8-bit error data X and the number of indicated error bits EN(X). Therefore, step 442B calculates the indication error bit number EN(A), the indication error bit number EN(B), the indication error bit number EN (C) and indicate the number of error bits EN (D). Subsequently, step 442B calculates the sum Res of the indicated error bit number EN(A), the indicated error bit number EN(B), the indicated error bit number EN(C) and the indicated error bit number EN(D).

Sub-step 442C following sub-step 442B compares the sum Res with the number "α" of error correction capability bits. When the sum Res is larger than the error correction capability bit number "α", the program proceeds from sub-step 442C to step 444 of FIG. 14 . Otherwise, the program proceeds to step 443 of FIG. 14 from substep 442C.

fifth embodiment

A fifth embodiment of the present invention will now be briefly described. According to the fifth embodiment, a radio paging signal is demodulated into a baseband signal, and the baseband signal is decoded into corresponding data. The CPU alternately performs data processing and other tasks. The first and second clock signals have first and second predetermined frequencies, respectively. The first predetermined frequency is greater than the second predetermined frequency. When the CPU performs data processing it operates in response to the first clock signal. It operates in response to the second clock signal while the CPU is performing other tasks. A clock generator that generates a certain frequency is provided, and if the error correction capability of the CPU is "α" and data is interleaved in units of "m" bits/words × "n" words, "n" × "α" is received in the receiving section The CPU has a data processing speed of "m" x "n" bits at this frequency during a bit period.

Referring to FIG. 17, a radio message receiver (radio paging receiver) includes an antenna 621 followed by a receiving section 622. Referring to FIG. The antenna 621 is used to catch radio wave signals emitted by, for example, a base station. Radio wave signals usually contain paging signals with synchronization information, address information and message information. Synchronization information precedes address information and message information. Address information precedes message information. A radio wave signal captured by the antenna 621 is input to the receiving section 622 . The receiving section 622 demodulates the radio wave signal into a corresponding baseband signal.

The decoder 623 following the receiving part 622 receives the baseband signal and decodes it into corresponding data.

The decoder 623 is connected to a CPU 624 having an I/O port (interface), a processing section, a combination of RAM and ROM. CPU 624 can be replaced with microprocessor, DSP or other similar devices. The CPU 624 receives data from the decoder 623. The CPU 624 deinterleaves the received data into second data. The CPU 624 restores the identification code information (address information) from the second data. The CPU 624 is connected to peripherals 625 including a display and sound generator. The sound generator is, for example, a loudspeaker. The CPU 624 is connected to the receiving section 622. CPU 424 operates in response to an external clock signal. The CPU 624 is connected to generators 626 and 627 which generate a predetermined high and low frequency. For example, the two clock signals are equal to 1.2288Mhz and 76.8KHz respectively. The CPU 624 operates according to programs stored in the built-in ROM.

The low frequency clock signal generator 627 is generally active and the high frequency clock signal 626 is generally inactive. Thus, CPU 624 generally operates in response to a low frequency clock signal generated by generator 627, and the activity of CPU 624 is relatively low. This helps suppress the wireless noise level generated by the CPU 624. As described below, the CPU 624 activates the high frequency clock signal generator 626 and deactivates the low frequency clock signal generator 627 in response to the block sync signal. In a given short time interval thereafter, the high-frequency clock signal generator 626 and the low-frequency clock signal generator 627 are still active and inactive, respectively, and the CPU 624 responds to the high-frequency clock signal produced by the generator 626 rather than the generator 627 Generated low frequency clock signal for operation.

CPU 624 can be switched between low speed mode and high speed mode. When the high-frequency clock signal generator 626 and the low-frequency clock signal generator 627 are in an inactive and active state respectively, the CPU 624 is in a low-speed operation mode. When the high-frequency clock signal generator 626 and the low-frequency clock signal generator 627 are in active and inactive states respectively, the CPU 624 is in a high-speed operation mode. When the CPU 624 is running in low speed mode, the wireless noise level generated by the CPU 624 is effectively suppressed.

As shown in FIG. 12 , the header of the paging signal 521 is a synchronization signal (bit synchronization signal) 522 followed by a data block 523 successively. Synchronization signal 522 comprises a sequence of bits whose logic states are predetermined to correspond to a given bit pattern (synchronization bit pattern). Data in each block 523 is interleaved in units of "n" words, where "n" represents a given integer. The total number of blocks 523 is equal to the given number "j". Normally, one or more blocks 523 in the front represent identification code information (address information) and the following blocks 523 represent message information.

As shown in FIG. 13, the capacity of one block is "n" words of "m" bits, where "m" represents a given integer. The length of each word is fixed at "m" bits. Each word contains bits 524 representing main information and bits 525 representing error correction code information. The main information includes identification code information (address information) or message information. The error correcting code used is capable of correcting "α" bit errors, where "α" is an integer. In FIG. 13, reference numeral 526 denotes an n-bit data unit subjected to interleave processing and composed of an equal number of bits in each word. At the base station (transmitting station), the data in block 523 is divided into "m" data units. The base station transmits "m" data units of each block 523 sequentially.

The decoder 623 includes a bit synchronization section which generates a sampling clock signal from the output signal of the receiving section 622 corresponding to the first half of the bit synchronization signal 522 in the paging signal 521 . The decoder 623 includes a sampling section that periodically samples the output signal of the receiving section 622 in response to a sampling clock signal to decode the output signal of the receiving section 622 into first data bit by bit. Decoder 623 includes a pair of buffer memories 623A and 623B, each having a capacity equal to one block 523 in paging signal 521 . The parts of the first data corresponding to the blocks 523 in the paging signal 521 are sequentially and alternately written into the buffer memories 623A and 623B. One of the buffer memories of the decoder 623 is usually used for data write processing and the other buffer memory is accessed by the CPU 424 to read out the first data.

The decoder 623 also includes a block synchronization section for generating a clock synchronization signal in response to the sampling clock signal. A pulse in the block sync signal occurs each time a 1-block portion of the first data is written into the buffer memories 623A and 623B. The decoder 623 outputs a block synchronization signal to the CPU 624. In this manner, when the writing of the buffer memories 623A and 623B of the decoder 623 reaches a given value, the decoder outputs a specific signal to the CPU 624. The value given here corresponds to "n" bits.

The CPU 624 operates according to programs stored in the built-in ROM. The processing unit of the CPU 624 is a codeword ("m" bits) in a block. When the CPU 624 receives the address assigned to the receiver of the relevant wireless message, the CPU 624 recognizes the location and the length of the message transmitted to the receiver of the relevant wireless message information. The CPU 624 identifies the number of codewords in the block.

FIG. 18 shows a flowchart of program segments executed each time a paging signal 521 is received. As shown in Figure 18, the first step 651 of the program segment is to turn off the message receiving flag. The packet reception flag is hereinafter referred to as the flag for short. After step 651, the program goes to step 652. Step 652 determines if "n" bits are available. From step 652, the program proceeds to step 653 when "n" bits are available. Otherwise step 652 is repeated.

Step 653 determines if the flag is on. When the flag is on, the program goes from step 653 to step 654. Otherwise, the program proceeds from step 653 to 655. Step 654 determines whether the message for the associated wireless message receiver is located within the current block. The program proceeds from step 654 to step 655 when the message sent to the relevant wireless message receiver is within the current block. Otherwise the program returns to step 652 from step 654 .

Step 655 reads "n" bits. Step 656 following step 655 determines whether the block has been read. After the block has been read, the program proceeds from step 656 to step 657. Otherwise the program returns to step 652 from step 656 .

Step 657 makes CPU 624 change over to high-speed operation mode. Step 658 following step 657 performs a de-interleaving process. Step 659 following step 658 sets variable P to "0". The variable P represents the order of the codeword. After step 659, the program goes to step 660. Step 660 increments the number P by one. Step 661 following step 660 determines whether data processing for 1 block is complete. When the data processing of one block is completed, the program returns from step 661 to step 662 . Otherwise, the program enters step 663 from step 661 .

Step 622 makes CPU 624 change over to low-speed operation mode. In step 662, the program returns to step 652. Step 663 determines if the flag is off. When the flag is off, the program goes from step 663 to step 664. Otherwise, the program enters step 665 from step 663 .

Step 664 fetches codewords with order P. Step 666 following step 664 determines whether the addresses match. When the addresses coincide with each other, the program proceeds from step 666 to step 667. Otherwise, the program proceeds from step 666 to step 668. Step 666 is similar to step 442 in FIGS. 14 and 15 . Step 667 turns the flag on. After step 667, the program returns to step 660.

Step 668 determines whether all address information has been checked. After all address information has been checked, program enters step 669 from step 668. Otherwise, the program returns to step 660 from step 668 . Step 669 suspends the operation of the receiving section. After step 669, the program goes to step 670. Step 670 makes CPU 624 change over to low-speed operation mode. After step 670, the execution loop of the current program segment ends.

Step 665 determines whether the number P corresponds to the message code word passed to the associated wireless message receiver. When the number P corresponds to the message code word sent to the relevant wireless message receiver, the program proceeds from step 665 to step 671. Otherwise, the program enters step 660 from step 665 .

Step 671 fetches codewords whose order is equal to the number P. Step 672 following step 671 performs error correction operations. A step 674 following step 673 determines whether the entire message is available for delivery to the associated wireless message receiver. From step 674, the program proceeds to step 675 when the entire message to the relevant wireless message receiver is available. Otherwise, the program returns to step 660 from step 674 .

Step 675 turns off the flag. Step 676 following step 675 outputs the signal to the peripheral. After step 676, the program goes to step 670.

Figure 19 shows the timing of the data processing and reception process of block 523, the block is composed of "n" words of "m" bits, and the error correction capability is "α" bits per word. In FIG. 19, reference numeral 81 denotes a timing of receiving and storing the data sequence of "k+1" blocks 523, and reference numeral 82 denotes a timing of data processing of "k" blocks 523. In FIG. 19, reference numeral 83 represents the timing of receiving and storing the data sequence of block 523, while reference numeral 84 represents the timing of receiving "α" data units in the current receiving block under the error correction capability of "α" bits per word. In Fig. 19, reference numeral 85 represents the state of CPU 624 operation clock. The high-speed clock is, for example, 1.2288Mhz. The low-speed clock is, for example, 76.8kHz. The above-described process is executed in the sequence shown in FIG. 19 .

The above-mentioned operation of the CPU 624 is completed under the sequence 84 shown in FIG. 19 . Specifically, if the error correction capability of each word is "α" bits, then the CPU 624 responds at a high The clock runs and processes and ends a "k" block data sequence at high speed. Therefore, the CPU 624 operates so that the bit error rate generated by the receiving section 622 is suppressed at the level of "α" bits per deinterleaving codeword. This is limited to the error correction capability of a codeword, so it can be corrected. This makes it possible to process a data sequence at high speed and process "m" x "n" bits in an interval shorter than that during which "n" x "α" bits are stored in the buffer, thus reducing the bit error rate.

Sixth embodiment

A sixth embodiment of the present invention will now be briefly described. According to the sixth embodiment of the present invention, a radio paging signal is demodulated into a baseband signal, and the baseband signal is decoded into corresponding data. The bit error rate of the data was tested. It is determined whether the detected bit error rate is higher than a predetermined reference rate. Storage devices can store data. The processing device can read data from the storage device and process the read data. If the detected bit error rate is greater than a predetermined reference rate, the operation of the processing device is suspended until the data stored in the storage device is the entire radio paging signal. Operation of the processing device begins after storing data corresponding to the entire radio paging signal in the storage device.

Referring to FIG. 20, a radio message receiver (radio paging receiver) includes an antenna 721 followed by a receiving section 722. Referring to FIG. The antenna 721 is used to catch radio wave signals transmitted by, for example, a base station. Radio wave signals usually include paging signals and information signals with bit synchronization signal sequences. The bit synchronization signal comprises a sequence of bits whose logic states are predetermined to correspond to a given bit pattern (synchronous bit pattern). The information signal represents address information and message information. Address information precedes message information. The address information includes identification code information. A radio wave signal captured by the antenna 721 is input to the receiving section 722 . The receiving section 722 demodulates the radio wave signal into a corresponding baseband signal.

A decoder 723 following the receiving section 722 receives the baseband signal and decodes it into corresponding data.

The decoder 723 is connected to a CPU 724 having an I/O port (interface), a processing section, a combination of RAM and ROM. CPU 724 can be replaced with microprocessor, DSP or other similar devices. The CPU 724 receives the data generated by the decoder 723. The CPU 724 detects or calculates the bit error rate related to the data portion generated by the decoder 723 corresponding to the bit synchronization signal. CPU 724 handles the rest of the data generated by decoder 723. The CPU 724 switches the data processing method between two different types according to the detected bit error rate. The basic task of the CPU 724 is to deinterleave the received data into the second data. The CPU 724 restores the identification code information (address information) from the second data. The CPU 724 is connected to a display 725. The CPU 724 is also connected to the receiving section 722. The CPU 724 operates according to programs stored in the built-in ROM.

As shown in FIG. 12 , the header of the paging signal 521 is a synchronization signal (bit synchronization signal) 522 followed by a data block 523 successively. Synchronization signal 522 comprises a sequence of bits whose logic states are predetermined to correspond to a given bit pattern (synchronization bit pattern). Data in each block 523 is interleaved in units of "n" words, where "n" represents a given integer. The total number of blocks 523 is equal to the given number "j". Normally, one or more blocks 523 in the front represent identification code information (address information) and the following blocks 523 represent message information.

As shown in FIG. 13, the capacity of one block is "n" words of "m" bits, where "m" represents a given integer. The length of each word is fixed at "m" bits. Each word contains bits 524 representing main information and bits 525 representing error correction code information. The main information includes identification code information (address information) or message information. The error correcting code used is capable of correcting "α" bit errors, where "α" is an integer. In FIG. 13, reference numeral 526 denotes an n-bit data unit subjected to interleave processing and composed of an equal number of bits in each word. At the base station (transmitting station), the data in block 523 is divided into "m" data units. The base station transmits "m" data units of each block 523 sequentially.

The decoder 723 includes a bit synchronization section which generates a sampling clock signal from the output signal of the receiving section 722 corresponding to the first half of the bit synchronization signal 522 in the paging signal 521 . The decoder 723 includes a sampling section which periodically samples the output signal of the receiving section 722 in response to a sampling clock signal to decode the output signal of the receiving section 722 into first data bit by bit. The decoder 723 sends the first half of the first data corresponding to the second half of the bit synchronization signal 522 in the paging signal 521 to the CPU 724 . Therefore, the first half of the first data is bit synchronization data. The decoder 723 includes a large-capacity buffer memory 723A. The first data portions corresponding to the respective blocks 523 in the paging signal 521 are sequentially written into different areas of the buffer memory 723A. The buffer memory 723A can be accessed by the CPU 724 so that the first data can be read by the CPU 724. When writing in the buffer memory 723A of the decoder 723 reaches a given value, the decoder outputs a specific signal to the CPU 724. The value given here corresponds to "n" bits.

The CPU 724 operates according to programs stored in the built-in ROM. The processing unit of the CPU 724 is a codeword ("m" bits) in a block. When the CPU 724 receives the address assigned to the associated wireless message receiver, the CPU 724 identifies the location and message length to be transmitted to the associated wireless message receiver. The CPU 724 identifies the number of codewords in the block.

21 and 22 are flowcharts of program segments executed each time a paging signal 521 is received. As shown in Figure 21, the first step 751 of the program segment calculates the bit error rate. Step 751 is similar to step 351 in FIG. 10 . Step 752 following step 751 determines whether the bit error rate is large. When the bit error rate is larger, the program enters step 753 from step 752 . Otherwise, the program enters step 851 in FIG. 22 from step 752 .

Step 753 waits for a given time interval. Step 754 following step 753 makes CPU 724 change over to high-speed mode. Step 755 following step 754 turns off the message reception flag. The packet reception flag is hereinafter referred to as the flag for short. After step 755, the program goes to step 756.

Step 756 determines if the flag is on. When the flag is on, the program goes from step 756 to step 757. Otherwise, the program proceeds from step 756 to step 758. Step 757 determines whether the message for the associated wireless message receiver is located within the current block. When the message sent to the relevant wireless information receiver is located in the current block, the program proceeds from step 757 to step 758. Otherwise the program returns to step 756 from step 757.

Step 758 reads a block. Step 759 following step 758 performs a de-interleaving process. Step 760 following step 759 sets variable P to "0". The variable P represents the order of the codeword. After step 760, the program goes to step 761. Step 761 increments the number P by one. Step 762 following step 761 determines whether data processing for 1 block is complete. When the data processing of 1 block is completed, the procedure returns from step 762 to step 756 . Otherwise, the program enters step 763 from step 762 .

Step 763 determines if the flag is off. When the flag is in the off state, the program proceeds from step 763 to step 764. Otherwise, the program proceeds from step 763 to step 765.

Step 764 fetches the codeword whose order is equal to the number P. Step 766 following step 764 determines whether the addresses match. When the addresses coincide with each other, the program proceeds from step 766 to step 767. Otherwise, the program proceeds from step 766 to step 768. Step 766 is similar to step 442 in FIGS. 14 and 15 . Step 767 turns the flag on. After step 767, the program returns to step 761.

Step 768 determines whether all address information has been checked. After all address information has been checked, program enters step 769 from step 768. Otherwise, the program returns to step 769 from step 768 . Step 769 suspends the operation of the receiving section. After step 769, the program goes to step 770. Step 770 puts the CPU 724 in a slow run mode. After step 770, the execution loop of the current program segment ends.

Step 765 determines whether the number P is equal to the message code word passed to the associated wireless message receiver. From step 765, the program proceeds to step 771 when the number P is equal to the message code word sent to the relevant wireless message receiver. Otherwise, the program returns to step 761 from step 765 .

Step 771 fetches codes with order P. Step 772 following step 771 performs error correction operations. Step 773 following step 772 saves the message. Step 774 following step 773 determines whether the entire message is available for delivery to the associated wireless message receiver. From step 774, the program proceeds to step 775 when the entire message delivered to the relevant wireless message receiver is available. Otherwise, the program returns to step 761 from step 774 .

Step 775 turns off the flag. Step 776 following step 775 outputs the signal to the peripheral. After step 776, the program goes to step 770.

Step 851 in Figure 22 turns off the flag. After step 851, the program goes to step 852. Step 852 determines if "n" bits are available. From step 852, the program proceeds to step 853 when "n" bits are available. Otherwise step 852 is repeated.

Step 853 determines if the flag is on. When the flag is on, the program goes from step 853 to step 854. Otherwise, the program proceeds from step 853 to 855 . Step 854 determines if the message for the associated wireless message receiver is located within the current block. From step 854, the program proceeds to step 855 when the message sent to the relevant wireless message receiver is within the current block. Otherwise the program returns to step 852 from step 854 .

Step 855 reads "n" bits. Step 856 following step 855 determines whether the block has already been read. After the block has been read, the program proceeds from step 856 to step 857. Otherwise the program returns to step 852 from step 856 .

Step 857 makes CPU 724 enter high-speed operation mode. Step 858 following step 857 performs a de-interleaving process. Step 859 following step 858 sets variable P to "0". The variable P represents the order of the codeword. After step 859, the program goes to step 860. Step 860 increments the number P by one. Step 861 following step 860 determines whether data processing for 1 block is complete. When the data processing of block 1 is completed, the program proceeds from step 861 to step 862 . Otherwise, the program enters step 863 from step 861 .

Step 862 causes CPU 724 to enter a low-speed operating mode. After step 862, the program returns to step 852. Step 863 determines if the flag is off. When the flag is turned off, the program proceeds from step 863 to step 864. Otherwise, the program enters step 865 from step 863 .

Step 864 fetches the order P code. Step 866 following step 864 determines whether the addresses match. When the addresses coincide with each other, the program proceeds from step 866 to step 867. Otherwise, the program proceeds from step 866 to step 868. Step 866 is similar to step 442 in FIGS. 14 and 15 . Step 867 turns the flag on. After step 867, the program returns to step 860.

Step 868 determines whether all address information has been checked. After all address information has been checked, program enters step 869 from step 868. Otherwise, the program returns to step 860 from step 868 . Step 869 suspends the operation of the receiving section. After step 869, the program goes to step 870. Step 870 puts the CPU 724 in a slow run mode. After step 870, the execution loop of the current program segment ends.

Step 865 determines whether the number P is equal to the message code word passed to the associated wireless message receiver. From step 865, the program proceeds to step 871 when the number P is equal to the message code word sent to the associated wireless message receiver. Otherwise, the program returns to step 860 from step 865 .

Step 871 fetches codes with order P. Step 872 following step 871 performs error correction operations. Step 873 following step 872 saves the message. Step 874 following step 873 determines whether the entire message is available for delivery to the associated wireless message receiver. From step 874, the program proceeds to step 875 when the entire message to the relevant wireless message receiver is available. Otherwise, the program returns to step 860 from step 874 .

Step 875 turns off the flag. Step 876 following step 875 outputs the signal to the peripheral. After step 876, the execution cycle of the current program segment is ended.

The advantage of this embodiment is that complete message information can be quickly restored. This embodiment has the following advantages. If the bit error rate is high, the CPU may not run during reception to minimize the impact (noise) on the reception process, resulting in better reception sensitivity. If the bit error rate is low, the received data is sequentially processed by the CPU during reception, and only necessary data is processed based on the information generated by the structure analysis, thereby shortening the processing time and reducing power consumption. Yet another advantage is that it is possible to achieve these two mutually reinforcing properties. The advantages of this embodiment are similar to those of the third embodiment.

Claims (1)

1. message receiving system is characterized in that it comprises:

Radio paging signal is demodulated into first device of baseband signal;

Baseband signal is decoded as second device of corresponding data;

Alternately carry out the CPU of this data processing and other operations;

Produce first clock generator of first clock signal;

Produce the second clock generator of second clock signal, the frequency of first clock signal is higher than the frequency of second clock signal;

CPU responds the 3rd device of first clock enabling signal CPU action when carrying out described data processing;

Response second clock signal made the 4th device of CPU action when CPU carried out described other operation;

Be that unit is when CPU has the error correcting capability of α bit when staggered with m bits/words * n word wherein when data, CPU by first clock start signal receives α data unit, and this α data unit is being stored in buffer is handled m * n bit in the time interval data block.

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