CN112599651A - Array substrate and transfer method - Google Patents
Array substrate and transfer method Download PDFInfo
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- CN112599651A CN112599651A CN202011438338.7A CN202011438338A CN112599651A CN 112599651 A CN112599651 A CN 112599651A CN 202011438338 A CN202011438338 A CN 202011438338A CN 112599651 A CN112599651 A CN 112599651A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/85—Packages
- H10H20/8506—Containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67144—Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/85—Packages
- H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
- H10H29/10—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00
- H10H29/14—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00 comprising multiple light-emitting semiconductor components
- H10H29/142—Two-dimensional arrangements, e.g. asymmetric LED layout
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/01—Manufacture or treatment
- H10H20/036—Manufacture or treatment of packages
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/01—Manufacture or treatment
- H10H20/036—Manufacture or treatment of packages
- H10H20/0364—Manufacture or treatment of packages of interconnections
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
The invention provides an array substrate and a transfer method, wherein the array substrate is provided with a plurality of bonding bulges, and each bonding bulge is configured to at least hold a micro device on the surface of the bonding bulge so as to electrically connect the held micro device with the array substrate; the array substrate and the transfer method can enable the array substrate to be in contact with the Micro device only through the bonding protrusions, so that the contact between the Micro device which does not need to be transferred and the array substrate is avoided, and the problems that the ACF is easy to break or tear and the Micro LED cannot be repaired in the ACF bonding process can be solved.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate and a transfer method.
Background
Compared with an OLED display, the Micro LED display has the advantages of high reliability, high color gamut, high brightness, high transparency, high PPI and the like. In addition, the packaging requirement of the Micro LED display is low, and flexible and seamless splicing display is easier to realize. Thus, Micro LED displays are a future display rate with great potential for future development.
Fig. 1 is a process flow diagram of a conventional transfer method. As shown in fig. 1, in the prior art, the contact area between the Micro LED array device 20 and the ACF (anisotropic Conductive film) adhesive layer 11 of the array substrate 10 is large, so that the Micro LED21 is not easily separated after being selectively transferred, and the ACF adhesive layer 11 is easily broken or torn badly, thereby affecting the transfer yield or transfer rate. In addition, the ACF bonding technology has a problem that the Micro LED21 cannot be repaired.
Therefore, it is desirable to provide an array substrate and a transfer method to solve the above-mentioned problems.
Disclosure of Invention
In order to solve the above problems, the invention provides an array substrate and a transfer method, the array substrate can avoid the contact between the Micro device which does not need to be transferred and the array substrate by arranging the bonding protrusion, and further can solve the problems that the ACF bonding is easy to generate holes or tear and the repairing of the Micro LED can not be carried out.
In order to achieve the purpose, the array substrate and the transfer method adopt the following technical scheme.
The invention provides an array substrate, which is provided with a plurality of bonding bulges, wherein each bonding bulge is configured to at least hold a micro device on the surface of the bonding bulge, so that the held micro device is electrically connected with the array substrate.
Further, the array substrate comprises a substrate base plate and a bonding electrode layer arranged on the substrate base plate; each bonding bulge corresponds to and is arranged on a bonding electrode.
Further, each bonding bump comprises a conductive welding layer and an insulating adhesive layer, wherein: the conductive soldering layer is arranged on the bonding electrode and is configured to be used for soldering an electrode of the micro device to the bonding electrode; the insulating adhesive layer covers at least partial area of the outer surface of the conductive welding layer on the bonding electrode, and the insulating adhesive layer is configured to be used for adhering the micro device to the bonding protrusion.
Further, the insulating adhesive layer only covers the surface of the conductive welding layer, which is far away from the bonding electrode layer.
Furthermore, the insulating adhesive layers of the adjacent bonding bulges are mutually continuous to form an adhesive insulating layer; the adhesive insulating layer covers the conductive welding layer, the bonding electrode layer and the substrate base plate.
Further, the conductive solder layer has an ambient melting temperature that is lower than an ambient melting temperature of the bonding electrode; the adhesive insulating layer has an ambient melting temperature lower than an ambient melting temperature of the conductive solder layer.
Further, the material of the conductive welding layer is at least one of indium, tin, bismuth, silver or gold.
Further, the insulating adhesive layer is at least one of epoxy glue, polyimide glue, acrylic glue or silica gel.
Furthermore, the bonding bulge has a preset height; the preset height enables the array substrate to be in contact with the micro device only through the bonding protrusions.
The invention also provides a transfer method based on the array substrate, which comprises the following steps: and (3) aligning: aligning a micro device array carrying micro devices with the array substrate to enable the bonding bulges on the array substrate to be aligned with the micro devices to be transferred; a transfer step: peeling the micro device to be transferred from the micro device array onto the array substrate, wherein the bonding bumps hold the peeled micro device on the surface of the bonding bumps; and, a joining step: and the held micro device is electrically connected with the array substrate through the bonding bumps.
The array substrate and the transfer method have the beneficial effects that:
according to the array substrate, the bonding protrusions are arranged, so that the micro device can be selectively transferred, the problems that ACF is easy to break or tear and the micro device cannot be repaired in ACF bonding in the prior art are solved, and the transfer yield and the transfer rate can be improved; the array substrate is contacted with the micro device only through the bonding bumps by configuring the preset height of the bonding bumps, so that the micro device which does not need to be transferred is prevented from being contacted with the array substrate; by configuring the bonding bumps into a composite structure with a conductive welding layer and an insulating adhesive layer, the micro device can be held on the corresponding bonding bumps, so that the micro device is electrically connected with the bonding electrodes.
According to the transfer method, the array substrate can be contacted with the micro device only through the bonding bumps by adopting the array substrate, so that the micro device which does not need to be transferred can be prevented from being contacted with the array substrate, and the selective transfer of the bonding bumps can be realized; in the transferring step, the bonding bumps can be used for fixing the bonding bumps, and the bonding bumps can be used for realizing the electrical connection between the bonding bumps and the bonding electrodes.
Drawings
The technical solution and other advantages of the present invention will become apparent from the following detailed description of specific embodiments of the present invention, which is to be read in connection with the accompanying drawings.
Fig. 1 is a process flow diagram of a conventional transfer method.
Fig. 2 is a schematic structural diagram of the array substrate according to the first embodiment of the invention.
Fig. 3 is a schematic structural diagram of an array substrate according to a second embodiment of the invention.
Fig. 4 is a schematic structural diagram of a third embodiment of the array substrate according to the present invention.
Fig. 5A-5C are process flow diagrams of the transfer method of the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically or electrically connected or may communicate with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize applications of other processes and/or uses of other materials.
Fig. 2 is a schematic structural diagram of the array substrate according to the first embodiment of the invention. As shown in fig. 2, the present invention provides an array substrate 100, the array substrate 100 is provided with a plurality of bonding bumps 200, each bonding bump 200 is configured to at least hold a micro device 300 on a surface thereof, so that the held micro device 300 is electrically connected to the array substrate 100.
Specifically, the array substrate 100 may be in contact with the micro device 200 only through the bonding bumps 200, and may also hold the micro device 300 only through the bonding bumps 200, and further may be electrically connected to the held micro device 300 through the bonding bumps 200.
According to the array substrate 100, the bonding bumps 200 protruding out of the surface of the array substrate are configured, so that selective transfer of the micro devices 200 and electrical connection between the micro devices 200 and the array substrate 100 can be realized;
obviously, the array substrate 100 of the present invention can only contact the micro devices 200 through the bonding bumps 200, so that the problems that the micro devices 300 are not easily separated after being selectively transferred due to the excessively large contact area between the wafer or the array of micro devices and the array substrate 100, the ACF is easily broken or torn, and the micro devices 300 cannot be repaired, and finally the transfer yield or transfer rate can be improved.
Specifically, the bonding bumps 200 are configured to have a predetermined height such that the array substrate 100 is in contact with the micro device 300 only through the bonding bumps 200. Or, the preset height is such that the bonding bump 200 has a bump distance protruding from the surface of the array substrate 100 in a direction perpendicular to the array substrate 100, and the bump distance is greater than the sum of the warpage heights of the array substrate 100 and the carrier substrate 300 carrying the to-be-transferred micro device 200
That is, the predetermined height of the bonding bumps 200 enables the array substrate 100 to contact the micro devices 300 only through the bonding bumps 200, thereby preventing the micro devices 300 on an array of micro devices from contacting the array substrate 100 without transferring or peeling.
In particular implementations, the Micro device 300 may be a Micro light emitting diode (Micro LED). But it should be understood that: the Micro device 300 of the present invention is not limited to Micro light emitting diodes (Micro LEDs) and certain embodiments may also be applied to other Micro semiconductor devices designed in such a way as to perform a predetermined electronic function (e.g., diode, transistor, integrated circuit) or photonic function (LED, laser) in a controlled manner.
As shown in fig. 2, the array substrate 100 includes a substrate base plate 110 and a bonding electrode layer 120 disposed on the substrate base plate 110.
As shown in fig. 2, the substrate 110 includes a base 111, and a thin film transistor 112 and a common electrode 113 disposed on the base 111.
Among them, the material of the substrate 111 may include polyimide, polysiloxane, epoxy resin, acrylic resin, polyester, and/or the like. In one embodiment, the substrate 111 may comprise polyimide.
As shown in fig. 2, the thin film transistor 112 includes an active layer 1121, a gate insulating layer 1122, a gate electrode 1123, a first insulating layer 1124, a drain electrode 1125, a source electrode 1126, and a second insulating layer 1127.
As shown in fig. 2, the active layer 1121 is disposed on the substrate 111. In particular implementations, the active layer 1121 may include a silicon compound such as polysilicon. In some embodiments, source and drain regions including p-type or n-type impurities may be formed at both ends of the active layer 1121. In some embodiments, the active layer 1121 may include an oxide semiconductor, such as Indium Gallium Zinc Oxide (IGZO), Zinc Tin Oxide (ZTO), Indium Tin Zinc Oxide (ITZO), and/or the like.
Specifically, the active layer 1121 includes a channel region and source and drain regions located at the periphery of the channel region. Wherein the channel region may serve as a channel through which charge may move or be transferred, and the source and drain regions are used for source and drain electrical connections or contacts, respectively.
As shown in fig. 2, the gate insulating layer 1122 is formed on the active layer 1121 to cover the channel region. In particular implementations, the gate insulating layer 1122 may comprise silicon oxide, silicon nitride, silicon oxynitride, and/or the like. These may be used alone or in combination thereof.
As shown in fig. 2, the gate electrode 1123 is disposed on the gate insulating layer 1122. Specifically, the gate electrode 1123 is stacked in a region of the gate insulating layer 1122 corresponding to the channel region.
Fig. 2 shows that the thin film transistor 112 has a top gate structure in which a gate electrode 1123 is located above the active layer 1121. However, the thin film transistor 112 may have a bottom gate structure in which the gate electrode 1123 is disposed under the active layer 1121.
As shown in fig. 2, the first insulating layer 1124 is disposed on the gate 132 and covers the gate 1123, the gate insulating layer 1122 and the active layer 1121; also, the first insulating layer 1124 is provided with first via holes at positions corresponding to the source region and the drain region, respectively.
As shown in fig. 2, the drain 1125 and the source 1126 are disposed on the first insulating layer 1124 and electrically connected or contacted to the source and the drain respectively through the first via.
In particular implementations, the gate 1123, the drain 1125, and the source 1126 may include a metal, an alloy, or a metal nitride. For example, the gate electrode 1123 may include a metal such as aluminum (Al), silver (Ag), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), molybdenum (Mo), titanium (Ti), platinum (Pt), tantalum (Ta), and neodymium (Nd), an alloy thereof, and/or a nitride thereof. These may be used alone or in combination thereof.
With continued reference to fig. 2, the second insulating layer 1127 is disposed over and covers the drain 1125 and the source 1126 and the first insulating layer 1124.
In particular implementations, the second insulating layer 1127 may include an organic material, such as polyimide, epoxy-based resin, acrylic resin, polyester, and/or the like.
As shown in fig. 2, the common electrode 113 is disposed in the same layer as the drain electrode 1125 and the source electrode 1126 of the thin film transistor layer 120. For example, in the present embodiment, the common electrode 113 is disposed on the first insulating layer 1124 and covered by the second insulating layer 1127.
As shown in fig. 2, the bonding electrode layer 120 is disposed on the substrate base plate 110, and the bonding electrode layer 120 includes a plurality of bonding electrodes 121.
For example, as shown in fig. 2, in the present embodiment, the bonding electrode layer 120 is disposed on the second insulating layer 1127, and the bonding electrode 121 is electrically connected to the drain 1125 and the source 1126 of the thin film transistor layer 121 or the common electrode 113 through a via hole disposed on the second insulating layer 1127.
Specifically, the bonding electrode 121 includes a first bonding electrode 141 electrically connected to the drain 1125 or the source 1126, and a second bonding electrode 142 electrically connected to the common electrode.
For example, as shown in fig. 2, in the present embodiment, the bonding electrode 121 may be a pixel electrode.
As shown in fig. 2, the bonding bumps 200 are disposed on the bonding electrode layer 120, and each bonding bump 200 is correspondingly disposed on one of the bonding electrodes 121.
In detail, each bonding bump 200 starts from a surface of the bonding electrode 121 facing away from the substrate base 110 and extends in a direction facing away from the substrate base 110 to protrude from the surface of the array substrate 100.
It should be noted that the present invention does not limit the corresponding relationship between the bonding bump 200 and the bonding electrode 121. For example, in the present embodiment, each bonding electrode 121 corresponds to one bonding bump 200, and in other embodiments, a plurality of bonding bumps 200 may be correspondingly disposed on each bonding electrode 121. It is sufficient that the bonding bump 200 has a cross-sectional size or shape that is appropriately configured for use in a micro device transfer process.
As shown in fig. 2, the bonding bump 200 includes a conductive bonding layer 210 and an insulating adhesive layer 220.
As shown in fig. 2, the conductive soldering layer 210 is disposed on one of the bonding electrodes 121 and is configured to solder an electrode of a micro device 300 onto the bonding electrode 121, so as to electrically connect the micro device 300 and the array substrate 100.
Specifically, the conductive solder layer 210 has an ambient melting temperature lower than the ambient melting temperature of the bonding electrode 121. In a specific implementation, the material of the conductive soldering layer 210 is at least one of indium, tin, bismuth, silver or gold. For example, the material of the conductive solder layer 210 is at least one of In, Sn, AuSn, SnBi, SnAgBi, or Au/In.
When a micro device 300 is bonded to the array substrate 100, the conductive bonding layer 210 may be exposed and melted by processing the bonding bump 200 to bond the electrode of the micro device 300 to the bonding electrode 121, so that the micro device 300 and the array substrate 100 can be electrically connected.
The "processing on the bonding bump 150" may be a hot pressing process, or may be other common processing methods. The invention does not limit the specific implementation method of the process treatment.
It should be noted that the present invention is not limited to the film structure or shape of the conductive welding layer 210. For example, in the present embodiment, the conductive welding layer 210 has a single-layer structure. In other embodiments, the conductive welding layer 210 may be a multi-layer laminated structure.
As shown in fig. 2, the insulating adhesive layer 220 covers at least a partial region of the outer surface of the conductive welding layer 210 on the bonding electrode 121, and the insulating adhesive layer 220 is configured to adhere the micro device 300 to the bonding bump 200.
During the transfer of the micro device 300, the insulating adhesive layer 220 can adhere to the surface of the micro device 300 in contact therewith, thereby holding a micro device 300 on the surface of the bonding bump 200 to which it belongs.
In an implementation, the insulating adhesive layer 220 may be disposed for one single bonding bump or disposed for a plurality of bonding bumps 200.
For example, as shown in fig. 2, in the present embodiment, the insulating adhesive layer 220 is commonly disposed for a plurality of bonding bumps 200, such that the insulating adhesive layer 220 substantially constitutes an adhesive insulating layer 230 covering the conductive solder layer 210, the bonding electrode layer 120 and the second insulating layer 1127. The adhesive insulation layer 230 may also serve as an outer surface of the array substrate 100.
Alternatively, the insulating adhesive layers 220 of the adjacent bonding bumps 200 are continuous to form an adhesive insulating layer 230, and the adhesive insulating layer 230 covers the conductive welding layer 210, the bonding electrode layer 110 and the substrate 110.
In other embodiments, the insulating adhesive layer 220 is separately disposed for one bonding bump 200. In this case, the present invention does not limit the specific area or area of the insulating adhesive layer 220 covering the outer surface of the conductive welding layer 210.
Specifically, the insulating adhesive layer 220 has an ambient melting temperature lower than that of the conductive soldering layer 220. In an implementation, the insulating adhesive layer 220 is an organic insulating adhesive. For example, the insulating adhesive layer 220 may be at least one of epoxy adhesives, polyimide adhesives, acrylic adhesives, and silicone adhesives.
It should be noted that the present invention does not limit the specific structure of the bonding bump 200, and fig. 2 is only an exemplary structure of the bonding bump 200 according to the present invention. For example, in other embodiments, the bonding bumps 200 may also be formed by directly integrally forming or laminating bonding materials with adhesive properties.
Fig. 3 is a schematic structural diagram of an array substrate according to a second embodiment of the invention. Compared with the array substrate shown in fig. 2, the structure of the bonding bump 200 of the array substrate 100 according to this embodiment is different.
As shown in fig. 3, in the present embodiment, the insulating adhesive layer 220 covers only the surface of the conductive welding layer 210 facing away from the bonding electrode 121.
Fig. 4 is a schematic structural diagram of a third embodiment of the array substrate according to the present invention. Compared with the array substrate shown in fig. 2, the structure of the bonding bump 200 of the array substrate 100 according to this embodiment is different.
As shown in fig. 4, in the present embodiment, the insulating adhesive layer 220 covers a surface of the conductive welding layer 210 facing away from the bonding electrode 121 and a partial area of an outer side surface of the conductive welding layer 210 in a thickness direction thereof.
It should be noted that fig. 2, 3 and 4 are only schematic structures of the insulating adhesive layer 220. In implementation, the covering position or the covering area of the insulating adhesive layer 220 may be changed according to the specific requirements of the bonding bump 200 or the micro device 300.
Fig. 5A-5C are process flow diagrams of the transfer method of the present invention. As shown in fig. 5A to 5C, the present invention provides a transfer method including the steps of:
s1, alignment step: aligning a micro device array carrying micro devices with the array substrate to enable the bonding bulges on the array substrate to be aligned with the micro devices to be transferred;
s2, transition step: peeling the micro device to be transferred from the micro device array onto the array substrate, wherein the bonding bumps hold the peeled micro device on the surface of the bonding bumps; and the number of the first and second groups,
s3, a joining step: and the held micro device is electrically connected with the array substrate through the bonding bumps.
As shown in fig. 5A, through the step S1, the bonding bumps 200 on the array substrate 100 are aligned with and contact the micro devices 300 to be transferred, so that the micro devices 300 on the micro device array that need not be transferred can be prevented from contacting the array substrate 100.
As shown in fig. 5B, the micro devices 300 to be transferred are separated from the carrier substrate 400 of the micro device array and held on the surface of the bonding bumps 200 by the peeling process of step S2.
In specific implementation, the peeling process can adopt laser lift-Off (laser lift-Off), chemical etching (chemical) or thermal stress peeling (thermal stress). In this embodiment, the lift-off process employs laser lift-off.
As shown in fig. 5C, in the step S3, the conductive bonding layer 210 and the insulating adhesive layer 220 of the bonding bump 200 are melted and cooled to be solidified, and the electrode of the micro device is bonded to the bonding electrode 121. In specific implementation, the welding process can be realized by adopting a hot pressing process.
For example, as shown in fig. 5C, in the present embodiment, the bonding head 500 is used to heat to melt the insulating adhesive layer 220 and expose the conductive soldering layer 210; then, the bonding head 500 is continuously heated to melt the conductive bonding layer 210, and at the same time, the melted conductive bonding layer 210 is used to bond the electrode of the micro device 300 to the bonding electrode 121 under the pressure of the bonding head 500.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The array substrate and the transferring method provided by the embodiment of the invention are described in detail above, and the principle and the implementation manner of the invention are explained in the present document by applying specific examples, and the description of the above embodiments is only used to help understanding the technical scheme and the core idea of the invention; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
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