CN112583360B - Power amplifier amplitude and phase consistency debugging device and method - Google Patents
Power amplifier amplitude and phase consistency debugging device and method Download PDFInfo
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Abstract
The invention discloses a device and a method for debugging amplitude-phase consistency of a power amplifier, wherein the device comprises the following components: the signal source is used for generating a reference signal; the power divider equally divides the reference signal into multiple paths of signals to be output; the amplitude-phase modulation unit is used for adjusting signals of each output channel signal of the power divider according to the amplitude and time delay correction factors; the power amplifier array comprises a plurality of power amplifying units; the synthesizer is used for synthesizing the multi-path output signals of the power amplifier array; the analog-to-digital conversion unit is used for respectively acquiring output signals of the power amplification unit and realizing analog-to-digital conversion; and the FPGA unit determines the amplitude and the time delay correction factor of each power amplification unit according to the output signal of the analog-to-digital conversion unit. The amplitude and the time delay correction factors of each power amplification unit are determined based on monitoring the output signals of each channel of the power amplification array, and the amplitude and the time delay of each channel are adjusted according to the amplitude and the time delay correction factors of each power amplification unit, so that the amplitude-phase consistency of the power amplification array in a wide input dynamic range is improved.
Description
Technical Field
The invention belongs to the technical field of power amplifiers, and particularly relates to a device and a method for debugging amplitude-phase consistency of a power amplifier.
Background
The fixed power amplifier component is one of key components in the T/R component, and the offset of amplitude and phase tracking between power components, namely amplitude-phase consistency directly influences the performance of the T/R component. As technology develops and demand increases, the mass producibility of power amplifier components becomes a critical technology. Due to the problems of production process, chip batch and the like, the array power amplifier is easy to cause the problem of inconsistent amplitude and phase.
Disclosure of Invention
In order to solve the problem of inconsistent amplitude and phase of the conventional power amplifier array, the invention provides a device and a method for debugging the amplitude and phase consistency of the power amplifier, which adopt an automatic amplitude and phase control system to improve the amplitude and phase consistency of the power amplifier array.
The invention is realized by the following technical scheme:
a power amplifier amplitude and phase consistency debugging device comprises:
the signal source is used for generating a reference signal;
the power divider equally divides the reference signal of the signal source into a plurality of paths of signals to be output by taking the reference signal as input;
the power amplifier array comprises a plurality of power amplifying units to realize signal amplification;
the synthesizer is electrically connected with the output end of the power amplifier array and synthesizes and outputs the multi-path output signals of the power amplifier array;
the input end of the analog-to-digital conversion unit is electrically connected with the output end of the power amplification unit, and the output end of the analog-to-digital conversion unit is electrically connected with the input end of the power amplification unit and converts an output signal of the power amplification unit into an analog signal;
the input end of the FPGA unit is electrically connected with the output end of the analog-to-digital conversion unit, and the amplitude and the time delay correction factor of each power amplification unit are determined according to the output signal of the analog-to-digital conversion unit;
and the input end of the amplitude-phase modulation unit is electrically connected with the output end of the power divider and the output end of the FPGA unit, the output end of the amplitude-phase modulation unit is electrically connected with the input end of the power amplification unit, and signals of each output channel of the power divider are adjusted according to the amplitude and time delay correction factors.
According to the scheme, a signal source is used for generating a reference signal, a power divider equally divides the reference signal into multiple paths for output, an analog-to-digital conversion unit collects output signals of a power amplification unit and uses the output signals as comparison signals of an FPGA unit, the FPGA unit determines amplitude and time delay correction factors of the power amplification unit of each channel according to signals of each path of a power amplifier array, and an amplitude-phase modulation unit adjusts the amplitude and time delay of information of each channel according to the correction factors. The analog-to-digital conversion unit, the FPGA unit and the amplitude-phase modulation unit form automatic amplitude-phase control, the detection and correction of the amplitude phase and the time delay of each power amplification unit are realized based on software, and the amplitude-phase consistency of the power amplification units in a wide input dynamic range is improved.
Preferably, the amplitude-phase modulation unit includes a first 90-degree mixer, a single-balanced bi-phase modulator, a second 90-degree mixer, and an IQ vector modulator, which are electrically connected in sequence.
Furthermore, the number of the single-balanced dual-phase modulators is two, the two single-balanced dual-phase modulators are respectively connected between the first 90-degree mixer and the second 90-degree mixer, and the electric signals of the single-balanced dual-phase modulators are connected to the control end of the FPGA unit.
Furthermore, the IQ vector modulator comprises a modulation branch and a combiner which are electrically connected in sequence by signals, and the modulation branch comprises an in-phase combiner, a bi-phase modulator and an attenuator which are electrically connected in sequence by signals.
Furthermore, the number of the modulation branches is two, the two modulation branches are respectively connected between the second 90-degree mixer and the combiner, and the dual-phase modulator and the attenuator of the modulation branches are electrically connected to the control end of the FPGA unit through signals.
Preferably, the FPGA unit includes:
a calculation module for determining the maximum homodromous component of each power amplification unit and calculating the average value of each maximum homodromous component,
a reference selecting module which takes the channel where the power amplifying unit corresponding to the maximum homodromous component closest to the average value is positioned as a reference channel,
and the confirming module confirms the amplitude and the time delay correction factor of each channel according to the reference channel.
A power amplifier amplitude and phase consistency debugging method comprises the following steps:
generating a reference signal and equally dividing the reference signal into a plurality of paths of signals;
the multi-path signals are respectively used as input signals of the amplitude-phase modulation unit and amplified and output through the corresponding power amplification units;
acquiring output signals of each power amplification unit;
performing analog-to-digital conversion on output signals of the power amplification units and determining amplitude and time delay correction factors of each power amplification unit;
the amplitude-phase modulation unit adjusts the input signals of the power amplification units according to the amplitude and time delay correction factors;
each power amplification unit respectively amplifies the adjusted signals;
and combining and outputting the output signals of the power amplification units.
Preferably, the method for determining the amplitude and time delay correction factors comprises the following steps:
selecting a channel where a power amplification unit is located as a reference channel,
calculating the difference of the maximum homodromous component of each channel and the reference channel;
the selection method of the reference channel comprises the following steps:
determining the maximum homodromous component of each power amplification unit,
the average of the maximum isotropic components is calculated,
and taking the channel where the power amplification unit corresponding to the maximum homodromous component closest to the average value is located as a reference channel.
Compared with the prior art, the invention at least has the following advantages and beneficial effects:
the method and the device of the scheme are based on monitoring the output signals of all channels of the power amplifier array, so that the amplitude and the time delay correction factor of each power amplification unit are determined, and the amplitude and the time delay of each channel are adjusted according to the amplitude and the time delay correction factor of each power amplification unit, so that the amplitude-phase consistency of the power amplifier array in a wide input dynamic range is improved.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic diagram of the present invention.
Fig. 2 is a schematic diagram of an amplitude-phase modulation unit.
Detailed Description
The invention is further described with reference to the following figures and specific embodiments. It should be noted that the description of the embodiments is provided to help understanding of the present invention, but the present invention is not limited thereto. Specific structural and functional details disclosed herein are merely illustrative of example embodiments of the invention. This invention may, however, be embodied in many alternate forms and should not be construed as limited to the embodiments set forth herein.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of example embodiments of the present invention.
It should be understood that, for the term "and/or" as may appear herein, it is merely an associative relationship that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, B exists alone, and A and B exist at the same time; for the term "/and" as may appear herein, which describes another associative object relationship, it means that two relationships may exist, e.g., a/and B, may mean: a exists independently, and A and B exist independently; in addition, for the character "/" that may appear herein, it generally means that the former and latter associated objects are in an "or" relationship.
It will be understood that when an element is referred to herein as being "connected," "connected," or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. Conversely, if a unit is referred to herein as being "directly connected" or "directly coupled" to another unit, it is intended that no intervening units are present. In addition, other words used to describe the relationship between elements should be interpreted in a similar manner (e.g., "between … …" versus "directly between … …", "adjacent" versus "directly adjacent", etc.).
It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes" and/or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and/or groups thereof.
It should also be noted that, in some alternative designs, the functions/acts noted may occur out of the order noted in the figures. For example, two figures shown in succession may, in fact, be executed substantially concurrently, or the figures may sometimes be executed in the reverse order, depending upon the functionality/acts involved.
It should be understood that specific details are provided in the following description to facilitate a thorough understanding of example embodiments. However, it will be understood by those of ordinary skill in the art that the example embodiments may be practiced without these specific details. For example, systems may be shown in block diagrams in order not to obscure the examples in unnecessary detail. In other instances, well-known processes, structures and techniques may be shown without unnecessary detail in order to avoid obscuring example embodiments.
The embodiment discloses a power amplifier amplitude and phase consistency debugging method, which comprises the following steps:
generating a reference signal and equally dividing the reference signal into a plurality of paths of signals; the equally divided signals are original signals, and the signals initially received by each power amplification unit are ensured to be the same.
And respectively taking the multipath signals as input signals of the amplitude-phase modulation unit, amplifying and outputting the input signals through the corresponding power amplification units, and acquiring output signals of each power amplification unit.
And performing analog-to-digital conversion on the output signals of the power amplification units, taking the converted signals as a judgment set for judging amplitude and delay correction factors, and determining the amplitude and delay correction factors of each power amplification unit according to the judgment set. Specifically, the maximum homodromous component of each power amplification unit is determined, the average value of the maximum homodromous components of each power amplification unit is calculated, the channel where the power amplification unit closest to the average value is located is taken as a reference channel, and the difference between the maximum homodromous component of each channel and the maximum homodromous component of the reference channel is calculated, so that the amplitude and the time delay correction factor are determined.
And the amplitude-phase modulation unit adjusts the input signals of the power amplification units according to the amplitude and the time delay correction factors, so that the amplitude of each channel is consistent with that of the reference channel, and the time delay between the channels is ensured to be consistent with that of the reference channel.
And each power amplification unit amplifies the regulated signals respectively, and outputs the combined output signals of each power amplification unit.
Based on the method, a device for implementing the method is disclosed, and as shown in fig. 1, the device includes a signal source, a power divider, a power amplifier array, a synthesizer, an analog-to-digital conversion unit, an FPGA unit, and an amplitude-phase modulation unit. The signal source is used for generating a reference signal; the power amplifier array is composed of a plurality of power amplifying units, the amplitude-phase consistency needs to be kept among the power amplifying units, and the power amplifier array is provided with at least 2 power amplifying units; the power divider equally divides the reference signal into multiple paths of signals to be output, and the equally divided multiple paths of output signals are respectively used as adjusting signals of each amplitude and phase modulation unit; the synthesizer is used for synthesizing a plurality of paths of output signals of the power amplifier array; the amplitude-phase modulation unit is arranged between the power divider and the power amplifier array; the analog-to-digital conversion unit respectively collects output signals of the power amplification unit and realizes analog-to-digital conversion, and the analog-to-digital conversion unit is provided with a plurality of paths which correspond to the paths of the power amplifier array power amplifiers one by one to realize output signal collection; the FPGA unit determines amplitude and delay correction factors of each power amplification unit according to signals output by the analog-to-digital conversion unit, the amplitude-phase modulation unit adjusts signals of each output channel of the power divider according to the amplitude and delay correction factors to ensure amplitude-phase consistency of each channel of the power amplifier array, specifically, a calculation module of the FPGA unit calculates an average value of maximum homodromous components of each power amplification unit, a confirmation module of the FPGA unit takes a channel where the power amplification unit closest to the average value is located as a reference channel, and a confirmation module of the FPGA unit calculates a difference between the maximum homodromous component of each channel and the maximum homodromous component of the reference channel to determine the amplitude and delay correction factors.
Specifically, referring to fig. 2, the amplitude-phase modulation unit includes a first 90-degree mixer, a single-balanced bi-phase modulator, a second 90-degree mixer, and an IQ vector modulator, which are connected in sequence. The single-balanced dual-phase modulator comprises a first single-balanced dual-phase modulator and a second single-balanced dual-phase modulator, the first single-balanced dual-phase modulator and the second single-balanced dual-phase modulator are respectively connected between the first 90-degree mixer and the second 90-degree mixer, and the single-balanced dual-phase modulators are electrically connected to the control end of the FPGA unit through signals. Based on the single-balance bi-phase modulator and the IQ vector modulator, modulation of continuous phases and amplitudes is achieved, and anti-interference capability is improved.
The IQ vector modulator comprises a modulation branch and a combiner which are electrically connected in sequence through signals, and the modulation branch comprises an in-phase combiner, a bi-phase modulator and an attenuator which are connected in sequence through signals. The two modulation branches are respectively connected between the second 90-degree mixer and the combiner, and the two-phase modulator and the attenuator of each modulation branch are electrically connected to the control end of the FPGA unit through signals. The modulation branch comprises a first in-phase combiner, a second in-phase combiner, a first bi-phase modulator, a second bi-phase modulator, a first attenuator and a second attenuator, the first in-phase combiner, the first bi-phase modulator and the first attenuator form a first modulation branch, the second in-phase combiner, the second bi-phase modulator and the second attenuator form a second modulation branch, the two modulation branches are respectively connected between the second 90-degree mixer and the combiner, and the bi-phase modulators and the attenuators of the two modulation branches are electrically connected to the control end of the FPGA unit through signals. By adopting the amplitude-phase modulation unit, complex modulation can be realized, and amplitude-phase consistency adjustment of equipment in a wide input dynamic range can be realized.
According to the scheme, the amplitude and delay consistency conditions of the output of each power amplifier of the power amplifier array are monitored through the FPGA unit, the amplitude and delay correction factors are determined, the input signals of each power amplifier unit are adjusted through the amplitude and delay correction factors, the output is corrected through continuous feedback until the amplitude of each channel is consistent with the amplitude of the reference channel, the delay between each channel is guaranteed to be consistent with the delay of the reference channel, and the amplitude consistency adjustment under a wide input dynamic range can be realized.
The embodiments described above are merely illustrative, and may or may not be physically separate, if referring to units illustrated as separate components; if reference is made to a component displayed as a unit, it may or may not be a physical unit, and may be located in one place or distributed over a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: modifications may be made to the embodiments described above, or equivalents may be substituted for some of the features described. And such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Finally, it should be noted that the present invention is not limited to the above alternative embodiments, and that various other forms of products can be obtained by anyone in light of the present invention. The above detailed description should not be taken as limiting the scope of the invention, which is defined in the claims, and which the description is intended to be interpreted accordingly.
Claims (9)
1. The utility model provides a power amplifier amplitude and phase consistency debugging device which characterized in that includes:
the signal source is used for generating a reference signal;
the power divider takes the reference signal of the signal source as input and equally divides the reference signal into a plurality of paths of same signals to be output;
the power amplifier array comprises a plurality of power amplifying units to realize signal amplification;
the synthesizer is electrically connected with the output end of the power amplifier array and synthesizes and outputs the multi-path output signals of the power amplifier array;
the input end of the analog-to-digital conversion unit is electrically connected with the output end of the power amplification unit and converts an output signal of the power amplification unit into an analog-to-digital signal;
the input end of the FPGA unit is electrically connected with the output end of the analog-to-digital conversion unit, and the amplitude and the time delay correction factor of each power amplification unit are determined according to the output signal of the analog-to-digital conversion unit;
and the input end of the amplitude-phase modulation unit is electrically connected with the output end of the power divider and the output end of the FPGA unit, the output end of the amplitude-phase modulation unit is electrically connected with the input end of the power amplification unit, and signals of each output channel of the power divider are adjusted according to the amplitude and time delay correction factors.
2. The power amplifier amplitude-phase consistency debugging device according to claim 1, wherein the amplitude-phase modulation unit comprises a first 90-degree mixer, a single-balanced bi-phase modulator, a second 90-degree mixer, and an IQ vector modulator, which are electrically connected in sequence by signals.
3. The device of claim 2, wherein there are two single-balanced dual-phase modulators, the two single-balanced dual-phase modulators are connected in parallel and respectively connected between the first 90-degree mixer and the second 90-degree mixer, and the single-balanced dual-phase modulator is electrically connected to the control terminal of the FPGA unit through a signal.
4. The apparatus of claim 2, wherein the IQ vector modulator comprises a modulation branch and a combiner electrically connected in sequence, and the modulation branch comprises an in-phase combiner, a bi-phase modulator, and an attenuator electrically connected in sequence.
5. The device for debugging amplitude-phase consistency of a power amplifier according to claim 4, wherein the number of the modulation branches is two, the two modulation branches are respectively connected between the second 90-degree mixer and the combiner, and both the bi-phase modulator and the attenuator of the modulation branches are electrically connected to the control end of the FPGA unit through signals.
6. The power amplifier amplitude and phase consistency debugging device of claim 1, wherein the FPGA unit comprises:
a calculation module for determining the maximum homodromous component of each power amplification unit and calculating the average value of each maximum homodromous component,
a reference selecting module which takes the channel where the power amplifying unit corresponding to the maximum homodromous component closest to the average value is positioned as a reference channel,
and the confirming module confirms the amplitude and the time delay correction factor of each channel according to the reference channel.
7. The apparatus according to claim 1, wherein the analog-to-digital conversion units are equal to the power amplification units of the power amplifier array.
8. A power amplifier amplitude and phase consistency debugging method is characterized by comprising the following steps:
generating a reference signal and equally dividing the reference signal into a plurality of paths of same signals;
the multi-path signals are respectively used as input signals of the amplitude-phase modulation unit and amplified and output through the corresponding power amplification units;
acquiring output signals of each power amplification unit;
performing analog-to-digital conversion on output signals of the power amplification units and determining amplitude and time delay correction factors of each power amplification unit;
the amplitude-phase modulation unit adjusts the input signals of the power amplification units according to the amplitude and time delay correction factors;
each power amplification unit respectively amplifies the adjusted signals;
and combining and outputting the output signals of the power amplification units.
9. The method for debugging amplitude-phase consistency of a power amplifier according to claim 8, wherein the method for determining the amplitude and delay correction factors comprises:
selecting a channel where a power amplification unit is located as a reference channel,
calculating the difference of the maximum homodromous component of each channel and the reference channel;
the selection method of the reference channel comprises the following steps:
determining the maximum homodromous component of each power amplification unit,
the average of the maximum isotropic components is calculated,
and taking the channel where the power amplification unit corresponding to the maximum homodromous component closest to the average value is located as a reference channel.
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| CN113030711B (en) * | 2021-05-26 | 2021-09-10 | 成都市克莱微波科技有限公司 | Power amplifier chip, chip testing system and method |
| CN114509972B (en) * | 2022-01-21 | 2024-04-12 | 中电科思仪科技股份有限公司 | Analog signal receiving channel delay measuring device and measuring method |
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|---|---|
| CN112583360A (en) | 2021-03-30 |
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