CN112582267B - Method for forming a semiconductor device - Google Patents

Abstract

The embodiment of the invention provides a method for forming a semiconductor device. In the embodiment of the invention, the upper surface of the control dummy gate is higher than the upper surface of the dielectric layer, and the mask layer with different materials from the dielectric layer is formed above the dielectric layer and the dummy gate, so that the depth of the groove formed above the dummy gate in the preset area can be accurately controlled, the stop layer formed later can be ensured not to cover the dummy gate, the dummy gate residue caused by the stop layer covering the dummy gate is avoided, the short circuit of a semiconductor device can be avoided, and the reliability of the semiconductor device is ensured.

Description

Method for forming a semiconductor device

Technical Field

The present invention relates to the field of semiconductor technology, and in particular to a method for forming a semiconductor device.

Background Art

With the continuous development of semiconductor manufacturing technology, the integration of semiconductor devices is getting higher and higher, and the characteristic size of semiconductor devices is gradually shrinking. However, the performance of semiconductor devices still needs to be improved.

Summary of the invention

In view of this, an embodiment of the present invention provides a method for forming a semiconductor device to improve the performance of the semiconductor device.

The method described in the embodiment of the present invention includes:

Providing a front-end device layer, wherein the front-end device layer includes a dummy gate;

forming a dielectric layer covering the sidewalls and top of the dummy gate;

Etching back the dielectric layer until the upper surface of the dielectric layer is lower than the upper surface of the dummy gate;

forming a mask layer on the dielectric layer and the dummy gate;

Patterning the mask layer to form a groove exposing the top of the dummy gate in a predetermined area;

forming a stop layer, wherein the stop layer at least covers the sidewall of the groove;

The dummy gate in a predetermined area is removed to form an isolation structure.

Furthermore, the etch-back makes the upper surface of the dielectric layer lower than the upper surface of the dummy gate by 5 nanometers to 10 nanometers.

Furthermore, the mask layer and the dielectric layer are made of different materials.

Furthermore, the material of the mask layer is silicon nitride, and the material of the dielectric layer is silicon dioxide.

Furthermore, the thickness of the mask layer is 10 nanometers to 100 nanometers.

Further, the forming of the stop layer is specifically:

An atomic layer deposition process is used to form a stop layer covering the sidewalls of the groove and the top of the dummy gate.

Furthermore, the size of the dummy gate is no greater than 10 nanometers.

Furthermore, the size of the groove is larger than the size of the dummy gate.

Furthermore, the material of the stop layer is silicon dioxide; and the material of the dummy gate is polysilicon.

Further, the removing of the dummy gate in the predetermined area is specifically:

The dummy gate is removed by using an etching process in which the etching rate of the dummy gate is greater than the etching rate of the stop layer.

In an embodiment of the present invention, the upper surface of the dummy gate is controlled to be higher than the upper surface of the dielectric layer, and a mask layer whose material is different from that of the dielectric layer is formed above the dielectric layer and the dummy gate. This can accurately control the depth of the groove formed above the dummy gate in a predetermined area, and can ensure that the subsequently formed stop layer does not cover the dummy gate, thereby avoiding dummy gate residues caused by the stop layer covering the dummy gate, thereby avoiding short circuits in the semiconductor device and ensuring the reliability of the semiconductor device.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

1 to 7 are schematic diagrams of structures formed in various steps of a method for forming a semiconductor device of a comparative example;

FIG8 is a photograph of a semiconductor device formed by a comparative example forming method;

9 is a flow chart of a method for forming a semiconductor device according to an embodiment of the present invention;

10 to 17 are schematic diagrams of structures formed in various steps of the method for forming a semiconductor device according to an embodiment of the present invention.

DETAILED DESCRIPTION

The present invention is described below based on embodiments, but the present invention is not limited to these embodiments. In the detailed description of the present invention below, some specific details are described in detail. It is possible for a person skilled in the art to fully understand the present invention without the description of these details. In order to avoid confusing the essence of the present invention, known methods, processes, flows, components and circuits are not described in detail.

In addition, persons of ordinary skill in the art will appreciate that the drawings provided herein are for illustration purposes and are not necessarily drawn to scale.

At the same time, it should be understood that in the following description, "circuit" refers to a conductive loop composed of at least one element or subcircuit through electrical connection or electromagnetic connection. When an element or circuit is said to be "connected to" another element or an element/circuit is said to be "connected between" two nodes, it can be directly coupled or connected to another element or there can be an intermediate element, and the connection between the elements can be physical, logical, or a combination thereof. On the contrary, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.

Unless the context clearly requires otherwise, words such as “include”, “including” and the like in this application document should be interpreted as including rather than being exclusive or exhaustive; that is, as meaning “including but not limited to”.

In the description of this application document, it should be understood that the terms "first", "second", etc. are used for descriptive purposes only and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, the meaning of "plurality" is two or more.

In the description of the present application document, it should be understood that the term "layer" is used in its broadest sense to include a film, a cover layer or the like, and one layer may include a plurality of sublayers.

In the description of the present application document, it is to be understood that conventional etching techniques known in the field of semiconductor manufacturing for selectively removing polysilicon, silicon nitride, silicon dioxide, metal, photoresist, polyimide or similar materials are mentioned throughout the specification, including, for example, wet chemical etching, reactive ion (plasma) etching (RIE), washing, wet cleaning, pre-cleaning, spray cleaning, chemical mechanical polishing (CMP) and similar processes. Specific embodiments are described herein with reference to examples of such processes. However, the present disclosure and reference to specific deposition techniques should not be limited to those described. In some examples, two such techniques may be interchangeable. For example, stripping the photoresist may include immersing the sample in a wet chemical bath or alternatively spraying the wet chemical directly on the sample.

“Spanning” means that, for example, the gate structure spans the fin, indicating that the dummy gate structure covers part of the top surface and part of the sidewall surface of the fin, and the dummy gate structure and the fin have a cross positional relationship, and the height of the dummy gate structure is greater than the height of the fin.

Semiconductor devices are electronic devices with conductivity between good conductors and insulators. They use the special electrical properties of semiconductor materials to perform specific functions. They can be used to generate, control, receive, transform, amplify signals and perform energy conversion. Commonly used semiconductor devices include Fin Field-Effect Transistor (Fin-FET).

FinFET is a new type of complementary metal oxide semiconductor transistor, which generally includes a fin protruding from the surface of a semiconductor substrate, a gate structure covering part of the top surface and sidewalls of the fin, and source and drain doped regions in the fin on both sides of the gate structure. This design can improve circuit control and reduce leakage current, shortening the gate length of the transistor.

FIG1 is a schematic diagram of the structure of a semiconductor device including a fin field effect transistor, and FIG2 is a three-dimensional structure diagram of FIG1 in area 4. Referring to FIG1-FIG2, the field effect transistor in the figure includes a fin 1, a dummy gate 2, and a groove 3 (also referred to as P2 CUT) between the dummy gate 2. The groove 3 is used to isolate the ends of two adjacent dummy gates 2. However, due to the limitations of the etching process, it is easy for the groove 3 to fail to successfully isolate two adjacent dummy gates.

3 to 7 are schematic diagrams of structures formed by various steps of a method for forming a semiconductor device of a comparative example. Referring to FIG. 3 to 7 , the method for forming a semiconductor device of a comparative example includes the following steps:

Step S1, providing a front-end device layer.

Step S2: forming a dielectric layer covering the sidewalls and top of the dummy gate.

Step S3: patterning the dielectric layer to form a groove exposing the top of the dummy gate in a predetermined area.

Step S4: forming a stop layer, wherein the stop layer at least covers the sidewall of the groove.

Step S5: removing the dummy gate in a predetermined area to form an isolation structure.

Referring to FIG. 3 , in step S1 , a front-end device layer is provided.

Specifically, the front-end device layer includes a fin 1 and a dummy gate 2 .

Fig. 4 is a cross section of the structure along line AA. Referring to Fig. 4 , in step S2 , a dielectric layer 5 is formed to cover the sidewalls and top of the dummy gate 2 .

5 , in step S3 , the dielectric layer 5 is patterned to form a groove 6 exposing a predetermined area of the top of the dummy gate 2 .

6 , in step S4 , a stop layer 7 is formed, and the stop layer 7 at least covers the sidewall of the groove 6 .

Referring to FIG. 7 , in step S5 , the dummy gate 2 in a predetermined area is removed to form an isolation structure 3 .

A portion of the dummy gate 2 will remain on both sides of the isolation structure 3 . When the dummy gate is subsequently replaced with a gate, a short circuit may occur in the semiconductor device, resulting in reduced reliability of the semiconductor device.

Fig. 8 is a photograph of a semiconductor device formed by a comparative example forming method. As shown in Fig. 8, two gates that should be electrically isolated from each other are electrically connected to each other, resulting in a short circuit.

In view of this, in order to improve the performance of semiconductor devices. An embodiment of the present invention provides a method for forming a semiconductor device. In the embodiment of the present invention, the formation of a fin field effect transistor is taken as an example for explanation. Furthermore, the method of the embodiment of the present invention can be used to form a fin field effect transistor at a 14nm process node and below a 14nm process node, for example, to form a 14nm or 7nm field effect transistor. Furthermore, the method of forming a fin field effect transistor by the method of the embodiment of the present invention can also be used to form other semiconductor devices such as complementary metal oxide semiconductors (CMOS), NAND flash memories (NAND flash memories) and static random access memories (SRAM).

FIG9 is a flow chart of a method for forming a semiconductor device according to an embodiment of the present invention. As shown in FIG9 , the method for forming a semiconductor device according to an embodiment of the present invention includes the following steps:

Step S100: providing a front-end device layer, wherein the front-end device layer includes a dummy gate.

Step S200 , forming a dielectric layer covering the sidewalls and top of the dummy gate.

Step S300 , etching back the dielectric layer until the upper surface of the dielectric layer is lower than the upper surface of the dummy gate.

Step S400: forming a mask layer on the dielectric layer and the dummy gate.

Step S500: patterning the mask layer to form a groove exposing the top of the dummy gate in a predetermined area.

Step S600: forming a stop layer, wherein the stop layer at least covers the sidewall of the groove.

Step S700: removing the dummy gate in a predetermined area to form an isolation structure.

10 to 17 are schematic diagrams of structures formed in various steps of the method for forming a semiconductor device according to an embodiment of the present invention.

Fig. 10 is a three-dimensional structural diagram of the front-end device layer. Fig. 11 is a cross-sectional schematic diagram along line BB of Fig. 10. Referring to Fig. 10 and Fig. 11, in step S100, a front-end device layer 10 is provided, and the front-end device layer 10 includes a dummy gate 12.

In an optional implementation, the front-end device layer 10 includes a plurality of discrete fins 11 and a dummy gate 12 spanning the fins 11. The plurality of fins 11 are parallel or substantially parallel. In this embodiment, the dummy gate 12 is made of polysilicon.

In an optional implementation, the size of the dummy gate is not greater than 10 nanometers. The size of the dummy gate represents the width of the dummy gate 12 in the cross section shown in Fig. 11. In this embodiment, the width of the dummy gate is 7 nm.

As shown in Fig. 11, a hard mask layer 12a may be further included above the dummy gate 12, and the hard mask layer 12a is used as a mask in the process of forming the dummy gate 12. In this embodiment, the material of the hard mask layer 12a is silicon nitride.

Specifically, the front-end device layer 10 provided in step S100 may include a silicon single crystal substrate, a germanium single crystal substrate or a silicon germanium single crystal substrate. Alternatively, the front-end device layer 10 may also include a silicon-on-insulator (SOI) substrate, a stacked silicon-on-insulator (SSOI), a stacked silicon-germanium-on-insulator (S-SiGeOI), a silicon-germanium-on-insulator (SiGeOI), a germanium-on-insulator (GeOI), a substrate of an epitaxial layer structure on silicon, a compound front-end device layer or an alloy front-end device layer. The compound front-end device layer includes silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium dysprosium, the alloy front-end device layer includes SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP or a combination thereof, the SOI substrate includes a semiconductor layer (such as a silicon layer, a silicon germanium layer, a carbon silicon layer or a germanium layer) disposed on an insulating material layer, the semiconductor layer has active devices and passive devices, and the insulating material layer protects the active devices and passive devices disposed on the semiconductor layer. Several structures such as epitaxial interface layers or strained layers can also be formed on the surface of the front-end device layer to improve the electrical performance of the semiconductor device.

In an optional implementation, the front-end device layer 10 also includes a shallow trench isolation structure (not shown in the figure). The shallow trench isolation structure fills the bottom of the trench formed by the adjacent fins 11. The shallow trench isolation structure is used for electrical isolation between adjacent fins. The material of the shallow trench isolation structure 13 can be silicon dioxide ( _SiO2 ), silicon oxynitride (SiON) or silicon oxycarbide (SiOC). The material of the shallow trench can also be a low-K dielectric material (dielectric constant greater than or equal to 2.5 and less than 3.9) or an ultra-low-K dielectric material (dielectric constant less than 2.5). In this embodiment, the material of the shallow trench isolation structure 13 is silicon dioxide.

It should be understood that the fins in the embodiment of the present invention may also have other different shapes, such as a trapezoid with a top width smaller than a bottom width, a rhombus, etc. The shape of the fins can be adjusted according to process conditions and application scenarios.

Referring to FIG. 12 , in step S200 , a dielectric layer 20 is formed to cover the sidewalls and top of the dummy gate.

In an optional implementation, before forming the dielectric layer 20, the method described in the embodiment of the present invention also includes: forming a side wall (not shown in the figure) on the side wall of the pseudo gate 13; and lightly doping ion implantation in the fins 11 on both sides of the pseudo gate 13 and the side wall to form a source and drain doping region.

In an optional implementation, the method for forming the dielectric layer 20 includes: forming a dielectric material layer covering the upper surface and sidewalls of the dummy gate 13 on the isolation layer 12, wherein the entire surface of the dielectric material layer is higher than the top surface of the dummy gate 13; removing the dielectric material layer above the top surface of the dummy gate 13 to expose the top of the dummy gate 13, thereby forming the dielectric layer 20. The removal of the dielectric material layer above the top surface of the gate structure 13 can be achieved by chemical mechanical polishing.

Specifically, the dielectric material layer is formed by chemical vapor deposition (CVD), such as low temperature chemical vapor deposition (LTCVD), plasma chemical vapor deposition (PCVD), low pressure chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (RTCVD), plasma enhanced chemical vapor deposition (PECVD), and fluid chemical vapor deposition (FCVD).

The material of the dielectric layer 20 may be silicon dioxide (SiO ₂ ), silicon oxynitride (SiON), silicon nitride (Si ₃ N ₄ ) or silicon oxycarbide (SiOC). In this embodiment, the material of the dielectric layer 20 is silicon dioxide.

After the dielectric layer 20 is deposited, a chemical mechanical polishing process is used to polish the upper surface of the dielectric layer 20 so that the upper surface of the dielectric layer 20 is substantially flush with the upper surface of the hard mask 12 a .

13 , in step S300 , the dielectric layer 20 is etched back until the upper surface of the dielectric layer 20 is lower than the upper surface of the dummy gate 12 .

The back etching makes the upper surface of the dielectric layer lower than the upper surface of the dummy gate by 5 nanometers to 10 nanometers.

Specifically, the back etching can be dry etching or wet etching. The etching rate of the back etching on the dielectric layer 20 is greater than the etching rate on the pseudo gate 12. In this embodiment, a dry etching process is used to back-etch the dielectric layer 20. The process parameters of the back etching are: CHF ₃ flow rate is 50sccm-500sccm, O ₂ flow rate is 0sccm-200sccm, chamber pressure is 2mTorr-100mTorr, source power is 200W-1000W, and bias power is 0W-200W.

In an optional implementation, the hard mask 12a may be removed before or after etching back the dielectric layer 20. Specifically, the hard mask 12a may be removed by dry etching or wet etching.

In this step, the dielectric layer is etched back until the upper surface of the dielectric layer is lower than the upper surface of the dummy gate, so as to form a mask layer with a material different from that of the dielectric layer in the subsequent process, thereby better controlling the size of the groove formed in the subsequent process and avoiding dummy gate residue.

14 , in step S400 , a mask layer 30 is formed on the dielectric layer 20 and the dummy gate 12 .

Specifically, the mask layer 30 and the dielectric layer 20 are made of different materials. Further, the mask layer is made of silicon nitride. The thickness of the mask layer 30 is 10 nanometers to 100 nanometers.

In an optional implementation, an isolation layer 30a is further formed above the mask layer 30. The isolation layer 30a is used to act as a mask when the mask layer 30 is subsequently patterned, so as to ensure the size of the grooves formed subsequently.

Specifically, the mask layer 30 and the isolation layer 30a may be formed by chemical vapor deposition, such as low-temperature chemical vapor deposition, plasma chemical vapor deposition, low-pressure chemical vapor deposition, rapid thermal chemical vapor deposition, plasma enhanced chemical vapor deposition, and fluid chemical vapor deposition.

The material of the mask layer formed in this step is different from the material of the dielectric layer. When the mask layer is subsequently patterned to form a groove exposing the top of the pseudo gate, the mask layer is etched at a rate greater than the dielectric layer etching rate in the same etching process. The dielectric layer can act as an etching stop layer and can better control the etching depth.

15 , in step S500 , the mask layer 30 is patterned to form a groove 40 exposing a predetermined area of the top of the dummy gate 12 .

Specifically, the mask layer 30 may be patterned by a photolithography process. A patterned photoresist is first formed on the mask layer 30a, and then the isolation layer 30a is etched using the photoresist as a mask. The pattern of the photoresist is transferred to the isolation layer 30a, and then the mask layer 30 is etched using the isolation layer 30a as a mask. By forming the isolation layer 30a on the mask layer 30, the size of the groove 40 can be better controlled.

Specifically, the etching process for etching the mask layer 30 may be dry etching or wet etching, and specifically, an etching process with a higher etching rate for the mask layer 30 than for the dielectric layer 20 may be selected. In other words, an etching process with a higher etching selectivity for the dielectric layer 20 may be selected.

The size of the groove 40 is greater than the size of the dummy gate 12. The size distribution of the groove 40 and the dummy gate 12 is the width of the groove 40 and the dummy gate 12 in the cross section shown in FIG. 15 .

The groove is above the dummy gate between two adjacent fins, and the groove exposes a section of the dummy gate. Forming a groove with a width greater than the gate can avoid the problem that the dummy gate cannot be completely removed later because the distance between the side walls of the groove is smaller than the dummy gate, so that a part of the dummy gate remains and the dummy gate cannot be divided into two electrically isolated parts.

Since semiconductor devices have a high degree of integration, the increase in the groove can easily lead to the destruction of the pseudo gate or fin around the groove, resulting in reduced reliability of the semiconductor device. However, in the process of forming the semiconductor device in the embodiment of the present invention, in the process of forming the groove by the photolithography process, because an etching process with a high etching selectivity ratio for the dielectric layer is selected, the dielectric layer acts as an etching stop layer, which can control the depth of the groove. The width of the groove is made larger than the width of the pseudo gate, and the depth of the groove can be well controlled. Avoiding the damage of the adjacent pseudo gate or fin due to the direct increase in the groove width can ensure the reliability of the semiconductor device.

16 , in step S600 , a stop layer 50 is formed. The stop layer 50 at least covers the sidewall of the groove.

Specifically, forming the stop layer includes the following steps:

Step S601 : forming a stop layer covering the sidewalls of the groove and the top of the dummy gate by an atomic layer deposition (ALD) process.

Atomic layer deposition is a method that can deposit materials layer by layer on the surface of a substrate in the form of a single atomic film. Atomic layer deposition is similar to ordinary chemical vapor deposition. However, during the atomic layer deposition process, the chemical reaction of a new layer of atomic film is directly related to the previous layer, so that only one layer of atoms is deposited each time. Atomic layer deposition technology is based on surface self-limitation and self-saturation adsorption reactions, and has surface control. The prepared thin film has excellent three-dimensional conformality and large-area uniformity. It is suitable for deposition and film formation on complex high-aspect ratio substrate surfaces, while also ensuring precise sub-monolayer film thickness control.

Therefore, the stop layer formed by the atomic layer deposition process has good compactness and thin thickness. In an optional implementation, the thickness of the stop layer is 1nm-10nm. In this embodiment, the thickness of the stop layer is 3nm.

Step S602 , etching back the stop layer 50 .

Specifically, the stop layer 50 is etched using an anisotropic etching process. Since the etching rate of the anisotropic etching in the vertical direction is greater than the etching rate in the horizontal direction, the stop layer 50 covering the sidewall of the groove is formed.

The stop layer is used to better control the size of the groove in the subsequent process of removing the dummy gate, avoid the etched dummy gate from being too long, and control the relative position between the subsequently formed isolation structure and the fin, thereby ensuring the reliability of the semiconductor device.

In this step, since the height of the dummy gate is higher than the dielectric layer, the thickness of the stop layer above the dummy gate is less than the thickness of the stop layer above the dielectric layer in the groove. Therefore, when the stop layer is etched back, the stop layer above the dummy gate is completely removed before the dielectric layer above the dielectric layer, and no stop layer will remain on the dummy gate. In the subsequent process of removing the dummy gate in the predetermined area, it can be ensured that the dummy gate is completely removed. The short circuit caused by the residual dummy gate in the comparative example can be avoided, and the reliability of the semiconductor device can be ensured.

Referring to FIG. 17 , in step S700 , the dummy gate in a predetermined area is removed to form an isolation structure.

Specifically, the dummy gate is removed by an etching process in which the etching rate of the dummy gate is greater than the etching rate of the stop layer. Optionally, the dummy gate in the predetermined area can be removed by wet etching or dry etching. In this embodiment, the dummy gate is removed by anisotropic dry etching or wet etching.

In an optional implementation, the dummy gate 13 and the extension layer are removed by etching. The etching is performed by a dry etching process, and the process parameters of the dry etching process are: HBr flow rate is 50sccm-500sccm, NF3 flow rate is 0sccm-50sccm, O2 flow rate is 0sccm-50sccm, He flow rate is 0sccm-200sccm, Ar flow rate is 0sccm-500sccm, chamber pressure is 2mTorr-100mTorr, source power is 200W-1000W, and bias power is 0W-200W.

In another optional implementation, the dummy gate is etched using 2%-10% tetramethylammonium hydroxide (TMAH) by mass.

During the etching process, the stop layer is used to limit the size of the predetermined area. At the same time, an anisotropic etching process is used to ensure that the side walls of the isolation structure are basically perpendicular to the horizontal plane, avoid etching the dummy gate in the horizontal direction, ensure the accurate removal of the dummy gate in the predetermined area, and ensure that after etching, the relative position between the dummy gate and the fin on both sides of the isolation structure formed meets the requirements, thereby ensuring the reliability of the semiconductor device.

In the subsequent process, a dielectric layer is filled between the isolation structures to form two separate dummy gates. In the subsequent process, the separate dummy gates are replaced with metal gates. A conductive via is formed that is electrically connected to the source and drain regions and the metal gate. An interconnection structure is formed that is electrically connected to the conductive via. The formed semiconductor structure is packaged to form a complete semiconductor device.

In an embodiment of the present invention, the upper surface of the dummy gate is controlled to be higher than the upper surface of the dielectric layer, and a mask layer whose material is different from that of the dielectric layer is formed above the dielectric layer and the dummy gate. This can accurately control the depth of the groove formed above the dummy gate in a predetermined area, and can ensure that the subsequently formed stop layer does not cover the dummy gate, thereby avoiding dummy gate residues caused by the stop layer covering the dummy gate, thereby avoiding short circuits in the semiconductor device and ensuring the reliability of the semiconductor device.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims (9)

1. A method of forming a semiconductor device, the method comprising:

providing a front-end device layer, wherein the front-end device layer comprises a dummy gate;

forming a dielectric layer covering the side wall and the top of the dummy gate;

etching the dielectric layer until the upper surface of the dielectric layer is lower than the upper surface of the dummy gate;

Forming a mask layer on the dielectric layer and the dummy gate;

patterning the mask layer to form a groove exposing the top of the dummy gate in a preset area, wherein the size of the groove is larger than that of the dummy gate;

forming a stop layer, wherein the stop layer at least covers the side wall of the groove;

and removing the dummy gate in the preset area to form an isolation structure.

2. The method of claim 1, wherein the etching back is performed such that an upper surface of the dielectric layer is 5 nm-10 nm lower than an upper surface of the dummy gate.

3. The method of forming a semiconductor device according to claim 1, wherein materials of the mask layer and the dielectric layer are different.

4. The method of claim 3, wherein the mask layer is silicon nitride and the dielectric layer is silicon dioxide.

5. The method of forming a semiconductor device according to claim 1, wherein a thickness of the mask layer is 10 nm to 100 nm.

6. The method for forming a semiconductor device according to claim 1, wherein the formation stop layer is specifically:

and forming a stop layer covering the side wall of the groove and the top of the pseudo gate by adopting an atomic layer deposition process.

7. The method of forming a semiconductor device according to claim 1, wherein a size of the dummy gate is not more than 10 nm.

8. The method for forming a semiconductor device according to claim 1, wherein a material of the stopper layer is silicon dioxide; the dummy gate is made of polysilicon.

9. The method of forming a semiconductor device according to claim 1, wherein the removing the dummy gate of the predetermined region is specifically:

And removing the dummy gate by adopting an etching process with the etching rate of the dummy gate being greater than that of the stop layer.