CN112542516B - Active switch, manufacturing method thereof and display panel - Google Patents

Abstract

The application discloses an active switch, a manufacturing method thereof and a display panel, wherein the active switch comprises a substrate, a buffer layer, an active layer, a grid insulating layer, a first grid, a second grid, a passivation layer, a source electrode and a drain electrode which are stacked in sequence, the active layer is composed of indium gallium zinc oxide, and the first grid and the second grid are arranged in parallel and are positioned between the source electrode and the drain electrode; the source electrode and the drain electrode penetrate through the passivation layer and are respectively connected with two ends of the active layer. According to the active switch with the double-top gate structure, the parallel double-top gates are equivalent to the two cascaded active switches controlled by the same gate signal, and the double-top gate structure can enable off-state leakage current to be obviously reduced without affecting on-state current, so that the control capability of the grid can be improved, the leakage effect of the TFT is improved, and the stability of the InGaZn oxide active layer is improved.

Description

An active switch and its manufacturing method and display panel

Technical field

The present application relates to the field of display technology, and in particular to an active switch, a manufacturing method thereof, and a display panel.

Background technique

In the field of liquid crystal display, the active layer of thin film transistors has always used silicon-based materials with excellent stability and processing performance. Silicon-based materials are mainly divided into amorphous silicon and polycrystalline silicon. The mobility of amorphous silicon materials is very low, and Although polycrystalline silicon material has a high mobility, devices made with it have poor uniformity, low yield, and high unit price. Therefore, in recent years, technology in which a transparent oxide semiconductor film is used in a channel formation region to manufacture thin film transistors (TFTs) and is applied to electronic devices and optical devices has attracted widespread attention. Among them, in particular, field effect transistors using amorphous In-Ga-Zn-O (indium gallium zinc oxide, IGZO)-based materials containing indium, gallium, zinc, and oxygen as constituent elements are With higher mobility and larger switching ratio, it is more valued.

However, since indium gallium zinc oxide has an amorphous structure, the presence of oxygen vacancies in the film will increase the carrier concentration of the film, making the characteristics of the active layer unstable and resulting in poor performance of the thin film transistor.

Contents of the invention

The purpose of this application is to provide an active switch, a manufacturing method thereof, and a display panel to improve the stability of the indium gallium zinc oxide active layer.

The application discloses an active switch, which includes a substrate, a buffer layer, an active layer, a gate insulating layer, a first gate, a second gate, a passivation layer, a source and a drain stacked in sequence. The active layer is composed of indium gallium zinc oxide; the first gate electrode and the second gate electrode are arranged side by side and between the source electrode and the drain electrode; the passivation layer is arranged on the first gate electrode and above the second gate electrode; the source electrode and the drain electrode penetrate the passivation layer, and are respectively connected to both ends of the active layer through via holes provided in the passivation layer.

Optionally, the first gate and the second gate are arranged on the same layer.

Optionally, the active layer includes a first doped region, a second doped region, a third doped region, a first non-doped region and a second non-doped region, and the first doped region is configured Between the first undoped region and the second undoped region, the first undoped region is disposed between the first doped region and the second doped region, and the second undoped region A doped region is provided between the first doped region and the third doped region; the gate insulating layer includes a first gate insulating layer and a second gate insulating layer, and the first gate insulating layer Overlapping the first non-doped region, the second gate insulating layer overlaps the second non-doped region.

Optionally, the first gate insulating layer overlaps the first gate, and the second gate insulating layer overlaps the second gate.

Optionally, the gate insulating layer includes a stacked third gate insulating layer and a fourth gate insulating layer, the third insulating layer being disposed between the fourth insulating layer and the active layer. .

Optionally, the first doped region, the second doped region and the third doped region are all N-type highly doped regions.

Optionally, the widths of the first gate and the second gate are equal.

This application also discloses a method for making an active switch, which includes the steps:

forming a buffer layer on the substrate;

forming an indium gallium zinc oxide type active layer on the buffer layer;

forming a gate insulating layer on the active layer;

forming a first gate and a second gate on the gate insulating layer;

Highly doping the area of the active layer except the overlapping portions with the first gate, the second gate and the gate insulating layer;

forming a passivation layer on the first gate and the second gate; and

Etching through holes on the passivation layer, and forming source electrodes and drain electrodes respectively connected to both ends of the active layer;

Wherein, the first gate electrode and the second gate electrode are arranged in parallel and located between the source electrode and the drain electrode.

Optionally, the step of simultaneously forming the first gate and the second gate on the gate insulating layer includes the steps;

forming a gate metal layer on the gate insulating layer;

Etching the gate metal layer into a first gate and a second gate; and

Etching the gate insulating layer into a first gate insulating layer and a second gate insulating layer using the first gate and the second gate as etching barrier layers;

Wherein, the first gate insulating layer has the same pattern as the first gate electrode, and the second gate insulating layer has the same pattern as the second gate electrode.

This application also discloses a display panel, which includes an active switch as described above, and pixels configured to display a picture. The active switch controls the pixels to turn on and off.

This application uses an active switch with a double top gate structure. The parallel double gates are equivalent to two cascaded active switches controlled by the same gate signal. When the double gate TFT is in the open state, its current size is the same as that of the same channel length. Single-gate TFT is consistent; in the off state, its leakage current is significantly smaller than that of a single gate; that is to say, compared with a single-gate active switch of the same channel length, the use of a double-gate structure can significantly reduce the off-state leakage current with almost no change. Affects the size of the on-state current, so the parallel double-gate active switch can improve the control ability of the gate, improve the leakage effect of TFT, and improve the stability of the indium gallium zinc oxide semiconductor; and in the double top gate structure, the gate It can also effectively block the impact of external light on the active layer and prevent leakage current.

Description of the drawings

The accompanying drawings are included to provide a further understanding of the embodiments of the application, and constitute a part of the specification for illustrating the embodiments of the application and together with the written description to explain the principles of the application. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without exerting any creative effort. In the attached picture:

Figure 1 is a schematic diagram of a display panel according to an embodiment of the present application;

Figure 2 is a schematic diagram of an active switch according to an embodiment of the present application;

Figure 3 is a schematic diagram of another active switch according to an embodiment of the present application;

Figure 4 is a flow chart of an active switch manufacturing method according to an embodiment of the present application.

Among them, 100. Display panel; 200. Active switch; 210. Substrate; 220. Buffer layer; 230. Active layer; 231. First doping region; 232. Second doping region; 233. Third doping region region; 234, first non-doped region; 235, second non-doped region; 240, gate insulating layer; 241, first gate insulating layer; 242, second gate insulating layer; 243, third gate 244, fourth gate insulating layer; 250, first gate; 260, second gate; 270, passivation layer; 280, source; 290, drain; 300, pixel.

Detailed ways

It should be understood that the terminology used and the specific structural and functional details disclosed here are only for describing specific embodiments and are representative. However, the present application can be specifically implemented in many alternative forms and should not be interpreted as merely are limited to the embodiments set forth herein.

In the description of the present application, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating relative importance or implicitly indicating the number of indicated technical features. Therefore, unless otherwise stated, features defined as “first” and “second” may explicitly or implicitly include one or more of the features; “plurality” means two or more. The term "comprises" and any variations thereof, means the non-exclusive inclusion of the possible presence or addition of one or more other features, integers, steps, operations, units, components and/or combinations thereof.

In addition, "center", "horizontal", "top", "bottom", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" The terms indicating the orientation or positional relationship, etc. are described based on the orientation or relative positional relationship shown in the drawings, and are only used to facilitate the simplified description of the present application, and do not indicate that the device or element referred to must have a specific orientation. , is constructed and operated in a specific orientation and therefore cannot be construed as a limitation on this application.

In addition, unless otherwise clearly stated and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection. , or it can be an electrical connection; it can be a direct connection, an indirect connection through an intermediate medium, or an internal connection between two components. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

The application is described in detail below with reference to the accompanying drawings and optional embodiments.

As shown in Figure 1, it is a schematic diagram of a display panel 100. The display panel 100 includes two array substrates and a color filter substrate arranged oppositely. An active switch 200 is provided on the array substrate. The active switch 200 Used to control the opening and closing of the pixels 300 in the display panel 100 . As shown in Figure 2, it is a schematic diagram of an active switch 200. The active switch 200 includes a substrate 210, a buffer layer 220, an active layer 230, a gate insulating layer 240, a first gate 250, and a third stacked in sequence. Two gates 260, a passivation layer 270, a source electrode 280 and a drain electrode 290. The active layer 230 is composed of indium gallium zinc oxide; the first gate 250 and the second gate 260 are arranged side by side and are passivated. The passivation layer 270 is separated and located between the source electrode 280 and the drain electrode 290; the source electrode 280 and the drain electrode 290 penetrate the passivation layer 270 and pass through the via holes provided in the passivation layer 270. , respectively connected to both ends of the active layer 230 . Since the oxide active layer 230 is an amorphous material, and oxygen vacancies are defect states related to the material structure, the presence of oxygen vacancies in the active layer 230 film will increase the concentration of carriers in the film, resulting in The characteristics of the active layer 230 are unstable; this application uses an active switch 200 with a double top gate structure. The parallel double gates are equivalent to two cascaded active switches controlled by the same gate signal. When the double gate TFT is in the open state , its current size is consistent with that of a single-gate TFT of equal channel length; in the off state, its leakage current is significantly smaller than that of a single-gate; that is to say, compared with a single-gate active switch of the same channel length, the use of a double-gate structure can make The off-state leakage current is significantly reduced and hardly affects the on-state current. Therefore, the parallel double-gate active switch can improve the control ability of the gate, improve the leakage effect of TFT, and improve the carrier mobility in the transistor. Effectively improve and reduce the threshold voltage drift caused by negative voltage bias and positive voltage bias, improve the electrical stability of the device and the stability of indium gallium zinc oxide.

In addition, the active switch 200 in this application adopts a top gate structure. Since in the bottom gate structure, external light can pass through the interlayer insulating layer and illuminate the metal oxide semiconductor layer, photoexcitation defects will occur under illumination conditions; when After an external voltage is applied to the metal oxide thin film transistor, these photoexcited defects will diffuse to the back channel area under the action of the external electric field, causing the back channel area to be affected and an interface state (referring to the energy at the semiconductor interface located in the forbidden band) to appear. level or energy band, which can exchange charges with the semiconductor in a very short period of time), which will cause a threshold voltage shift; with a top-gate structure, external light will be blocked by the gate and cannot illuminate the active layer. 230, thus reducing the impact of light on the active layer 230 of the device and maintaining the threshold voltage in a relatively stable state.

The first gate 250 and the second gate 260 are arranged in the same layer, so that the first gate 250 and the second gate 260 can be formed through a synchronous process, which reduces the preparation process and process cost. Moreover, the insulating layer also includes a first gate insulating layer 241 and a second gate insulating layer 242. The first gate insulating layer 241 has the same pattern as the first gate 250 (ie, on the lining). (the orthographic projection direction on the bottom coincides with each other), the second gate insulating layer 242 and the second gate 260 have the same pattern; in this embodiment, since the first gate 250 and the first gate insulating layer 241 completely overlaps, and the second gate 260 completely overlaps the second gate insulating layer 242; in this way, when the first gate insulating layer 241 and the second gate insulating layer 242 are etched, the first gate 250 and the second gate insulating layer 241 completely overlap. 260 can act as an etching barrier and reduce the process of etching the barrier. In addition, the widths of the first gate 250 and the second gate 260 are equal, so that the current and voltage in each gate are equal, which is beneficial to improving the gate control capability of the TFT.

Specifically, the active layer 230 includes a first doped region 231, a second doped region 232 and a third doped region 233 that do not overlap the first gate 250 and the second gate 260. The second doped region 232 is connected to the source electrode 280 , the third doped region 233 is connected to the drain electrode 290 , and the first doped region 231 is disposed between the second doped region 232 and the third doped region 232 . Between the three doping regions 233; by doping the portion of the active layer 230 that does not overlap the first gate 250 and the second gate 260, the doping area of the active layer 230 is increased, and the doping area of the active layer 230 is limited. electron migration to prevent leakage current; and the first doped region 231, the second doped region 232 and the third doped region 233 are spaced apart so that the doped parts in the active layer 230 are evenly distributed; The semiconductors in the first doped region 231, the second doped region 232 and the third doped region 233 are all N-type highly doped, which further reduces the generation of leakage current in the active layer 230, making the source-drain The pole 290 forms a good ohmic contact with the active layer 230, which improves the electrical performance of the active switch 200.

The active layer 230 further includes a first non-doped region 234 disposed between the first doped region 231 and the second doped region 232, and a first non-doped region 234 disposed between the second doped region 232 and a third doped region 232. The second undoped region 235 between the doped regions 233, the first gate insulating layer 241 and the first undoped region 234 overlap, the second gate insulating layer 242 and the second Undoped regions 235 overlap. In this way, the first gate insulating layer 241 and the second gate insulating layer 242 partially overlap the undoped active layer 230. When the active layer 230 is doped, the first gate insulating layer 241 and the second gate insulating layer 242 partially overlap. The polar insulating layer 242 can function as an etching barrier layer, reducing the process steps of etching the barrier layer.

Further, the first gate 250 overlaps the first non-doped region 234 (first channel) (that is, the first gate 250 and the first non-doped region 234 are in the The orthographic projection direction on the substrate 210 coincides with the second gate electrode 260 and the second non-doped region 235 (second channel) (that is, the second gate electrode 260 overlaps with the second non-doped region 235 (second channel)). The second non-doped region 235 coincides with the orthographic projection direction on the substrate 210). Since the accuracy of the non-doped part (channel) of the active layer 230 of the traditional bottom gate structure is mainly controlled by the photomask process and the etching process, this method will have problems such as over-etching and under-etching, making The accuracy of the channel is not high; on the contrary, through doping, there are no problems such as over-etching and under-etching. Even if there is an over-etching problem before doping, this error can be compensated for by subsequent doping; this application uses the first gate 250 and the second gate 260 are used as masks to dope the active layer 230, which can achieve higher channel size accuracy and improve channel quality than the bottom gate structure.

As shown in FIG. 3 , it is a schematic diagram of another active switch. The active switch 200 includes a substrate 210 , a buffer layer 220 , an active layer 230 , a gate insulation layer 240 , a first gate 250 , and a third stacked in sequence. Two gates 260, passivation layer 270, source electrode 280 and drain electrode 290, the active layer 230 is composed of indium gallium zinc oxide; the first gate 250 and the second gate 260 are arranged side by side and located at Between the source electrode 280 and the drain electrode 290; the source electrode 280 and the drain electrode 290 penetrate the passivation layer 270 and are respectively connected to both ends of the active layer 230. The first gate 250 and the second gate 260 have the same length and are arranged in the same layer; the gate insulating layer 240 includes a stacked third gate insulating layer 243 and a fourth gate insulating layer 244. The third insulating layer 243 is disposed between the fourth insulating layer 244 and the active layer 230; and the third gate insulating layer 243 overlaps the first gate 250 and the second gate 260 in the orthographic projection direction, The fourth gate insulating layer 244 overlaps the first gate 250 and the second gate 260 in the orthographic projection direction.

The third gate insulating layer 243 and the fourth gate insulating layer 244 may be made of the same material. For example, the third gate insulating layer 243 and the fourth gate insulating layer 244 may both be silicon nitride layers. Or a silicon oxide layer; it can also be made of different materials. For example, the third gate insulating layer 243 is a silicon nitride layer, and the fourth gate insulating layer 244 is a silicon oxide layer, or vice versa. The third gate insulating layer 243 and the fourth gate insulating layer 244 can be deposited on the active layer 230 through chemical vapor deposition technology, and the fourth gate insulating layer 244 is deposited after the third gate insulating layer 243 is cooled and solidified; by The stacked arrangement of the gate insulating layer 240 enables the gate insulating layer 240 to better adhere to the active layer 230 and prevents metal burrs on the surfaces of the first gate 250 and the second gate 260 from puncturing the gate insulating layer. 240, causing a leakage problem in the active switch 200.

In this application, the active layer 230 can be a single layer or a multi-layer structure. As for the atomic ratio of the active layer 230, it changes due to the size of the product and the size of the device; and the passivation layer 270 adopts oxidation. Silicon or silicon nitride and their composite materials can also be single-layer or multi-layer materials; and the source electrode 280 and the drain electrode 290 can be made of Al, CU, Mo, Ti, and their alloys and composite structures.

As shown in Figure 4, as another embodiment of the present application, a method for manufacturing an active switch is also disclosed, which is used to prepare the above-mentioned active switch. The manufacturing method includes the steps:

S1: Form a buffer layer on the substrate;

S2: Form an indium gallium zinc oxide type active layer on the buffer layer;

S3: Form a gate insulating layer on the active layer;

S4: Form a first gate and a second gate on the gate insulating layer;

S5: Highly dope the area of the active layer except the overlapping portions with the first gate, the second gate and the gate insulating layer;

S6: Form a passivation layer on the first gate and the second gate;

S7: Etch through holes on the passivation layer, and form source electrodes and drain electrodes respectively connected to both ends of the active layer.

By providing a method for manufacturing the above-mentioned double top gate active switch, the off-state leakage current of the active switch is significantly reduced without almost affecting the on-state current, thereby improving the electrical stability and gate control capability of the active switch; It can also effectively control electron migration, effectively improving electron mobility and on-state current; in addition, using the gate as a mask to dope the active layer can achieve higher channel size accuracy than the bottom gate structure, improving Channel quality.

Moreover, in step S4, there are also steps:

S41: Form a gate metal layer on the gate insulation layer;

S42: Etch the gate metal layer into a first gate and a second gate;

S43: Etch the gate insulating layer into a first gate insulating layer and a second gate insulating layer using the first gate and the second gate as etching barrier layers.

The first gate insulating layer has the same pattern as the first gate, and the second gate insulating layer has the same pattern as the second gate; in this way, the first gate and the second gate serve as When doping the active layer, the etching barrier layer can ensure the accuracy of the doping pattern.

It should be noted that the restrictions on each step involved in this plan are not considered to limit the order of the steps as long as they do not affect the implementation of the specific plan. The steps written in front can be executed first. It can also be executed later, or even simultaneously. As long as this solution can be implemented, it should be regarded as belonging to the protection scope of this application.

The technical solution of this application can be widely used in various display panels, such as TN (Twisted Nematic, twisted nematic) display panel, IPS (In-Plane Switching, plane conversion type) display panel, VA (VerticalAlignment, vertical alignment type) Display panels, MVA (Multi-Domain Vertical Alignment, multi-quadrant vertical alignment) display panels, of course, can also be other types of display panels, such as OLED (Organic Light-Emitting Diode, organic light-emitting diode) display panels, all of which are applicable to the above. plan.

The above content is a further detailed description of the present application in combination with specific optional implementation modes, and it cannot be concluded that the specific implementation of the present application is limited to these descriptions. For those of ordinary skill in the technical field to which this application belongs, several simple deductions or substitutions can be made without departing from the concept of this application, which should be regarded as falling within the protection scope of this application.

Claims (7)

1. An active switch, characterized in that it includes: substrate; A buffer layer arranged on the substrate; An active layer, composed of indium gallium zinc oxide, is provided on the buffer layer; A gate insulating layer is provided on the active layer; A first gate electrode is provided on the gate insulating layer; A second gate electrode is provided on the gate insulating layer; A passivation layer disposed above the first gate and the second gate; The source electrode is connected to one end of the active layer through a via hole provided in the passivation layer; and The drain electrode is connected to the other end of the active layer through a via hole provided in the passivation layer; Wherein, the first gate and the second gate are arranged in parallel and are located between the source and the drain; the parallel double gates are equivalent to two cascaded active switches controlled by the same gate signal; The first gate and the second gate are arranged on the same layer, and the width of the first gate and the second gate are equal; the insulating layer includes a first gate insulating layer and a second gate insulating layer. , the orthographic projection of the first gate insulating layer and the first gate on the substrate coincides with the orthogonal projection of the second gate insulating layer and the second gate on the substrate. Projections overlap. 2. An active switch according to claim 1, characterized in that the active layer includes a first doped region, a second doped region, a third doped region, a first non-doped region and a third Two non-doped regions, the first doped region is disposed between the first non-doped region and the second non-doped region, the first non-doped region is disposed between the first doped region and a second doped region, the second non-doped region being disposed between the first doped region and the third doped region; The first gate insulating layer overlaps the first non-doped region, and the second gate insulating layer overlaps the second non-doped region. 3. An active switch according to claim 1, characterized in that the gate insulating layer includes a stacked third gate insulating layer and a fourth gate insulating layer, and the third insulating layer is disposed on between the fourth insulating layer and the active layer. 4. An active switch according to claim 2, characterized in that the first doped region, the second doped region and the third doped region are all N-type highly doped regions. 5. A method for manufacturing the active switch applied to any one of the above claims 1-4, characterized in that it includes the steps: forming a buffer layer on the substrate; forming an indium gallium zinc oxide type active layer on the buffer layer; forming a gate insulating layer on the active layer; forming a first gate and a second gate on the gate insulating layer; Highly doping the area of the active layer except the overlapping portions with the first gate, the second gate and the gate insulating layer; forming a passivation layer on the first gate and the second gate; and Etching through holes on the passivation layer, and forming source electrodes and drain electrodes respectively connected to both ends of the active layer; Wherein, the first gate and the second gate are arranged in parallel and are located between the source and the drain; the parallel double gates are equivalent to two cascaded active switches controlled by the same gate signal. 6. The manufacturing method of an active switch according to claim 5, wherein the step of synchronously forming the first gate and the second gate on the gate insulating layer includes the step; forming a gate metal layer on the gate insulating layer; Etching the gate metal layer into a first gate and a second gate; and Etching the gate insulating layer into a first gate insulating layer and a second gate insulating layer using the first gate and the second gate as etching barrier layers; Wherein, the first gate insulating layer has the same pattern as the first gate electrode, and the second gate insulating layer has the same pattern as the second gate electrode. 7. A display panel, characterized in that it includes an active switch according to any one of claims 1 to 4, and pixels configured to display a picture, and the active switch controls the pixels to turn on and off.