CN112540944A - Parallel bus protocol and method for realizing data interaction between boards based on protocol - Google Patents
Parallel bus protocol and method for realizing data interaction between boards based on protocol Download PDFInfo
- Publication number
- CN112540944A CN112540944A CN202011474072.1A CN202011474072A CN112540944A CN 112540944 A CN112540944 A CN 112540944A CN 202011474072 A CN202011474072 A CN 202011474072A CN 112540944 A CN112540944 A CN 112540944A
- Authority
- CN
- China
- Prior art keywords
- cycle
- cnt
- read
- write
- cpu
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 18
- 230000003993 interaction Effects 0.000 title claims abstract description 10
- 238000012545 processing Methods 0.000 claims abstract description 11
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 238000013461 design Methods 0.000 claims description 3
- 238000004891 communication Methods 0.000 description 4
- 230000002860 competitive effect Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Information Transfer Systems (AREA)
- Communication Control (AREA)
Abstract
The invention discloses a parallel bus protocol and a method for realizing data interaction between boards based on the protocol, which is applied to a scene of performing data interaction between two editable logic devices across single boards by using a parallel data bus and a localbus bus of a CPU (central processing unit) so as to complete the access of the single board with the CPU to the single board without the CPU, wherein the parallel data bus comprises a clock signal line, an initial signal line and n parallel signal lines; the n-bit parallel signal line is used for transmitting a read-write indicating signal, a multi-bit address signal and a 16-bit data signal; the read/write state machine cycle of the parallel signal line is related to the value of 16/n, when the value of n is larger, the cycle of the state machine is smaller, and when the value of n is smaller, the cycle of the state machine is larger. Compared with the IFC bus, the parallel bus saves the cost of the connector in the number of buses; compared with serial buses such as SMI and the like, the access efficiency is greatly improved, and the limitation of accessing an address space does not exist.
Description
Technical Field
The invention relates to a network communication technology, in particular to a parallel bus protocol and a method for realizing data interaction between boards based on the protocol.
Background
Today, with the rapid development of low-end communication devices, manufacturers of communication devices are increasingly competitive, and not only are functions required to meet requirements, but also the cost is required to be competitive. In the current architecture of communication equipment, the functions of a single board are divided into: single boards such as main control, line card, interface card, backboard, etc. The main control board must have a CPU for configuring each chip of the main control board, but the interface card can not use the CPU in order to save cost, and the number of the interface cards in the system is large, if each interface card saves one CPU, the cost of the whole system shows an advantage. Interface card is when not using CPU, the configuration of each chip of this board still needs to be realized, this just needs main control board CPU's address, data, the chip selection, signals such as read-write enable send the interface card through the backplate, there is 20 multibit address lines after CPU's LOCALBUS bus decodes under the general condition, 16-bit data line and 4-bit reading, write, the chip selection, signals such as clock, if not encode and send the interface card through the backplate connector, can occupy 2-3 backplate connectors, so not only increased the connector cost but also can make the system device volume grow and then increase the cost of whole system device. At present, the most connector saving is that buses of two-wire coding and decoding such as SMI, I2C and the like are all serial, the data cycle of one-time reading and writing is long, for a huge system, more chips need to be configured for each single board, if the serial data bus is used for configuration for a long time, the version starting time of the whole system is long, the user experience is poor, and the performance requirements cannot be met in some link switching scenes.
In summary, the following steps: the problem that the cost of equipment is increased due to the use of a CPU in the prior art is solved, and the problems that the system is started, the link switching time is long and the like due to the fact that the period of reading and writing once data of a two-wire serial port protocol after the CPU is removed are solved.
Disclosure of Invention
The invention aims to solve the problems and provide a method for realizing the conversion of the parallel signal line into the code on a programmable logic device with a CPU single board and then realizing the conversion of the parallel signal line into the code on the programmable logic device without the CPU single board.
In order to achieve the purpose, the invention is realized by the following technical scheme: a parallel bus protocol is applied to a scene of performing data interaction between two editable logic devices crossing a single board by using a parallel data bus and a localbus bus of a CPU (central processing unit) so as to complete the access of the single board with the CPU to the single board without the CPU, wherein the parallel data bus comprises a clock signal line, an initial signal line and n parallel signal lines;
the clock signal line edge is used for reading and writing n-bit parallel signal lines;
the start signal line indicates the start of the read/write state machine with a low level or a high level;
the n-bit parallel signal line is used for transmitting a read-write indicating signal, a multi-bit address signal and a 16-bit data signal; the read/write state machine cycle of the parallel signal line is related to the value of 16/n, when the value of n is larger, the cycle of the state machine is smaller, and when the value of n is smaller, the cycle of the state machine is larger.
Further, n is a signal line greater than 1bit and less than or equal to 8 bits, and the assignment of n is based on the layout space and cost of the single board in the design.
Still further, n is 4.
In addition, the invention also provides a method for converting a single-board localbus bus with a CPU (central processing unit) into a 6-wire parallel bus protocol in data interaction among boards based on the parallel bus protocol, wherein the 6-wire parallel bus refers to 1 CLK (clock) signal wire, 1 frame starting signal wire frame and 4 parallel signal wires are used for transmitting a read-write flag bit, an address signal and a data signal, and the method comprises the following steps:
102, defining a 5-bit counting register R _ cycle _ cnt [4:0] and assigning an initial value of 0 to indicate a read-write state machine, and triggering the counting of a counter by using the effective signal edges of the localbus cs, rd and wr signals sent by a CPU; defining a 4-bit R _ ad [3:0] register, assigning an initial value of 0, and transmitting information such as address data to 4 parallel signal lines; defining 1bit R _ frame, assigning an initial value of 1, for transferring the signal to the frame start signal line frame;
103, when detecting that the cs and rd signals are valid, triggering an R _ cycle _ cnt counter to add 1, and meanwhile, judging that when the R _ cycle _ cnt is equal to 1, the R _ frame is assigned with 0 to mark the beginning of a read-write cycle, and the R _ ad is assigned with a read indication signal 4' h0 to indicate a CPU to read;
and step 110, ending the read-write period, entering an Idle state to wait for the start of the next read-write period, assigning 1 to the R _ frame, and keeping the R _ ad.
Corresponding to the method, the invention also provides a method for realizing the conversion of 6-wire parallel bus protocol to localbus of the single board without CPU in the data interaction between the boards based on the parallel bus protocol, wherein the 6-wire parallel bus refers to 1 CLK signal wire, 1 frame starting signal wire frame and 4 parallel signal wires are used for transmitting read-write flag bits, address signals and data signals; the method comprises the following steps:
step S101, after the system is powered on, the whole board logic is reset and subjected to reset-releasing processing, and all the counters and the state machine are operated by taking clk clocks sent by a single board with a CPU as reference;
step S102, defining a 5-bit counting register R _ cycle _ cnt [4:0] and assigning an initial value of 0 to indicate a read-write state machine, defining a read enable R _ rd _ en _ n, a write enable R _ wr _ en _ n, a chip select R _ lb _ cs _ n, a read valid signal R _ lb _ rd _ n, a write valid signal R _ lb _ wr _ n all assigned with 1, and defining a frame start signal R _ frame _ n assigned with 1; defining a register R _ ad with 4 bits to be assigned with an initial value of 0, wherein the register R _ ad is used for butting 4-wire parallel signal wires with a CPU single board;
step S103, assigning a frame starting signal frame sent by a single board with a CPU to R _ frame _ n, when the R _ frame _ n is detected to be equal to 0, assigning 1 to R _ cycle _ cnt, triggering a counter, and simultaneously judging the value of R _ ad; if R _ ad is equal to 4' h0, assigning R _ rd _ en _ n to be equal to 0, entering a read state machine, and executing S104; if R _ ad is equal to 4' h1, assigning R _ wr _ en _ n to be equal to 0, entering a write state machine, and executing S108;
step S104, entering a read state machine, assigning the register address of the 5 groups of 20 bits received by the R _ lb _ addr [19:0] when the R _ cycle _ cnt is equal to 1 to 5 to the R _ lb _ addr, and assigning 0 to the R _ lb _ cs _ n when the R _ cycle _ cnt is equal to 5;
step S105, when R _ cycle _ cnt is 6, assigning R _ lb _ rd _ n to 0;
step S106, after waiting a certain period, namely after meeting the address establishment time of the equipment of the board, setting the R _ lb _ cs _ n and the R _ lb _ rd _ n to be 1, simultaneously sending out the values of the corresponding address registers of the board from 1 group, and then sending out 3 groups, wherein the total number of the data is 16 bit;
step S107, when the R _ cycle _ cnt is other values, each defined register is in a holding state, and the reading cycle is finished;
step S108, entering a write state machine, assigning a register address of R _ cycle _ cnt equal to 1 to 5 for receiving 5 groups of 20 bits to R _ lb _ addr [19:0], receiving 4 groups of 16bit data when R _ cycle _ cnt is equal to 6 to 9, and setting R _ lb _ cs _ n to 0 when R _ cycle _ cnt is equal to 9;
step S109, when R _ cycle _ cnt is 10, R _ lb _ wr _ n is set to 0;
step S110, after waiting a certain period, the setup holding time of the EPLD register of the board or the setup holding time of other slave devices of the board needs to be met, and then R _ lb _ wr _ n is set to 1; setting R _ lb _ cs _ n to 1 in the next clock cycle;
step S111, when the R _ cycle _ cnt is other values, each defined register is in a holding state, and the write cycle is finished;
step S112, the read-write cycle is ended, the Idle state is entered to wait for the start of the next read-write cycle, the signals R _ rd _ en _ n, R _ wr _ en _ n, R _ lb _ cs _ n, R _ lb _ rd _ n, R _ lb _ wr _ n, and R _ frame _ n are all set to 1, indicating an invalid state, and R _ lb _ addr is maintained.
In conclusion, the invention has the following beneficial effects: compared with the existing IFC bus number output by the CPU and the serial bus access efficiency, the invention greatly improves. Compared with the IFC bus, the parallel bus saves the cost of the connector in the number of buses; compared with serial buses such as SMI and the like, the access efficiency is greatly improved, and the limitation of accessing an address space does not exist.
Drawings
FIG. 1 is a method for converting a single-board localbus bus with a CPU provided by the invention into a 6-wire parallel bus protocol of the invention;
FIG. 2 is a method for converting 6-wire parallel bus protocol to localbus on a single board without CPU provided by the present invention.
Detailed Description
The invention will be further described in detail with reference to examples of embodiments shown in the drawings to which, however, the invention is not restricted.
Based on the defects that the prior art has the defects that the cost of equipment is increased by accessing the localbus with the CPU, the bus access period is long without two lines of SMIs with the CPU and the like, the parallel coding and decoding bus provided by the invention has the advantages that the cost is saved, the access period is shortened, the access efficiency is improved and the like.
A parallel bus protocol is applied to a scene of performing data interaction between two editable logic devices crossing a single board by using a parallel data bus and a localbus bus of a CPU (central processing unit) so as to complete the access of the single board with the CPU to the single board without the CPU, wherein the parallel data bus comprises a clock signal line, an initial signal line and n parallel signal lines; the edge of the clock signal line is used for reading and writing the n-bit parallel signal line; the start signal line indicates the start of the read/write state machine with a low level or a high level; the n-bit parallel signal line is used for transmitting a read-write indicating signal, a multi-bit address signal and a 16-bit data signal; the period of a read-write state machine of the parallel signal line is related to the value of 16/n, when the value of n is larger, the period of the state machine is smaller, and when the value of n is smaller, the period of the state machine is larger;
in addition, n is a signal line with more than 1bit and less than or equal to 8 bits, the assignment of n is based on the layout space and cost of a single board in the design, and the following discussion is specifically made on the application of the parallel bus protocol of the present invention by taking n as 4:
specifically, as shown in fig. 1, in the method for converting a single board localbus bus with a CPU into a 6-line parallel bus protocol of the present invention, a 6-line parallel bus in this example refers to 1 CLK signal line, 1 frame start signal line frame, and 4 parallel signal lines for transmitting read-write flag bits, address signals, data signals, and the like.
Firstly, 101 is executed, after the system is powered on, the whole board logic is reset, and the reset processing is carried out. After the reset is released, the Localbus clock output by the CPU is assigned to the CLK signal line of the invention and is sent to other single boards. And all counters and state machine operations in this example are referenced to this clock.
Then executing 102, defining a 5-bit counting register R _ cycle _ cnt [4:0] and assigning an initial value of 0 to indicate a read-write state machine, and triggering the counting of a counter by using effective signal edges of localbus signals such as cs, rd and wr sent by a CPU; a register R _ ad [3:0] of 4 bits is defined, an initial value of 0 is assigned, and the register R _ ad [3:0] is used for transmitting information such as address data to the 4-bit parallel signal line; a 1bit R _ frame is defined, and an initial value of 1 is assigned for transferring a signal to the frame start signal line frame in the present invention.
103, when detecting that the cs, rd signals are valid, triggering the R _ cycle _ cnt counter to increment by 1, and meanwhile judging that when the R _ cycle _ cnt is equal to 1, the R _ frame is assigned with 0 to mark the beginning of the read-write cycle, and the R _ ad is assigned with a read indication signal 4' h0 to indicate the CPU to read.
And executing 105, after the address is sent, waiting for a certain number of clock cycles, specifically determining according to a slave device localbus reading time sequence, and after waiting for a certain period, sequentially receiving 4 groups of 16-bit data from the 4-bit parallel signal line to the CPU of the local board to finish the reading operation of the CPU.
106 when detecting cs, wr signal is effective, triggering the R _ cycle _ cnt counter to add 1, meanwhile judging when R _ cycle _ cnt is equal to 1, R _ frame is assigned 0 to mark the beginning of read-write period, R _ ad is assigned write indication signal 4' h1 to indicate CPU write.
When execution is carried out 107, R _ cycle _ cnt is 2 to 6, R _ ad assigns a register address of 5 sets of 20 bits to the slave.
And executing 108, after the address is sent, immediately when the R _ cycle _ cnt is equal to 7 to 10, assigning 4 groups of 16-bit data to the R _ ad, and sending the data to the slave device to finish the writing operation of the CPU.
109, when the read/write state machine is still running, R _ cycle _ cnt is other value, R _ frame hold, R _ ad hold, etc.
And when the read-write period is ended, entering Idle and waiting for the start of the next read-write period, assigning 1 to the R _ frame, and keeping the R _ ad.
As shown in FIG. 2, the method for converting 6-wire parallel bus protocol to localbus of a single board without CPU provided by the invention. The 6-wire parallel bus in this example refers to 1-bit CLK signal line, 1-bit frame start signal line frame, and 4-bit parallel signal lines for transmitting read-write flag bits, address signals, data signals, and the like.
S101 is executed firstly, after the system is powered on, the whole board logic is reset, and the reset processing is carried out. In this example, all the counters and the state machine are operated by referring to the clk clock sent from the board with the CPU.
Then executing S102, defining a 5-bit counting register R _ cycle _ cnt [4:0] and assigning an initial value of 0 to indicate a read-write state machine, defining a read enable R _ rd _ en _ n, a write enable R _ wr _ en _ n, a chip select R _ lb _ cs _ n, a read valid signal R _ lb _ rd _ n, a write valid signal R _ lb _ wr _ n and the like which are all assigned with 1, and defining a frame start signal R _ frame _ n which is assigned with 1; a register R _ ad with 4 bits is defined to be assigned with an initial value of 0 and is used for butting 4-wire parallel signal wires with a CPU single board.
S103, assigning a frame starting signal frame sent by the CPU single board to R _ frame _ n, and when the R _ frame _ n is detected to be equal to 0, assigning 1 to R _ cycle _ cnt, triggering a counter, and simultaneously judging the value of R _ ad. If R _ ad is equal to 4' h0, assigning R _ rd _ en _ n to be equal to 0, entering a read state machine, and executing S104; if R _ ad is equal to 4' h1, the value R _ wr _ en _ n is equal to 0, and the write state machine is entered to execute S108.
Execution of S104 enters the read state machine with R _ cycle _ cnt equal to 1 to 5 receive 5 sets of 20bit register address assignments to R _ lb _ addr [19:0], and R _ lb _ cs _ n assigns 0 when R _ cycle _ cnt equals 5.
And S105, when the R _ cycle _ cnt is 6, assigning the R _ lb _ rd _ n to 0.
S106, after waiting a certain period, namely meeting the address establishment time of the local board equipment, setting the R _ lb _ cs _ n and the R _ lb _ rd _ n to be 1, simultaneously sending out 1 group of values of the corresponding address register of the local board, and then sending out 3 groups of data with 16 bits.
S107, when the R _ cycle _ cnt has another value, each defined register is in a hold state. The read cycle ends.
S108, entering a write state machine, assigning a register address of R _ cycle _ cnt equal to 1 to 5 receiving 5 groups of 20 bits to R _ lb _ addr [19:0], receiving 4 groups of 16 bits data immediately after R _ cycle _ cnt equal to 6 to 9, and setting R _ lb _ cs _ n to 0 when R _ cycle _ cnt is equal to 9.
In S109, when R _ cycle _ cnt is 10, R _ lb _ wr _ n is set to 0.
S110, after waiting a certain period, the setup holding time of the EPLD register of the board or the setup holding time of other slave devices of the board needs to be met, and then R _ lb _ wr _ n is set to be 1; the next clock cycle sets R _ lb _ cs _ n to 1.
S111, when the R _ cycle _ cnt has another value, each defined register is in a hold state. The write cycle ends.
And S112, the read-write period is ended, Idle is started to wait for the start of the next read-write period, signals of R _ rd _ en _ n, R _ wr _ en _ n, R _ lb _ cs _ n, R _ lb _ rd _ n, R _ lb _ wr _ n, R _ frame _ n and the like are all set to be 1, an invalid state is indicated, and R _ lb _ addr is kept.
The above-mentioned embodiments are only for convenience of description, and are not intended to limit the present invention in any way, and those skilled in the art will understand that the technical features of the present invention can be modified or changed by other equivalent embodiments without departing from the scope of the present invention.
Claims (5)
1. A parallel bus protocol is applied to a scene of performing data interaction between two editable logic devices of a cross-single board by using a parallel data bus and a localbus bus of a CPU (central processing unit) so as to complete the access of the single board with the CPU to the single board without the CPU, and is characterized in that: the parallel data bus comprises a clock signal line, a starting signal line and n parallel signal lines;
the clock signal line edge is used for reading and writing n-bit parallel signal lines;
the start signal line indicates the start of the read/write state machine with a low level or a high level;
the n-bit parallel signal line is used for transmitting a read-write indicating signal, a multi-bit address signal and a 16-bit data signal; the read/write state machine cycle of the parallel signal line is related to the value of 16/n, when the value of n is larger, the cycle of the state machine is smaller, and when the value of n is smaller, the cycle of the state machine is larger.
2. A parallel bus protocol according to claim 1, wherein: n is a signal line with more than 1bit and less than or equal to 8 bits, and the assignment of n is based on the layout space and cost of the single board in the design.
3. A parallel bus protocol according to claim 2, wherein: n is 4.
4. A method for converting a single board localbus bus with a CPU into a 6-wire parallel bus protocol according to the parallel bus protocol of claim 3, characterized in that: the 6-wire parallel bus refers to 1 CLK signal wire, 1 frame starting signal wire frame and 4 parallel signal wires for transmitting read-write flag bits, address signals and data signals, and the method comprises the following steps:
step 101, after the system is powered on, resetting and resetting the logic of the whole board, and after the resetting is released, assigning a localbus clock output by a CPU to a CLK signal line and sending the clock to other single boards, wherein the clock is used as a reference for the running of all counters and state machines;
102, defining a 5-bit counting register R _ cycle _ cnt [4:0] and assigning an initial value of 0 to indicate a read-write state machine, and triggering the counting of a counter by using the effective signal edges of the localbus cs, rd and wr signals sent by a CPU; defining a 4-bit R _ ad [3:0] register, assigning an initial value of 0, and transmitting information such as address data to 4 parallel signal lines; defining 1bit R _ frame, assigning an initial value of 1, for transferring the signal to the frame start signal line frame;
103, when detecting that the cs and rd signals are valid, triggering an R _ cycle _ cnt counter to add 1, and meanwhile, judging that when the R _ cycle _ cnt is equal to 1, the R _ frame is assigned with 0 to mark the beginning of a read-write cycle, and the R _ ad is assigned with a read indication signal 4' h0 to indicate a CPU to read;
step 104, when the R _ cycle _ cnt is 2 to 6, the R _ ad assigns a register address of 5 groups of 20 bits to the slave device, and when the R _ cycle _ cnt is 2, the R _ frame assigns 1;
step 105, after sending the address, waiting for a certain number of clock cycles, specifically determining according to a slave device localbus reading time sequence, and after waiting for a certain period, sequentially receiving 4 groups of 16-bit data from 4 parallel signal lines to a local board CPU (central processing unit) to complete the reading operation of the CPU;
step 106, when detecting that the signals cs and wr are effective, triggering an R _ cycle _ cnt counter to add 1, and meanwhile judging that when the R _ cycle _ cnt is equal to 1, the R _ frame is assigned with 0 to mark the beginning of a read-write cycle, and the R _ ad is assigned with a write indication signal 4' h1 to indicate the CPU to write;
step 107, when the R _ cycle _ cnt is 2 to 6, the R _ ad assigns a register address of 5 groups of 20 bits to the slave device;
step 108, after the address is sent, immediately when the R _ cycle _ cnt is 7 to 10, R _ ad assigns 4 groups of 16-bit data, and sends the data to the slave device to complete the writing operation of the CPU;
step 109, when the read/write state machine is still running and the R _ cycle _ cnt is other value, the R _ frame is kept and the R _ ad is kept;
and step 110, ending the read-write period, entering an Idle state to wait for the start of the next read-write period, assigning 1 to the R _ frame, and keeping the R _ ad.
5. A method for implementing conversion of 6-wire parallel bus protocol to localbus by the parallel bus protocol without CPU board according to claim 3, characterized in that: the 6-wire parallel bus refers to 1 CLK signal wire, 1 frame starting signal wire frame and 4 parallel signal wires for transmitting read-write flag bits, address signals and data signals; the method comprises the following steps:
step S101, after the system is powered on, the whole board logic is reset and subjected to reset-releasing processing, and all the counters and the state machine are operated by taking clk clocks sent by a single board with a CPU as reference;
step S102, defining a 5-bit counting register R _ cycle _ cnt [4:0] and assigning an initial value of 0 to indicate a read-write state machine, defining a read enable R _ rd _ en _ n, a write enable R _ wr _ en _ n, a chip select R _ lb _ cs _ n, a read valid signal R _ lb _ rd _ n, a write valid signal R _ lb _ wr _ n all assigned with 1, and defining a frame start signal R _ frame _ n assigned with 1; defining a register R _ ad with 4 bits to be assigned with an initial value of 0, wherein the register R _ ad is used for butting 4-wire parallel signal wires with a CPU single board;
step S103, assigning a frame starting signal frame sent by a single board with a CPU to R _ frame _ n, when the R _ frame _ n is detected to be equal to 0, assigning 1 to R _ cycle _ cnt, triggering a counter, and simultaneously judging the value of R _ ad; if R _ ad is equal to 4' h0, assigning R _ rd _ en _ n to be equal to 0, entering a read state machine, and executing S104; if R _ ad is equal to 4' h1, assigning R _ wr _ en _ n to be equal to 0, entering a write state machine, and executing S108;
step S104, entering a read state machine, assigning the register address of the 5 groups of 20 bits received by the R _ lb _ addr [19:0] when the R _ cycle _ cnt is equal to 1 to 5 to the R _ lb _ addr, and assigning 0 to the R _ lb _ cs _ n when the R _ cycle _ cnt is equal to 5;
step S105, when R _ cycle _ cnt is 6, assigning R _ lb _ rd _ n to 0;
step S106, after waiting a certain period, namely after meeting the address establishment time of the equipment of the board, setting the R _ lb _ cs _ n and the R _ lb _ rd _ n to be 1, simultaneously sending out the values of the corresponding address registers of the board from 1 group, and then sending out 3 groups, wherein the total number of the data is 16 bit;
step S107, when the R _ cycle _ cnt is other values, each defined register is in a holding state, and the reading cycle is finished;
step S108, entering a write state machine, assigning a register address of R _ cycle _ cnt equal to 1 to 5 for receiving 5 groups of 20 bits to R _ lb _ addr [19:0], receiving 4 groups of 16bit data when R _ cycle _ cnt is equal to 6 to 9, and setting R _ lb _ cs _ n to 0 when R _ cycle _ cnt is equal to 9;
step S109, when R _ cycle _ cnt is 10, R _ lb _ wr _ n is set to 0;
step S110, after waiting a certain period, the setup holding time of the EPLD register of the board or the setup holding time of other slave devices of the board needs to be met, and then R _ lb _ wr _ n is set to 1; setting R _ lb _ cs _ n to 1 in the next clock cycle;
step S111, when the R _ cycle _ cnt is other values, each defined register is in a holding state, and the write cycle is finished;
step S112, the read-write cycle is ended, the Idle state is entered to wait for the start of the next read-write cycle, the signals R _ rd _ en _ n, R _ wr _ en _ n, R _ lb _ cs _ n, R _ lb _ rd _ n, R _ lb _ wr _ n, and R _ frame _ n are all set to 1, indicating an invalid state, and R _ lb _ addr is maintained.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011474072.1A CN112540944B (en) | 2020-12-15 | 2020-12-15 | Parallel bus protocol and method for realizing data interaction between boards based on protocol |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011474072.1A CN112540944B (en) | 2020-12-15 | 2020-12-15 | Parallel bus protocol and method for realizing data interaction between boards based on protocol |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112540944A true CN112540944A (en) | 2021-03-23 |
| CN112540944B CN112540944B (en) | 2022-11-25 |
Family
ID=75020138
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011474072.1A Active CN112540944B (en) | 2020-12-15 | 2020-12-15 | Parallel bus protocol and method for realizing data interaction between boards based on protocol |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112540944B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118585479A (en) * | 2024-08-02 | 2024-09-03 | 广东匠芯创科技有限公司 | Parallel interface signal transmission method based on configurable state signal and related equipment |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5099481A (en) * | 1989-02-28 | 1992-03-24 | Integrated Device Technology, Inc. | Registered RAM array with parallel and serial interface |
| US5668810A (en) * | 1995-04-26 | 1997-09-16 | Scientific-Atlanta, Inc. | Data transmission protocol method and apparatus |
| US5812881A (en) * | 1997-04-10 | 1998-09-22 | International Business Machines Corporation | Handshake minimizing serial to parallel bus interface in a data processing system |
| CN1558332A (en) * | 2004-01-18 | 2004-12-29 | 中兴通讯股份有限公司 | Device and method for implementing automatically reading and writing internal integrated circuit equipment |
| CN101399654A (en) * | 2007-09-25 | 2009-04-01 | 华为技术有限公司 | Serial communication method and apparatus |
| CN103714029A (en) * | 2013-05-07 | 2014-04-09 | 深圳市汇春科技有限公司 | Novel two-line synchronous communication protocol and application |
| CN104484301A (en) * | 2014-12-25 | 2015-04-01 | 南京因泰莱电器股份有限公司 | FPGA-based (Field Programmable Gate Array-based) IO (Input/Output) bus device with automatic recognition function |
| CN107766273A (en) * | 2017-11-09 | 2018-03-06 | 安徽皖通邮电股份有限公司 | Two line encoding and decoding and localbus mutually turn to realize the method for data interaction between plate |
-
2020
- 2020-12-15 CN CN202011474072.1A patent/CN112540944B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5099481A (en) * | 1989-02-28 | 1992-03-24 | Integrated Device Technology, Inc. | Registered RAM array with parallel and serial interface |
| US5668810A (en) * | 1995-04-26 | 1997-09-16 | Scientific-Atlanta, Inc. | Data transmission protocol method and apparatus |
| US5812881A (en) * | 1997-04-10 | 1998-09-22 | International Business Machines Corporation | Handshake minimizing serial to parallel bus interface in a data processing system |
| CN1558332A (en) * | 2004-01-18 | 2004-12-29 | 中兴通讯股份有限公司 | Device and method for implementing automatically reading and writing internal integrated circuit equipment |
| CN101399654A (en) * | 2007-09-25 | 2009-04-01 | 华为技术有限公司 | Serial communication method and apparatus |
| CN103714029A (en) * | 2013-05-07 | 2014-04-09 | 深圳市汇春科技有限公司 | Novel two-line synchronous communication protocol and application |
| CN104484301A (en) * | 2014-12-25 | 2015-04-01 | 南京因泰莱电器股份有限公司 | FPGA-based (Field Programmable Gate Array-based) IO (Input/Output) bus device with automatic recognition function |
| CN107766273A (en) * | 2017-11-09 | 2018-03-06 | 安徽皖通邮电股份有限公司 | Two line encoding and decoding and localbus mutually turn to realize the method for data interaction between plate |
Non-Patent Citations (1)
| Title |
|---|
| 范建荣等: "微处理器串行Flash接口设计", 《电脑知识与技术》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118585479A (en) * | 2024-08-02 | 2024-09-03 | 广东匠芯创科技有限公司 | Parallel interface signal transmission method based on configurable state signal and related equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112540944B (en) | 2022-11-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102831096B (en) | A kind of 1553B bus protocol IP kernel | |
| WO2021244194A1 (en) | Register reading/writing method, chip, subsystem, register group, and terminal | |
| CN109582623B (en) | Expansion board circuit capable of realizing cascade connection of multiple expansion boards of different types | |
| CN103092798B (en) | The method of the access means under SOC(system on a chip) and bus | |
| US20190356412A1 (en) | Fast termination of multilane double data rate transactions | |
| CN114610669B (en) | Method and system for realizing clock synchronization calibration in multi-channel serial port communication | |
| CN112564882B (en) | A single-wire digital communication interface based on AHB bus | |
| CN110765058A (en) | Method, system, equipment and medium for realizing SPI slave function by GPIO | |
| CN104320317B (en) | A kind of transfer approach and device of ethernet physical layer chip status | |
| CN115729879A (en) | Data frame format, chip communication method and chip | |
| CN115840592A (en) | Flash access method, controller, system and readable storage medium | |
| CN112540944B (en) | Parallel bus protocol and method for realizing data interaction between boards based on protocol | |
| CN114490467A (en) | Message processing DMA (direct memory access) system and method of multi-core network processor | |
| CN114817114A (en) | MIPI interface, control method, device and medium thereof | |
| CN107766273B (en) | Method for realizing data interaction between boards by two-line coding and decoding and localbus mutual conversion | |
| CN113534695B (en) | Tandem amplification device and tandem system including the same | |
| CN103488601B (en) | A kind of clock delay, data access method, system and equipment | |
| CN110856195B (en) | Configuration system and method of radio frequency assembly | |
| KR20170117326A (en) | Direct memory access control device for at least one processing unit having a random access memory | |
| TW202121181A (en) | Data transmission system | |
| CN117056262A (en) | Sensor circuit, sensing chip and single-wire cascade sensing system | |
| CN116166602A (en) | SPI-based SSI protocol data receiving method and system | |
| CN112015425A (en) | Data storage method, reading method, device, electronic device and storage medium | |
| CN114637718B (en) | USB multiplexing single-wire interface unit, chip and communication system | |
| CN113961500B (en) | IIC bus slave controller and working method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |