CN104484301A - FPGA-based (Field Programmable Gate Array-based) IO (Input/Output) bus device with automatic recognition function - Google Patents
FPGA-based (Field Programmable Gate Array-based) IO (Input/Output) bus device with automatic recognition function Download PDFInfo
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- CN104484301A CN104484301A CN201410821282.1A CN201410821282A CN104484301A CN 104484301 A CN104484301 A CN 104484301A CN 201410821282 A CN201410821282 A CN 201410821282A CN 104484301 A CN104484301 A CN 104484301A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0002—Serial port, e.g. RS232C
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0004—Parallel ports, e.g. centronics
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/38—Universal adapter
- G06F2213/3852—Converter between protocols
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Abstract
The invention relates to an FPGA-based (Field Programmable Gate Array-based) IO (Input/Output) bus device with an automatic recognition function, and belongs to the technical field of buses. The IO bus device comprises a CPU (Central Processing Unit), an FPGA, slot position plates, a parallel bus, a serial bus and a field bus, wherein the CPU and the FPGA are used for carrying out data interaction through an external bus, and the FPGA and the slot position plates are interacted through the parallel bus or the serial bus; the CPU and the slot position plates are directly interacted through the field bus; the FPGA is used for providing a plate address for the CPU and helping the CPU to send and receive data, a state machine is arranged in the FPGA, and the state machine can be used for selecting plate interfaces in a circulation mode to read plate information and data signals. The FPGA-based IO bus device has a self-recognition plate information function, so that the reliability of data interaction is enhanced. The communication among plates is more flexible, and upgrading of a device platform is facilitated. The FPGA serves as a bridge of the CPU and external data, and the interaction of plate data is carried out through the serial bus and the parallel bus.
Description
Technical field
The present invention relates to bussing technique field, particularly relate to extendible electric equipment protection device.
Background technology
In traditional electric equipment protection device, host CPU plate and open, output, connection between the plate such as analog quantity adopts private bus, data interaction is directly based upon between host CPU and various plate, and this kind of data transfer mode exists many inherent shortcomings.First, this transmission mode fixes the position of each block of plate, and namely each block of plate can only be inserted in the fixed position of backboard, and the line between backboard and host CPU plate is just fixed at the beginning of designing, and on backboard, each slot can not the plate of grafting other types.Secondly, plate wrong plug may cause device to damage, and especially misplugs wrong power panel or simulation template, host CPU plate may be caused to damage.3rd, because dedicated connection is various, and in protective device, there is no self-checking function and the recognition function of intelligence; in long-term work, the oxidation of plate connector place can be there is, cause plate to be connected with backboard unreliable; input signal can not be correctly validated, and outputs signal also possible errors action.4th, along with power equipment is to the increase in demand of protective device, CPU needs often to update, and traditional device often needs significantly to revise hardware and program.
Summary of the invention
In order to solve above-mentioned problems of the prior art, the invention provides a kind of IO bus unit based on FPGA with self-recognition function.Achieve various plate optional position to install, and host CPU has self-identifying plate function, thus enhance the reliability of electric equipment protection device.Meanwhile, by FPGA managing I/O bus, facilitate hardware platform upgrading, CPU updates.
The technical solution adopted in the present invention is as follows.
A kind of IO bus unit based on FPGA with self-recognition function, comprise CPU, FPGA, slot plate, parallel bus, universal serial bus and fieldbus, described CPU carries out data interaction by external bus and FPGA, and it is mutual that described FPGA passes through parallel bus or universal serial bus and slot plate; CPU is by fieldbus and slot plate direct interaction; Described FPGA provides plate address to CPU, and helps CPU to transmit and receive data.Be provided with state machine in described FPGA, state machine can circulate and choose plate interface, reads plate information and data-signal.
Described parallel bus adopts data line, chip select line, write signal line, reading signal lines, and data line is that each slot is public, and data are transmitted as two-way; The all brace route selections of each plate interface; In reading signal lines, part is for reading plate information.
Described data line is 8, and described route selection is 1, and described write signal line is 4, and described reading signal lines is 6, and wherein 2 reading signal lines are used as to read plate information, and 4 are used as read functions data.
Described plate information is made up of 28 bit data, comprises 5 plate types, 3 hardware versions, 5 BOM versions, 3 fixed code.
The transmission of described FPGA and receiving register adopt FIFO data cached.
Described fieldbus is CAN, and described universal serial bus is RS485 universal serial bus.
The IO bus unit based on FPGA with self-recognition function is by FPGA to parallel bus and universal serial bus unified management, FPGA is used as the main bridge of CPU and each plate data interaction.Parallel bus adopts 8 position datawires, 1 bit slice route selection, 4 write signal lines, 6 reading signal lines.Universal serial bus can be R
s485 universal serial bus.fPGA is connected with each plate with RS485 universal serial bus by parallel bus.FPGA provides plate interface IP address to CPU, and helps CPU to transmit and receive data.Adopt CAN to carry out communication for the higher data volume of rate requirement, CPU directly with each plate communication.
Parallel bus is controlled by FPGA, and on backboard, each slot is to there being respective CS chip select line.8 bit data are that all slots are public, and data line is two-way, and FPGA can send data to each plate, also can read the data of each plate.WR write signal line has 4, coordinates 8 position datawires, can send 32 bit data to the plate of each slot, and the relay outputed on plate as controlled, 32 relays supported at most by veneer.Same reading signal lines has 6, and wherein 2 are used as to read plate information, and remaining 4 are used as read functions data, and as read the intake opened into plate, single plate supports that at most 32 are opened into signal.In FPGA, each slot is chosen in the circulation of using state machine, and to reading plate information and the data-signal (as intake) of each slot, then writes data to corresponding plate (as pilot relay).Self-recognition function is by reading plate information realization, and plate information is made up of 28 bit data.Plate packets of information is containing 5 plate types, 3 hardware versions, 5 BOM versions, 3 fixed code (as 010).Fixed code, for judging whether plate inserts, is convenient to investigation and is caused the phenomenon of plate information errors because welding makes mistakes.
Universal serial bus is used for the deficiency of supplementing parallel bus, when host CPU plate needs with special plate communication, just adopts serial bus transmission data.As direct current sampling plate needs when sampled data being issued host CPU plate, direct current sampling plate is by RS485 and the communication of host CPU plate.RS485 serial communication bus is also simulate uart by FPGA to realize, and the data of RS485 serial bus transmission are supplied to cpu i/f by FPGA.The transmission of FPGA and receiving register can adopt FIFO data cached, reduce the consumption of CPU like this.RS485 universal serial bus is left in each slot on backboard, facilitates each slot and the communication of host CPU plate.CAN is also same design, only CPU and plate Direct Communication, controls without FPGA is unified.
Parallel bus and universal serial bus not only can work alone and transmit different data, and all right collaborative work, is all used for transmitting data of the same race.Use parallel bus transfers to CPU for critical data, also use serial bus transmission to CPU simultaneously, this enhance the reliability of transmission data.
Beneficial effect:
The present invention has made improvement relative to traditional electric equipment protection device internal data bus.
First, bus can self-identifying to the plate of each slot, and can read plate information like this, self-identifying plate type, the information such as hardware version, are convenient to routine processes, enhance the versatility of each plate.
Secondly, in FPGA, each slot of design point machine cycle control, enhances the dirigibility of plate position, and each slot is no longer fixing can only insert single plate, but each slot can any plate of grafting.
3rd, data transmission both can pass through parallel bus, also can pass through universal serial bus, can also pass through two class bus transfer simultaneously, enhance the reliability of data.And can to disappear dithering process to intake in FPGA, enhance the reliability opened into data.
Four, FPGA controls parallel bus and universal serial bus, and program does not need uart to drive in the host CPU, and facilitate host CPU to update, the code with FPGA communication part write by a needs, just can control to output, read open into the function such as power board event data.
5th, operation when digital independent of the present invention and write between host CPU and FPGA can retain 32, this method saves the expense of host CPU to a certain extent, reduce the utilization rate of host CPU, can also do to disappear for the intake read simultaneously and tremble process, doing in FPGA disappears trembles the expense that the another step of process saves host CPU.
6th, in FPGA, adopt above-mentioned RS485 series bus controller, enhance overall versatility, host CPU accesses above address just can realize RS485 serial communication, saves inquiry or the break period of host CPU.
7th, data can arrive host CPU from different bus runs respectively, for the signal that rate requirement is high, are directly connected with the CPU of mainboard by CAN, this ensure that the promptness of signal.For the signal that speed is lower, RS485 bus transfer data can be passed through.
8th, parallel bus and universal serial bus not only can work alone and transmit different data, and all right collaborative work, is all used for transmitting data of the same race.Use parallel bus transfers to host CPU for critical data, also use serial bus transmission to host CPU simultaneously, this enhance the reliability of transmission data.
Whether feature of the present invention is, can self-identifying have plate to insert for certain slot, and the information such as type, hardware version of plate is inserted in self-identifying.And can Dynamic Recognition, so just can realize the warm connection function of plate.The design of plate is simultaneously not limited to certain product, and different product can use veneer of the same race, especially a large amount of input and output plate used.
Accompanying drawing explanation
Fig. 1 is one-piece construction block diagram of the present invention.
Fig. 2 is the circuit diagram that the present invention reads plate information.
Embodiment
As shown in Figure 1, the present embodiment comprises host CPU plate, the slot of grafting plate, and three kinds of bus parallel buses, universal serial bus and fieldbus, host CPU plate comprises CPU module and FPGA module.Wherein these three kinds of buses are all connected with each slot.Each slot can use these three kinds of buses to send data.Except CAN is directly connected with slot by CPU, all the other are all be connected with slot by FPGA, unified management parallel bus and RS485 bus.
There is places different separately each slot, and each slot has CS chip select line to be connected with FPGA, and such FPGA just can time-sharing multiplex parallel bus.
Parallel bus is made up of CS chip select line, 2 RD_ID, 4 RD, 4 WR and 8 data lines, as shown in table 1.
The concrete terminal definition list of table 1 bus
| A | B | C | |
| 1 | CS | ||
| 2 | |||
| 3 | DATA1 | DGND | DATA0 |
| 4 | DATA3 | DGND | DATA2 |
| 5 | DATA5 | DGND | DATA4 |
| 6 | DATA7 | DGND | DATA6 |
| 7 | RD_1 | DGND | RD_0 |
| 8 | RD_3 | DGND | RD_2 |
| 9 | RD_ID1 | DGND | RD_ID0 |
| 10 | WR_1 | DGND | WR_0 |
| 11 | WR_3 | DGND | WR_2 |
| 12 | +3.3V | CAN_H | RS485+ |
| 13 | +3.3V | CAN_L | RS485- |
| 14 | +5V | +5V | +5V |
| 15 | +24V | +24V | +24V |
| 16 | 24GND | 24GND | 24GND |
The state machine of FPGA is read and write data by sheet choosing, reading writing signal line.Read the circuit of 5 plate types and 3 hardware versions as shown in Figure 2.When chip select line CS and RD_ID0 is low level simultaneously, BOARD_RD_ID0 signal is low level, impact damper will be transferred on 8 position datawires 5 of this a plate type codes 0x07 and 3 hardware version numbers 0x0, and FPGA just can read type and the version number of this plate.Same method can read No. BOM of plate and be used for the fixed code of determining whether plate is plugged.16 plate information definitions are as shown in table 2.
Table 2 16 plate information definition tables
When reading 32 bit data (as intake) from plate, adopt the method same with reading plate information, read 8 bit data respectively by 4 RD signal wires, in FPGA, be combined into 32 bit data amounts, facilitate 32 bit CPUs (as ARM) to access.When writing 32 bit data (as relay) to plate, chip select line CS coordinates with 4 WR lines, writes 8 bit data respectively.Operation now between CPU and FPGA can also retain 32.This method saves the expense of CPU to a certain extent, reduces the utilization rate of CPU, can also do to disappear simultaneously tremble process for the intake read, and doing in FPGA disappears trembles the expense that the another step of process saves CPU.
As shown in table 1, not only there is parallel bus in bus, and leave RS485 and CAN two kinds of serial line interfaces.For the signal that rate requirement is high, be directly connected with the CPU of mainboard by CAN, this ensure that the promptness of signal.For the signal that speed is lower, RS485 bus transfer data can be passed through.RS485 bus is FPGA on mainboard and veneer connecting line, in FPGA, open up 2 FIFO be used for cache bus data, while such guarantee data do not lose transmission, decrease the time that CPU waits for, and do not need uart to drive for program CPU, facilitate CPU to update, only need to write the code with FPGA communication part, just can control to output, read open into the function such as power board event data.
The RS485 bus interface address that FPGA controls is as following table.
The RS485 bus interface address table that table 3 FPGA controls
| 0x3800_C000 | RS485 control register; Energy when 0bit is, 1bit is internal loopback, and 2bit is for resetting |
| 0x3800_C002 | RS485 baud rate register; For calculating the baud rate of RS485 |
| 0x3800_C004 | TX_FIFO use amount register; |
| 0x3800_C008 | TX data register; |
| 0x3800_C00A | RX_FIFO use amount register; |
| 0x3800_C00E | RX data register; |
In FPGA, adopt above-mentioned RS485 series bus controller, enhance overall versatility, CPU accesses above address just can realize RS485 serial communication, saves inquiry or the break period of CPU.
Claims (6)
1. one kind has the IO bus unit of self-recognition function based on FPGA, it is characterized in that, comprise CPU, FPGA, slot plate, parallel bus, universal serial bus and fieldbus, described CPU carries out data interaction by external bus and FPGA, and it is mutual that described FPGA passes through parallel bus or universal serial bus and slot plate; CPU is by fieldbus and slot plate direct interaction; Described FPGA provides plate address to CPU, and helps CPU to transmit and receive data, and is provided with state machine in described FPGA, and state machine can circulate and choose plate interface, reads plate information and data-signal.
2. IO bus unit according to claim 1, is characterized in that, described parallel bus adopts data line, chip select line, write signal line, reading signal lines, and data line is that each slot is public, and data are transmitted as two-way; The all brace route selections of each plate interface; In reading signal lines, part is for reading plate information.
3. IO bus unit according to claim 2, is characterized in that, described data line is 8, described route selection is 1, and described write signal line is 4, and described reading signal lines is 6, wherein 2 reading signal lines are used as to read plate information, and 4 are used as read functions data.
4. IO bus unit according to claim 1, is characterized in that, described plate information is made up of 28 bit data, comprises 5 plate types, 3 hardware versions, 5 BOM versions, 3 fixed code.
5. IO bus unit according to claim 1, is characterized in that, the transmission of described FPGA and receiving register adopt FIFO data cached.
6. IO bus unit according to claim 1, is characterized in that, described fieldbus is CAN, and described universal serial bus is RS485 universal serial bus.
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104993921A (en) * | 2015-07-08 | 2015-10-21 | 上海斐讯数据通信技术有限公司 | Communication channel gating method of serial port master-slave communication control system |
| CN106210016A (en) * | 2016-07-05 | 2016-12-07 | 上海斐讯数据通信技术有限公司 | The network equipment and configuration upgrade method thereof |
| CN107193763A (en) * | 2017-04-13 | 2017-09-22 | 联想(北京)有限公司 | The method and electronic equipment of a kind of information processing |
| CN107632566A (en) * | 2017-09-19 | 2018-01-26 | 新华三技术有限公司 | A kind of board identification device, method and the network equipment |
| CN107907760A (en) * | 2017-10-30 | 2018-04-13 | 许继电气股份有限公司 | A kind of electric system distributed intelligent I/O Interface device and TT＆C system |
| CN108108316A (en) * | 2017-12-14 | 2018-06-01 | 上海斐讯数据通信技术有限公司 | A kind of Interface Expanding method and system based on field programmable gate array |
| CN109361607A (en) * | 2018-10-15 | 2019-02-19 | 迈普通信技术股份有限公司 | List item data capture method, device and communication equipment |
| CN109541475A (en) * | 2018-12-18 | 2019-03-29 | 武汉精能电子技术有限公司 | The method that automatic identification is carried out to multiple functions module simultaneously |
| CN109614351A (en) * | 2018-11-30 | 2019-04-12 | 中国人民解放军陆军工程大学 | Parallel bus serial interconnection extension method with error correction and automatic response mechanism |
| CN110120922A (en) * | 2019-05-14 | 2019-08-13 | 中国核动力研究设计院 | A kind of data interaction Network Management System and method based on FPGA |
| CN112540944A (en) * | 2020-12-15 | 2021-03-23 | 安徽皖通邮电股份有限公司 | Parallel bus protocol and method for realizing data interaction between boards based on protocol |
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| CN104993921B (en) * | 2015-07-08 | 2018-04-10 | 上海斐讯数据通信技术有限公司 | A kind of communication port gating method of serial ports master-slave communication control system |
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| CN107632566A (en) * | 2017-09-19 | 2018-01-26 | 新华三技术有限公司 | A kind of board identification device, method and the network equipment |
| CN107907760A (en) * | 2017-10-30 | 2018-04-13 | 许继电气股份有限公司 | A kind of electric system distributed intelligent I/O Interface device and TT＆C system |
| CN108108316A (en) * | 2017-12-14 | 2018-06-01 | 上海斐讯数据通信技术有限公司 | A kind of Interface Expanding method and system based on field programmable gate array |
| CN108108316B (en) * | 2017-12-14 | 2023-08-11 | 珠海西格电力科技有限公司 | Interface expansion method and system based on field programmable gate array |
| CN109361607B (en) * | 2018-10-15 | 2021-09-17 | 迈普通信技术股份有限公司 | Method and device for acquiring table item data and communication equipment |
| CN109361607A (en) * | 2018-10-15 | 2019-02-19 | 迈普通信技术股份有限公司 | List item data capture method, device and communication equipment |
| CN109614351A (en) * | 2018-11-30 | 2019-04-12 | 中国人民解放军陆军工程大学 | Parallel bus serial interconnection extension method with error correction and automatic response mechanism |
| CN109614351B (en) * | 2018-11-30 | 2022-05-24 | 中国人民解放军陆军工程大学 | Parallel bus serial interconnection extension method with error correction and automatic response mechanism |
| CN109541475A (en) * | 2018-12-18 | 2019-03-29 | 武汉精能电子技术有限公司 | The method that automatic identification is carried out to multiple functions module simultaneously |
| CN110120922A (en) * | 2019-05-14 | 2019-08-13 | 中国核动力研究设计院 | A kind of data interaction Network Management System and method based on FPGA |
| CN110120922B (en) * | 2019-05-14 | 2022-09-20 | 中核控制系统工程有限公司 | FPGA-based data interaction network management system and method |
| CN112540944A (en) * | 2020-12-15 | 2021-03-23 | 安徽皖通邮电股份有限公司 | Parallel bus protocol and method for realizing data interaction between boards based on protocol |
| CN112540944B (en) * | 2020-12-15 | 2022-11-25 | 安徽皖通邮电股份有限公司 | Parallel bus protocol and method for realizing data interaction between boards based on protocol |
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