CN112530371A

CN112530371A - Pixel driving circuit

Info

Publication number: CN112530371A
Application number: CN202011430603.7A
Authority: CN
Inventors: 张竞文; 王贤军; 王雅榕; 苏松宇
Original assignee: AU Optronics Corp
Current assignee: AUO Corp
Priority date: 2020-06-16
Filing date: 2020-12-07
Publication date: 2021-03-19
Anticipated expiration: 2040-12-07
Also published as: TWI723903B; CN112530371B; TW202201375A

Abstract

The pixel driving circuit comprises a light emitting diode, a capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a sixth transistor. The first transistor is used for providing a light emitting diode driving current. The light emitting diode, the second transistor, the first transistor and the third transistor are connected in series and electrically connected between the first system voltage end and the second system voltage end. The capacitor is electrically connected to the grid end of the first transistor. The fourth transistor and the fifth transistor are connected in series and electrically connected to the first end of the first transistor. The sixth transistor is electrically connected to the second end of the first transistor. The capacitor is used for providing a modulatable voltage to the grid end of the first transistor so as to adjust the current provided to the light-emitting diode.

Description

Pixel driving circuit

Technical Field

The present disclosure relates to a pixel driving circuit, and more particularly, to a pixel driving circuit of a light emitting diode.

Background

In the present display panel, an Organic Light-Emitting Diode (OLED) has a large Light-Emitting surface, and has a transparent and flexible characteristic. The OLED can be divided into active driving and passive driving according to different driving methods.

In the operation of the active OLED display panel, the driving current is influenced by a threshold voltage (threshold voltage) of the driving transistor. Since there is a certain error in the threshold voltage of the driving transistors of the different display units in the active OLED display panel, the driving currents are different. The driving currents generate differences, so that the luminance of the OLED is inconsistent, and the brightness of the image is uneven when the active OLED display panel displays images.

Disclosure of Invention

The present disclosure provides a memory device including a pixel driving circuit. The pixel driving circuit includes: the light-emitting diode comprises a light-emitting diode, a first transistor, a capacitor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a sixth transistor. The first transistor is used for providing a driving current for the light-emitting diode; the second transistor is coupled on a current path of the driving current; the third transistor is coupled between the first transistor and a first system voltage end, and the third transistor is coupled on the current path of the driving current; the fourth transistor is coupled between the first end of the first transistor and the grid end of the first transistor and is used for compensating a critical voltage of the first transistor; the fifth transistor is coupled to the grid terminal of the first transistor and is used for resetting the voltage of the grid terminal of the first transistor; a first terminal of the sixth transistor receives a data signal, a second terminal of the sixth transistor is coupled to the second terminal of the first transistor, and the sixth transistor is used for inputting the data signal to the second terminal of the first transistor; the first end of the capacitor is electrically coupled with the grid end of the first transistor, and when the pixel driving circuit enters a light-emitting period, the voltage level of the first end of the capacitor is changed from a first level to a second level so as to adjust the magnitude of the driving current.

In summary, the pixel driving circuit of the present disclosure compensates the threshold voltage of the first transistor, so that the driving current flowing through the light emitting diode is not affected by the threshold voltage. And setting a capacitor and adjusting the voltage amplitude provided to the grid of the first transistor through the capacitor to adjust the driving current flowing through the light-emitting diode, so that the brightness of the light-emitting diode can be further adjusted and controlled.

Drawings

The foregoing and other objects, features, and advantages of the disclosure will be apparent from the following more particular description of the embodiments, as illustrated in the accompanying drawings in which:

fig. 1 is a circuit architecture diagram of a pixel driving circuit according to an embodiment of the disclosure.

FIG. 2A is a timing diagram of control signals and data signals of the pixel driving circuit of FIG. 1 according to an embodiment.

FIG. 2B is a timing diagram of control signals and data signals of the pixel driving circuit of FIG. 1 according to another embodiment.

Fig. 3A is a circuit state diagram of the pixel driving circuit in fig. 1 during a reset period.

Fig. 3B is a circuit state diagram of the pixel driving circuit in fig. 1 during the compensation and data input periods.

Fig. 3C is a circuit state diagram of the pixel driving circuit in fig. 1 during a light emitting period.

Fig. 4 is a circuit architecture diagram of a pixel driving circuit according to an embodiment of the disclosure.

Fig. 5 is a circuit architecture diagram of a pixel driving circuit according to an embodiment of the disclosure.

Fig. 6 is a circuit architecture diagram of a pixel driving circuit according to an embodiment of the disclosure.

Fig. 7 is a timing diagram of control signals and data signals of the pixel driving circuit in fig. 5 and 6.

Description of reference numerals:

in order to make the above and other objects, features, advantages and embodiments of the present disclosure more comprehensible, the following symbols are provided:

100,200,300,400: pixel driving circuit

L1: light emitting diode

C1: capacitor with a capacitor element

T1: a first transistor

T2: second transistor

T3: a third transistor

T4: a fourth transistor

T5: fifth transistor

T6: sixth transistor

Vdata: data signal

VSS: first system voltage terminal

VDD: second system voltage terminal

SN-1: a first control signal

EM: third control signal

SN: the second control signal

CS: a fourth control signal

N1, N2, N3: node point

P1: during reset

P2: during compensation and data input

P3: during the light emitting period

Id: drive current

Detailed Description

The following embodiments are described in detail with reference to the accompanying drawings, but the embodiments are not provided to limit the scope of the present disclosure, and the description of the structure operation is not intended to limit the execution sequence thereof, and any structure resulting from the rearrangement of elements to produce the device with the technical effects is included in the scope of the present disclosure. In addition, the drawings are for illustrative purposes only and are not drawn to scale. For ease of understanding, the same or similar elements will be described with the same reference numerals in the following description.

The term (terms) used throughout the specification and claims has the ordinary meaning as commonly understood in each term used in the art, in the disclosure herein, and in the specific context, unless otherwise indicated.

As used herein, the terms "first," "second," "third," etc. do not denote any order or order, nor are they used to limit the disclosure, but rather are used to distinguish one element from another element or operation described in such technical terms.

Please refer to fig. 1. Fig. 1 is a circuit architecture diagram of a pixel driving circuit 100 according to an embodiment of the disclosure. As shown in fig. 1, the pixel driving circuit 100 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a capacitor C1, and a light emitting diode L1.

In some embodiments, the first transistor T1, the second transistor T2, the third transistor T3, and the light emitting diode L1 are connected in series. The first transistor T1 is used for providing a driving current Id to the led L1. The second transistor T2 is coupled in the current path of the driving current Id. The third transistor T3 is coupled between the first transistor T1 and the first system voltage terminal VSS, and the third transistor T3 is coupled to the current path of the driving current Id. The second terminal of the capacitor C1 is electrically connected to the gate terminal of the first transistor T1. When the light-emitting period is entered, the pixel driving circuit 100 changes the voltage level of the first terminal of the capacitor C1 from the first level to the second level to adjust the magnitude of the driving current.

The fourth transistor T4 and the fifth transistor T5 are connected in series and electrically connected to the first terminal of the first transistor T1. The fourth transistor T4 is coupled between the first terminal of the first transistor T1 and the gate terminal of the first transistor T1, and the fourth transistor T4 is used for compensating the threshold voltage Vth of the first transistor T1. The fifth transistor T5 is coupled to the gate terminal of the first transistor T1, and the fifth transistor T5 is used for resetting the voltage at the gate terminal of the first transistor T1. The sixth transistor T6 is electrically connected to the second terminal of the first transistor T1, the first terminal of the sixth transistor T6 receives the data signal Vdata, the second terminal of the sixth transistor T6 is coupled to the second terminal of the first transistor T1, and the sixth transistor T6 is used for inputting the data signal Vdata to the second terminal of the first transistor T1.

The node N1 is a connection point between the capacitor C1 and the gate terminal of the first transistor T1, the node N2 is a connection point between the fourth transistor T4 and the first transistor T1, and the node N3 is a connection point between the sixth transistor T6 and the first transistor T1.

The transistors respectively have a first terminal, a second terminal and a Gate terminal (Gate). When the first terminal of one of the transistors is a drain terminal (source terminal), the second terminal of the transistor is a source terminal (drain terminal). In addition, the capacitors also have a first terminal and a second terminal, respectively.

In the embodiment shown in fig. 1, the first terminal of the capacitor C1 is configured to receive the fourth control signal CS, and the second terminal of the capacitor C1 is electrically connected to the gate terminal of the first transistor T1 (e.g., the node N1 in fig. 1). in some embodiments, the fourth control signal CS is a control signal for compensating/enhancing the brightness, and the voltage level of the node N1 can be adjusted by controlling the coupling of the level of the fourth control signal CS through the capacitor C1. In some embodiments of the present disclosure, the fourth control signal CS is switched between a high level VA1 and a low level VB1, and the difference between the high level VA1 and the low level VB1 is utilized to correspondingly increase the gate voltage of the first transistor T1, thereby increasing the light emitting current flowing through the first transistor T1, it should be noted that the voltage levels of the high level VA1 and the low level VB1 can be dynamically changed according to the ambient brightness or the required brightness enhancement ratio, which will be further described in detail in the following embodiments.

Please continue to refer to fig. 1. The first terminal of the first transistor T1 is electrically connected to the second terminal of the second transistor T2, and the second terminal of the first transistor T1 is electrically connected to the first terminal of the third transistor T3. The first terminal of the second transistor T2 is electrically connected to the first terminal of the led L1, and the second terminal of the led L1 is electrically connected to the second system voltage terminal VDD. A second terminal of the third transistor T3 is electrically connected to the first system voltage terminal VSS. The gate terminals of the second transistor T2 and the third transistor T3 are configured to receive the third control signal EM. In some embodiments, the third control signal EM is an emission control signal of the pixel driving circuit 100, and the pixel driving circuit 100 can be driven to emit light when the third control signal EM is at a high level.

Moreover, a first terminal of the fourth transistor T4 is electrically connected to the second terminal of the capacitor C1 and the gate terminal of the first transistor T1, and a second terminal of the fourth transistor T4 is electrically connected to the first terminal of the first transistor T1 (e.g., the node N2 in fig. 1). The gate terminal of the fourth transistor T4 is for receiving the second control signal SN. The first terminal and the gate terminal of the fifth transistor T5 are configured to receive the first control signal SN-1, and the second terminal of the fifth transistor T5 is electrically connected to the second terminal of the capacitor C1, the first terminal of the fourth transistor T4, and the gate terminal of the first transistor T1 (e.g., the node N1 in fig. 1). The first terminal of the sixth transistor T6 is for receiving the data signal Vdata, and the second terminal of the sixth transistor T6 is electrically connected to the second terminal of the first transistor T1 and the first terminal of the third transistor T3 (e.g., the node N3 in fig. 1). The gate terminal of the sixth transistor T6 is for receiving the second control signal SN.

For convenience of illustration, the pixel driving circuit 100 shown in fig. 1 is a single-stage driving circuit for driving one column (or one row) of display pixels on the display panel, and in practical applications, the pixel driving circuit 100 may include a plurality of stages of driving circuits for sequentially driving the display pixels of the columns (or the rows), that is, the pixel driving circuit 100 may have a plurality of single-stage driving circuit structures as shown in fig. 1. In some embodiments, the second control signal SN is a scan signal of a current stage of the pixel driving circuit 100, and the first control signal SN-1 is a scan signal of a previous stage.

In the embodiment shown in fig. 1, the transistors T1-T6 are N-type metal oxide semiconductor field effect transistor (NMOS) switches for illustration purposes, but the disclosure is not limited thereto. In another embodiment, those skilled in the art can replace the transistors T1-T6 with P-type metal-oxide-semiconductor field-effect transistor (P-type MOSFET, PMOS) switches, C-type metal-oxide-semiconductor field-effect transistor (C-type MOSFET, CMOS) switches, or other similar switching devices, and adjust the logic levels of the system voltages (e.g., the second system voltage terminal VDD and the first system voltage terminal VSS), the control signals (e.g., the control signals SN-1, SN, CS, EM), and the data signal Vdata correspondingly, so as to achieve the same function as the present embodiment.

Fig. 2A is a timing diagram of control signals and data signals of the pixel driving circuit 100 in fig. 1 according to an embodiment. Fig. 2B is a timing diagram of control signals and data signals of the pixel driving circuit 100 in fig. 1 according to another embodiment.

As shown in fig. 2A, in this embodiment, one display period in the control timing of the pixel driving circuit 100 can be divided into three periods, which are the reset period P1, the compensation and data input period P2 and the light emitting period P3. It should be noted that the time lengths of the periods in fig. 2A are only for illustration and are not used to limit the disclosure.

To make the overall operation of the pixel driving circuit 100 more clear and easy to understand, please refer to fig. 1 and fig. 2A together.

Fig. 3A is a circuit state diagram of the pixel driving circuit 100 in fig. 1 during the reset period P1. As shown in FIG. 2A, the first control signal SN-1 is high during the reset period P1. The third control signal EM, the second control signal SN, and the data signal Vdata are low level. The fourth control signal CS is at a low level VB 1. Correspondingly, as shown in fig. 3A, the second transistor T2, the third transistor T3, the fourth transistor T4, and the sixth transistor T6 are in an off state, and the first transistor T1 and the fifth transistor T5 are in an on state.

In the reset period P1, a current in the pixel driving circuit 100 flows from the first control signal SN-1 to the gate terminal of the first transistor T1 via the fifth transistor T5 and the node N1 in sequence. Since the gate terminal of the first transistor T1 is electrically connected to the second terminal of the capacitor C1, the current path also enables the second terminal of the capacitor C1 to receive the first control signal SN-1 to set the node N1 to a high level, and the first terminal of the capacitor C1 is at a low level based on the fourth control signal CS, so that the potential difference VD is stored between the two terminals (the first terminal and the second terminal) of the capacitor C1. The first transistor T1 is turned on by the first control signal SN-1, so that the node N2 is pulled to be equal to the node N3.

That is, at the end of the reset period P1. The voltage of the gate terminal (node N1) of the first transistor T1 is at a high level.

Fig. 3B is a circuit state diagram of the pixel driving circuit 100 in fig. 1 during the compensation and data input period P2. As shown in fig. 2A, in the compensation and data input period P2, the second control signal SN and the data signal Vdata are at a high level, and the first control signal SN-1 and the third control signal EM are at a low level. The fourth control signal CS is at a low level VB 1. Correspondingly, as shown in fig. 3B, the second transistor T2, the third transistor T3, and the fifth transistor T5 are in an off state, and the first transistor T1, the fourth transistor T4, and the sixth transistor T6 are in an on state.

In the compensation and data input period P2, the potential difference VD stored in the capacitor C1 by the reset period P1 temporarily maintains the node N1 at a high level, thereby maintaining the first transistor T1 in a turned-on state. In the compensation and data input period P2, the potential of the node N1 flows to the data signal Vdata through the fourth transistor T4, the node N2, the first transistor T1, the node N3, and the sixth transistor T6, that is, the level of the node N1 is slowly discharged through the above path. The current path continues until the potential difference VD stored in the capacitor C1 gradually decreases until the potential at the node N1 decreases to a level where the first transistor T1 cannot be turned on. When the voltage difference between the gate and the source of the transistor is a threshold voltage, the transistor is in an off state. That is, when the potential of the gate terminal of the first transistor T1 drops to a threshold voltage Vth higher than the data signal Vdata, the first transistor T1 is turned off. In this embodiment, the threshold voltage Vth is a threshold voltage Vth of the first transistor T1.

At this time, the potential of the node N1 (the gate terminal of the first transistor T1) and the potential of the node N2 are both equal to the data signal Vdata plus a threshold voltage Vth, and the first transistor T1 is turned off (turned into the off state).

That is, at the end of the compensation and data input period P2. The gate terminal (node N1) of the first transistor T1 has a voltage of (Vdata + Vth). The source terminal (node N3) of the first transistor T1 has a voltage Vdata.

Fig. 3C is a circuit state diagram of the pixel driving circuit 100 in fig. 1 in the light-emitting period P3. As shown in fig. 2A, the third control signal EM is at a high level during the light emission period P3. The fourth control signal CS is at a high level VA 1. The first control signal SN-1, the second control signal SN, and the data signal Vdata are low. Correspondingly, as shown in fig. 3C, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 belong to an off state, and the first transistor T1, the second transistor T2, and the third transistor T3 belong to an on state.

In the light-emitting period P3, the voltage at the node N1 is (Vdata + Vth) in the light-emitting period P3. The third control signal EM turns on the second transistor T2 and the third transistor T3. The voltage at the second terminal of the first transistor T1 drops to be consistent with the first system voltage terminal VSS, causing the voltage difference between the gate and the source of the first transistor T1 to be greater than the threshold voltage Vth, and the gate terminal of the first transistor T1 is pulled high by the fourth control signal Cs via the capacitor C1, so that the first transistor T1 is turned on. Therefore, the light emitting current flows from the second system voltage terminal VDD to the first system voltage terminal VSS through the light emitting diode L1, the second transistor T2, the first transistor T1 and the third transistor T3 in sequence.

In detail, in the reset period P1 and the compensation and data input period P2 before the light emitting period P3, the fourth control signal CS is at the low level VB 1. In the light-emitting period P3, the fourth control signal CS is at the high level VA 1. Therefore, when the light emitting period P3 is entered, the difference between the low level VB1 and the high level VA1 of the fourth control signal CS can be transmitted to the gate terminal of the first transistor T1 (node N1) through the capacitor C1.

At this time, the voltage at the gate terminal (node N1) of the first transistor T1 is the data signal Vdata plus a threshold voltage Vth, plus the difference between the high level VA1 and the low level VB1 of the fourth control signal CS.

That is, in the light emission period P3. The gate terminal (node N1) of the first transistor T1 has a voltage of (Vdata + Vth + VA1-VB 1). The voltage of the source terminal (node N3) of the first transistor T1 is equal to zero.

In the light emitting period P3, since the current flowing through the light emitting diode L1 is equal to the current flowing through the first transistor T1, the driving current flowing through the first transistor T1 is represented by Id. In general, the driving current Id provided by an N-type transistor follows the following equation: drive current Id ═ k (Vg-Vs-Vth)². In the embodiment of the present disclosure, k is a constant related to the device characteristics of the first transistor T1.

By substituting the gate terminal voltage (Vg) and the source terminal voltage (Vs) of the first transistor T1 into the formula of the driving current Id, it can be calculated:

Id＝k(Vg-Vs-Vth)²

Id＝k[(Vdata+Vth+VA1-VB1)-0-Vth]²

Id＝k[Vdata+VA1-VB1]²

from the above formula of the driving current Id, the driving current Id will be related to the difference between the high level VA1 and the low level VB1 of the data signal Vdata and the fourth control signal CS, but is not affected by the threshold voltage Vth.

In some embodiments of the present disclosure, the high level VA1 and the low level VB1 of the fourth control signal CS are amplitude modulatable. The voltage amplitudes of the high level VA1 and the low level VB1 of the fourth control signal CS are adjusted according to the environmental conditions, so that the voltage amplitude difference between the high level VA1 and the low level VB1 is increased or decreased. In this way, the voltage amplitude difference between the high level VA1 and the low level VB1 of the fourth control signal CS is modulated. Therefore, the brightness of the led L1 can be controlled according to the formula of the driving current Id. The voltage amplitude difference that can be modulated can modulate the brightness of the led L1 more greatly than the data signal Vdata that is a dc signal.

Please refer to fig. 2A and fig. 2B together. As shown in fig. 2A, in the outdoor where the ambient light source is bright, by increasing the voltage magnitude difference between the high level VA1 and the low level VB1 of the fourth control signal CS, the voltage supplied to the gate terminal of the first transistor T1 is increased, the current flowing through the first transistor T1 is increased, and the luminance of the light emitting diode L1 is increased. As shown in fig. 2B, in a room with a dark ambient light source, by reducing the voltage magnitude difference between the high level VA2 and the low level VB2 of the fourth control signal CS, the voltage supplied to the gate terminal of the first transistor T1 is reduced, the current flowing through the first transistor T1 is reduced, and the luminance of the light emitting diode L1 is reduced. Thereby controlling the brightness of the led L1 according to the environmental condition.

For example, when the ambient light source is determined to be bright, the pixel driving circuit 100 as shown in fig. 2A can set the modulatable voltage amplitude difference between the low level VB1 and the high level VA1 of the fourth control signal CS to be 0V to 8V; when the ambient light source is determined to be dark, as shown in fig. 2B, the pixel driving circuit 100 may set the modulatable voltage amplitude difference between the high level VA1 and the low level VB2 of the fourth control signal CS to 0V to 4V. In this way, when the ambient light source is bright, the gate of the first transistor T1 can be raised to a high level.

Fig. 4 is a circuit architecture diagram of a pixel driving circuit 200 according to an embodiment of the disclosure. In the embodiment shown in fig. 4, the pixel driving circuit 200 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a capacitor C1, and a light emitting diode L1. Compared to the pixel driving circuit 100 in the embodiment of fig. 1, the difference between the pixel driving circuit 200 in the embodiment of fig. 4 is that the first terminal of the light emitting diode L1 receives the third control signal EM, that is, the second terminal of the light emitting diode L1 in this embodiment is not connected to the second system voltage terminal VDD, but is instead connected to the third control signal EM.

Please refer to fig. 4 and fig. 2A together. In the reset period P1 and the compensation and data input period P2, since the second transistor T2 and the fourth transistor T4 are turned off, no current flows through the light emitting diode L1. When the driving current Id is generated through the light emitting diode L1 during the light emitting period P3, the third control signal EM is already switched to the high level, similar to the second system voltage terminal VDD in function, and the second terminal of the light emitting diode L1 can be driven by the high level third control signal EM during the light emitting period P3. Regarding the connection and operation of the pixel driving circuit 200, the connection and operation are substantially the same as those of the pixel driving circuit 100 in the embodiment of fig. 1, and are not repeated herein.

Fig. 5 is a circuit architecture diagram of a pixel driving circuit 300 according to an embodiment of the disclosure. Fig. 6 is a circuit architecture diagram of a pixel driving circuit 400 according to an embodiment of the disclosure. Fig. 7 is a timing diagram of control signals and data signals of the pixel driving circuit in fig. 5 and 6.

In the embodiment shown in fig. 5, the pixel driving circuit 300 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a capacitor C1, and a light emitting diode L1. Compared to the pixel driving circuit 100 in the embodiment of fig. 1, the difference between the pixel driving circuit 300 in the embodiment of fig. 5 is that the first terminal of the capacitor C1 is configured to receive the third control signal EM. That is, in this embodiment, the capacitor C1 receives the third control signal EM instead of the fourth control signal CS. More specifically, the gate terminal of the second transistor T2, the gate terminal of the third transistor T3 and the capacitor C1 all receive the third control signal EM.

Please refer to fig. 5 and fig. 7. In the reset period P1 and the compensation and data input period P2, since the second transistor T2 and the fourth transistor T4 are turned off, no current flows through the light emitting diode L1. In the light emitting period P3, the third control signal EM is switched to a high level, and in this embodiment, the third control signal EM is similar to the fourth control signal CS in function, and the voltage of the gate terminal of the first transistor T1 can be pulled high by the high level of the third control signal EM through the capacitor C1. Other details of the connection and operation of the pixel driving circuit 300 are substantially the same as those of the pixel driving circuit 100 in the embodiment of fig. 1, and are not repeated herein.

In the embodiment shown in fig. 6, the pixel driving circuit 400 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a capacitor C1, and a light emitting diode L1. Compared to the pixel driving circuit 100 in the embodiment of fig. 1, the pixel driving circuit 400 in the embodiment of fig. 5 is different in that the first terminal of the capacitor C1 is configured to receive the third control signal EM, and the second terminal of the light emitting diode L1 is configured to receive the third control signal EM, that is, the first terminal of the capacitor C1 in this embodiment does not receive the fourth control signal CS, but instead receives the third control signal EM. Also, the second terminal of the light emitting diode L1 is not connected to the second system voltage terminal VDD, but is instead connected to the third control signal EM. More specifically, the gate terminal of the second transistor T2, the gate terminal of the third transistor T3, the second terminal of the led L1 and the capacitor C1 all receive the third control signal EM.

In this embodiment, please refer to fig. 6 and fig. 7 together. In the reset period P1 and the compensation and data input period P2, since the second transistor T2 and the fourth transistor T4 are turned off, no current flows through the light emitting diode L1. In the light-emitting period P3, when the driving current Id is generated through the light-emitting diode L1, the third control signal EM is already switched to the high level, so that the high level of the third control signal EM in the light-emitting period P3 can be used to pull up the voltage at the gate terminal of the first transistor T1 and drive the second terminal of the light-emitting diode L1. Other details of the connection and operation of the pixel driving circuit 400 are substantially the same as those of the pixel driving circuit 100 in the embodiment of fig. 1, and are not repeated herein.

Since the capacitor C1 in fig. 5 and 6 receives the third control signal EM instead of the fourth control signal CS. Therefore, the timing diagram in fig. 7 is different from the timing diagram in fig. 2A in that the fourth control signal CS is not present. Regarding the other signal timings of the timing diagram in the embodiment of fig. 7, the other signal timings are substantially the same as the timing diagram in the embodiment of fig. 2A, and are not repeated herein.

In summary, the pixel driving circuit of the present disclosure compensates for the threshold voltage Vth of the first transistor T1, so that the current flowing through the light emitting diode L1 is not affected by the variation of the threshold voltage Vth. The capacitor C1 is disposed, and the voltage amplitude provided to the gate of the first transistor T1 is adjusted by the capacitor C1 to adjust the driving current Id flowing through the led L1, so that the brightness of the led L1 can be further controlled.

Although the present disclosure has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the disclosure, and therefore, the scope of the disclosure should be limited only by the appended claims.

Claims

1. A pixel driving circuit, comprising:

a light emitting diode;

a first transistor for providing a driving current to the light emitting diode;

a second transistor coupled to a current path of the driving current;

a third transistor, coupled between the first transistor and a first system voltage terminal, coupled to the current path of the driving current;

a fourth transistor, coupled between the first terminal of the first transistor and the gate terminal of the first transistor, for compensating a threshold voltage of the first transistor;

a fifth transistor, coupled to the gate terminal of the first transistor, for resetting the voltage at the gate terminal of the first transistor;

a sixth transistor, having a first end receiving a data signal and a second end coupled to the second end of the first transistor, for inputting the data signal to the second end of the first transistor; and

and a capacitor, wherein a first end of the capacitor is electrically coupled to the gate end of the first transistor, and when the pixel driving circuit enters a light-emitting period, the voltage level of the first end of the capacitor is changed from a first level to a second level so as to adjust the magnitude of the driving current.

2. A pixel drive circuit as claimed in claim 1, wherein:

the first end of the fifth transistor is used for receiving a first control signal, the second end of the fifth transistor is coupled with the grid end of the first transistor, and the grid end of the fifth transistor is used for receiving the first control signal; and

during a reset period of the pixel driving circuit, the first control signal is at a high level, which causes the fifth transistor to be turned on, so that the first control signal is input to the gate terminal of the first transistor.

3. A pixel drive circuit as claimed in claim 1, wherein:

the first end of the fourth transistor is coupled to the gate end of the first transistor, the second end of the fourth transistor is coupled to the first end of the first transistor, and the gate end of the fourth transistor is used for receiving a second control signal;

the first end of the sixth transistor is used for receiving the data signal, the second end of the sixth transistor is coupled to the second end of the first transistor, and the gate end of the sixth transistor is used for receiving the second control signal; and

in a compensation and data input period of the pixel driving circuit, the second control signal and the data signal are in high level, so that the sixth transistor and the fourth transistor are turned on, and the voltage at the grid end of the first transistor is continuously discharged to the first transistor through the fourth transistor and is turned off.

4. A pixel drive circuit as claimed in claim 1, wherein:

the first end of the light emitting diode is coupled with the first end of the second transistor;

the second end of the second transistor is coupled to the first end of the first transistor, and the gate terminal of the second transistor is used for receiving a third control signal; and

the first terminal of the third transistor is coupled to the second terminal of the first transistor, the second terminal of the third transistor is coupled to the first system voltage terminal, and the gate terminal of the third transistor is configured to receive the third control signal.

The first end of the capacitor is used for receiving a fourth control signal, and the second end of the capacitor is coupled with the grid end of the first transistor;

when the light-emitting period of the pixel driving circuit is entered, the fourth control signal is changed from the first level to the second level, so that the level of the grid terminal of the first transistor is correspondingly changed to adjust the magnitude of the driving current; and

during the light emitting period of the pixel driving circuit, the third control signal is at a high level, which causes the second transistor and the third transistor to be turned on, so that the driving current flows through the light emitting diode.

5. The pixel driving circuit according to claim 4, wherein the second terminal of the light emitting diode is coupled to a second system voltage terminal.

6. The pixel driving circuit according to claim 4, wherein the second terminal of the light emitting diode is configured to receive the third control signal.

7. The pixel driving circuit as claimed in claim 4, wherein the fourth control signal has a modulated voltage amplitude difference, and the fourth control signal adjusts the driving current provided to the light emitting diode according to the modulated voltage amplitude difference.

8. The pixel driving circuit of claim 7, wherein the magnitude of the modulatable voltage magnitude difference is positively correlated to an ambient light source intensity.

9. A pixel drive circuit as claimed in claim 1, wherein:

the second end of the second transistor is coupled to the first end of the first transistor, and the gate terminal of the second transistor is used for receiving a third control signal;

a first end of the third transistor is coupled to the second end of the first transistor, a second end of the third transistor is coupled to the first system voltage end, and a gate end of the third transistor is used for receiving the third control signal;

the first end of the capacitor is used for receiving the third control signal, and the second end of the capacitor is coupled with the grid end of the first transistor;

when the pixel driving circuit enters the light-emitting period, the third control signal changes from the first level to the second level, so that the level of the gate terminal of the first transistor changes correspondingly to adjust the magnitude of the driving current; and

10. The pixel driving circuit according to claim 9, wherein the second terminal of the light emitting diode is coupled to a second system voltage terminal or is configured to receive the third control signal.