CN110444165B

CN110444165B - Pixel compensation circuit and display device

Info

Publication number: CN110444165B
Application number: CN201810420654.8A
Authority: CN
Inventors: 周兴雨
Original assignee: EverDisplay Optronics Shanghai Co Ltd
Current assignee: EverDisplay Optronics Shanghai Co Ltd
Priority date: 2018-05-04
Filing date: 2018-05-04
Publication date: 2021-03-12
Anticipated expiration: 2038-05-04
Also published as: CN110444165A

Abstract

The invention provides a pixel compensation circuit and a display device, wherein the pixel compensation circuit at least comprises a first transistor, a second transistor, a third transistor, a fifth transistor, a sixth transistor, a seventh transistor, a ninth transistor, a tenth transistor, a light emitting diode and a capacitor. The pixel compensation circuit compensates the voltage drop of the voltage source due to the resistance value of the wiring, so that the driving current of the OLED display device is not influenced by the voltage drop of the voltage source on the display panel, the deviation between the driving current value at different positions of the display panel and the currently set driving current value is reduced as much as possible, the brightness uniformity of the display panel is improved, and the watching experience of a user is improved.

Description

Pixel compensation circuit and display device

Technical Field

The invention relates to the field of display control circuits, in particular to a pixel compensation circuit for compensating voltage drop of voltage of a voltage source generated in a display panel due to resistance of a wire and a display device.

Background

Recently, various flat panel displays having a smaller weight and volume than a cathode ray tube display have been developed including liquid crystal displays, field emission displays, plasma display panels, and organic light emitting displays.

Among the flat panel displays, the organic light emitting display displays an image using an Organic Light Emitting Diode (OLED) that generates light by recombination of electrons and holes. The organic light emitting display has a fast response speed and is driven with low power consumption. A typical organic light emitting display supplies a current according to a data signal to an OLED through a transistor formed in a pixel, so that the OLED emits light.

The organic light emitting display is classified into a passive driving type (PMOLED) which does not use a thin film transistor substrate and an active driving type (AMOLED) which uses a thin film transistor substrate, according to driving types.

Each pixel of the active-driving organic light-emitting display is provided with a low-temperature polycrystalline silicon thin film transistor with a switching function, each pixel is provided with a charge storage capacitor, and a peripheral driving circuit and a display component are integrated on the same glass substrate. Each pixel generates a driving current according to a data signal, and the brightness of the organic light emitting diode is controlled by adjusting the driving current of the organic light emitting diode.

In the driving circuit of the conventional AMOLED display module, since the AMOLED is driven by a current, a voltage supplied to the voltage source may generate a voltage drop in the display panel due to a resistance of the trace, thereby causing the display panel of the AMOLED to have different voltages at the top, the bottom, and the top. Since the luminance of the organic light emitting diode is proportional to the amount of the driving current, the voltage of the display panel of the AMOLED is not uniform, which may cause the luminance of the display panel to be non-uniform. With the aging of the wiring in the display panel along with the time, the resistance of the wiring part can be further increased, and the condition of uneven voltage in the display panel can be more obvious, so that the uneven brightness of the display panel is further deepened, the service life of the AMOLED display panel is also shortened, and the watching experience of a user is influenced.

The above information disclosed in this background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is not known to a person of ordinary skill in the art in this country.

Disclosure of Invention

In view of the defects in the prior art, an object of the present invention is to provide a pixel compensation circuit and a display device, which overcome the defects in the prior art, compensate the voltage drop of the voltage source caused by the resistance of the trace, and improve the brightness uniformity.

According to an aspect of the present invention, there is provided a pixel compensation circuit including:

a first transistor, wherein a first pole of the first transistor is coupled to a data signal, a second pole of the first transistor is coupled to a first node, and a grid of the first transistor is coupled to a second scanning signal;

a second transistor, wherein a first pole of the second transistor is coupled to the first node, a second pole of the second transistor is coupled to a second node, and a gate of the second transistor is coupled to a fourth node;

a first switch element, wherein a first terminal of the first switch element is coupled to the second node, a second terminal of the first switch element is coupled to the fourth node, and a control terminal of the first switch element is coupled to the second scan signal;

a second switch element, wherein a first terminal of the second switch element is coupled to an initialization signal, a second terminal of the second switch element is coupled to the fourth node, and a control terminal of the second switch element is coupled to a first scan signal;

a fifth transistor, wherein a first pole of the fifth transistor is coupled to the second node, a second pole of the fifth transistor is coupled to a third node, and a gate of the fifth transistor is coupled to an enable signal;

a sixth transistor, wherein a first pole of the sixth transistor is coupled to the first node, a second pole of the sixth transistor is coupled to a positive pole of a voltage source, and a gate of the sixth transistor is coupled to the enable signal;

a tenth transistor, having a first terminal coupled to the positive terminal of the voltage source, a second terminal coupled to a fifth node, and a gate coupled to the enable signal;

a ninth transistor, a first pole of which is coupled to the fifth node, a second pole of which is coupled to a reference voltage, and a gate of which is coupled to a second scan signal;

a capacitor having a first terminal coupled to the fifth node and a second terminal coupled to the fourth node; and

and the anode of the light-emitting diode is coupled with the third node, and the cathode of the light-emitting diode is coupled with the cathode of a voltage source.

Preferably, the first transistor, the second transistor, the fifth transistor, the sixth transistor, the ninth transistor, and the tenth transistor are all PMOS transistors.

Preferably, the first switch element is a third transistor, a first pole of the third transistor is coupled to the second node, a second pole of the third transistor is coupled to the fourth node, and gates of the third transistors are coupled to the second scan signal.

Preferably, the third transistor is a PMOS transistor.

Preferably, the first switching element includes a third transistor and a fourth transistor, wherein:

a first pole of the third transistor is coupled to the second node, a second pole of the third transistor is coupled to a first pole of the fourth transistor, a second pole of the fourth transistor is coupled to the fourth node, and gates of the third transistor and the fourth transistor are coupled to the second scan signal.

Preferably, the third transistor and the fourth transistor are both PMOS transistors.

Preferably, the second switch element is a seventh transistor, a first pole of the seventh transistor is coupled to the initialization signal, a second pole of the seventh transistor is coupled to the fourth node, and gates of the seventh transistors are coupled to the first scan signal.

Preferably, the seventh transistor is a PMOS transistor.

Preferably, the second switching element includes a seventh transistor and an eighth transistor, wherein:

a first pole of the seventh transistor is coupled to the initialization signal, a second pole of the seventh transistor is coupled to the first pole of the eighth transistor, a second pole of the eighth transistor is coupled to the fourth node, and gates of the seventh transistor and the eighth transistor are both coupled to the first scan signal.

Preferably, the seventh transistor and the eighth transistor are both PMOS transistors.

According to another aspect of the invention, a display device is also provided, which comprises the pixel compensation circuit.

According to another aspect of the present invention, there is also provided a display device including:

a plurality of data lines for transmitting data signals for displaying image signals;

a plurality of scan lines for transmitting scan signals; and

a plurality of stages of pixel circuits formed on a plurality of pixels defined by the data lines and the scan lines, respectively;

each stage of pixel circuit includes:

a first transistor for switching a current path between a first node and a data signal in response to a present-stage scan signal;

a second transistor for switching a current path between the first node and the second node in response to a signal of the fourth node;

a first switching element for switching a current path between a second node and a fourth node in response to the present stage scan signal;

a second switching element for switching a current path between a fourth node and an initialization signal in response to the previous stage scan signal;

a fifth transistor for switching a current path between the second node and a light emitting diode for emitting light corresponding to the supplied current in response to an enable signal;

a sixth transistor for switching a current path between the first node and the positive electrode of the voltage source in response to an enable signal;

a tenth transistor for switching a current path between the fifth node and the positive electrode of the voltage source in response to an enable signal;

a ninth transistor for switching a current path between a fifth node and a reference voltage in response to a present-stage scan signal; and

a capacitor having a first terminal coupled to the fifth node and a second terminal coupled to the fourth node.

Compared with the prior art, due to the adoption of the technology, the pixel compensation circuit and the display device in the invention use the TFT device composition circuit as few as possible to compensate the voltage drop of the voltage source caused by the resistance value of the wiring, so that the driving current of the OLED display device is not influenced by the voltage drop of the voltage source on the display panel, the deviation between the driving current values at different positions of the display panel and the currently set driving current value is reduced as much as possible, the brightness uniformity of the display panel is improved, and the watching experience of a user is improved.

Drawings

Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:

FIG. 1 is a circuit diagram of a pixel compensation circuit according to the present invention;

FIG. 2 is a circuit diagram of another pixel compensation circuit according to the present invention;

FIG. 3 is a driving waveform diagram of the pixel compensation circuit according to the present invention;

FIG. 4 is a diagram illustrating a conducting state of the pixel compensation circuit at stage A of FIG. 3;

FIG. 5 is a diagram illustrating a conducting state of the pixel compensation circuit at stage B in FIG. 3;

FIG. 6 is a diagram illustrating a conducting state of the pixel compensation circuit at stage C of FIG. 3;

FIG. 7 is a diagram illustrating a conducting state of the pixel compensation circuit at stage D in FIG. 3;

FIG. 8 is a diagram illustrating a conducting state of the pixel compensation circuit at stage E in FIG. 3;

FIG. 9 is a schematic diagram of the current variation at different voltages without the pixel compensation circuit of the present invention; and

FIG. 10 is a schematic diagram of the current variation at different voltages after the pixel compensation circuit of the present invention is used.

Reference numerals

M1 first transistor

M2 second transistor

M3 third transistor

M4 fourth transistor

M5 fifth transistor

M6 sixth transistor

M7 seventh transistor

M8 eighth transistor

M9 ninth transistor

M10 tenth transistor

C capacitor

XD light emitting diode

N1 first node

N2 second node

N3 third node

Fourth node of N4

N5 fifth node

N6 sixth node

dl5 data signal

Positive pole of ELVDD voltage source

Negative pole of ELVSS voltage source

Vin initialization voltage

ref reference voltage

En enable signal

Sn-1 first scanning signal

Sn second scanning signal

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their repetitive description will be omitted.

The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention may be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In some instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring the invention.

As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having" or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a method, article, or apparatus that comprises a list of features is not necessarily limited to only those features but may include other features not expressly listed or inherent to such method, article, or apparatus. Further, unless expressly stated to the contrary, "or" refers to an inclusive or, and not to an exclusive or. For example, condition a or B is satisfied by either: a is true (or present) and B is false (or not present), a is false (or not present) and B is true (or present), and both a and B are true (or present).

Also, the use of "a" or "an" is used to describe elements and components described herein. This is done merely for convenience and to provide a general sense of the scope of the invention. This description should be read to include one or at least one and the singular also includes the plural and vice versa unless it is obvious that it is meant otherwise. For example, when a single item is described herein, more than one item may be used in place of a single item. Similarly, when more than one article is described herein, a single article may replace more than one article.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The materials, methods, and examples are illustrative only and not intended to be limiting. To the extent not described herein, many details regarding specific materials and processing acts are conventional and may be found in textbooks and other sources within the inorganic layer deposition arts and corresponding manufacturing arts.

Fig. 1 is a circuit diagram of a pixel compensation circuit according to the present invention. As shown in fig. 1, the pixel compensation circuit of the present invention includes a first transistor M1, a second transistor M2, a third transistor M3, a fifth transistor M6, a seventh transistor M7, a ninth transistor M9, a tenth transistor M10, a capacitor C, and a diode XD.

The connection mode of each transistor is as follows:

the first transistor M1 has a first terminal coupled to a data signal dI5, a second terminal coupled to a first node N1, and a gate coupled to a second scan signal Sn.

The second transistor M2 has a first electrode coupled to the first node N1, a second electrode coupled to a second node N2, and a gate coupled to a fourth node N4.

The first switch element has a first terminal coupled to the second node N2, a second terminal coupled to the fourth node N4, and a control terminal coupled to the second scan signal Sn. In this embodiment, the first switch element is a third transistor M3, but not limited thereto. A first pole of the third transistor M3 is coupled to the second node N2, a second pole of the third transistor M3 is coupled to the fourth node N4, and gates of the third transistors M3 are coupled to the second scan signal Sn.

The second switch element has a first terminal coupled to an initialization signal Vin, a second terminal coupled to the fourth node N4, and a control terminal coupled to the first scan signal Sn-1. In this embodiment, the second switch element is a seventh transistor M7, a first pole of the seventh transistor M7 is coupled to the initialization signal Vin, a second pole of the seventh transistor M7 is coupled to the fourth node, and gates of the seventh transistors M7 are coupled to the first scan signal Sn-1.

The fifth transistor M5 has a first terminal coupled to the second node N2, a second terminal coupled to a third node N3, and a gate coupled to an enable signal En.

The sixth transistor M6 has a first electrode coupled to the first node N1, a second electrode coupled to a positive electrode ELVDD of a voltage source, and a gate coupled to the enable signal En.

The tenth transistor M10 has a first electrode coupled to the positive electrode ELVDD, a second electrode coupled to a fifth node N5, and a gate coupled to the enable signal En.

The ninth transistor M9 has a first electrode coupled to the fifth node N5, a second electrode coupled to a reference voltage ref, and a gate coupled to a second scan signal Sn.

The first terminal of the capacitor C is coupled to the fifth node N5, and the second terminal is coupled to the fourth node N4. And

the anode of the light emitting diode XD is coupled to the third node N3, and the cathode thereof is coupled to a voltage source cathode ELVSS.

The first transistor M1, the second transistor M2, the third transistor M3, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the ninth transistor M9 and the tenth transistor M10 are all PMOS transistors. The first pole of each transistor is the source pole, namely the s pole; the second pole of each transistor is a drain electrode, namely a d pole; the gate is the g-pole.

Wherein the width-to-length ratio parameters of the respective transistors are selected as follows:

the width-to-length ratio of the second transistor M2 is: length 3.5um, length 40 um; the width-to-length ratios of the transistors other than the second transistor M2, i.e., the first transistor M1, the third transistor M3, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the ninth transistor M9, and the tenth transistor M10 are: length 3.3um, width 3.6um, but not limited to this.

In practical applications, other types of transistors can be used for each transistor, and the width-to-length ratio parameter of each transistor is not limited to the above-listed values; in addition, the first double-gate transistor and the second double-gate transistor can be made on the same substrate with two gates

The structure is characterized in that parameters of the conduction voltage and the saturation voltage of each double-gate transistor are correspondingly adjusted; the purpose of the present invention, that is, the voltage drop of the voltage of the compensation voltage source in the display panel due to the resistance of the trace, is all within the protection scope of the present invention.

Fig. 2 is a circuit diagram of another pixel compensation circuit according to the present invention. In another modification, the pixel compensation circuit of the present invention includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, a capacitor C, and a diode XD.

The connection mode of each transistor is as follows:

The first switch element has a first terminal coupled to the second node N2, a second terminal coupled to the fourth node N4, and a control terminal coupled to the second scan signal Sn. In this embodiment, the first switch element includes a third transistor M3 and a fourth transistor M4, wherein: a first pole of the third transistor M3 is coupled to the second node N2, a second pole of the third transistor M3 is coupled to a first pole of the fourth transistor M4, a second pole of the fourth transistor M4 is coupled to the fourth node, and gates of the third transistor M3 and the fourth transistor M4 are coupled to the second scan signal Sn.

The second switch element has a first terminal coupled to an initialization signal Vin, a second terminal coupled to the fourth node N4, and a control terminal coupled to the first scan signal Sn-1. In this embodiment, the second switch element includes a seventh transistor M7 and an eighth transistor M8, wherein: a first pole of the seventh transistor M7 is coupled to the initialization signal Vin, a second pole of the seventh transistor M7 is coupled to a first pole of the eighth transistor M8, a second pole of the eighth transistor M8 is coupled to the fourth node, and gates of the seventh transistor M7 and the eighth transistor M8 are coupled to the first scan signal Sn-1.

The first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9 and the tenth transistor M10 are all PMOS transistors. The first pole of each transistor is the source, i.e., s pole, and the second pole of each transistor is the drain, i.e., d pole. Wherein the width-to-length ratio parameters of the respective transistors are selected as follows:

the width-to-length ratio of the second transistor M2 is: length 3.5um, length 40 um; the width-to-length ratios of the transistors other than the second transistor M2, i.e., the first transistor M1, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 are: length 3.3um, width 3.6um, but not limited to this.

Since, the third transistor M3 and the fourth transistor M4 function as a first double-gate transistor, and the seventh transistor M7 and the eighth transistor M8 function as a second double-gate transistor. The dual-gate transistor has a larger threshold voltage (Vth) than the single-gate transistor, and the pixel compensation circuit in fig. 2 has a lower leakage current.

The technical scheme of the invention adopts a data signal dl5, an enable signal En, a first scan signal Sn-1 and a second scan signal Sn, wherein the waveform diagrams of the enable signal En, the first scan signal Sn-1 and the second scan signal Sn are shown in FIG. 3. The voltage states of the other signal input ends are as follows: the positive electrode ELVDD of the voltage source is a positive voltage, the negative electrode ELVSS of the voltage source is a negative voltage, the initialization voltage Vin is a negative voltage, and the reference voltage ref is a positive voltage. The voltage source anode ELVDD is a voltage source for supplying current, and generates a continuous and stable voltage when the AMOLED emits light, so that a continuous current flows through the ELVDD; the negative voltage source ELVSS is the cathode potential of the OLED display element.

FIG. 3 is a driving waveform diagram of the pixel compensation circuit of the present invention. Fig. 4 is a schematic diagram of the conducting state of the pixel compensation circuit at stage a in fig. 3. Fig. 5 is a schematic diagram of the on state of the pixel compensation circuit at stage B in fig. 3. Fig. 6 is a schematic diagram of the conducting state of the pixel compensation circuit at stage C in fig. 3. Fig. 7 is a schematic diagram of the conducting state of the pixel compensation circuit at the stage D in fig. 3. Fig. 8 is a schematic diagram of the conducting state of the pixel compensation circuit at stage E in fig. 3. In conjunction with fig. 4 to 8, the on states of the pixel compensation circuit in fig. 1 are respectively described through A, B, C, D, E stages of the waveform diagram in fig. 3. The cross numbers in fig. 4 to 8 indicate that the corresponding transistor is not currently conducting. (the working of each transistor in different time states is only specifically described below by using the pixel compensation circuit with 8 transistors and 1 capacitor as shown in fig. 1, but not limited thereto, for example, the working of the transistor in the pixel compensation circuit with 10 transistors in fig. 2 is the same, and is not described here again)

As shown in fig. 4, that is, when the waveform diagram of fig. 2 is in the state a, the enable signal En is at a high level, the first scan signal Sn-1 is at a low level, and the second scan signal Sn is at a high level. The transistors crossed in the figure are not conductive at present, i.e., the first transistor M1, the third transistor M3, the fifth transistor M5, the sixth transistor M6, the ninth transistor M9 and the tenth transistor M10 are not conductive.

At this time, the voltage of the initialization voltage Vin is written in the fourth node N4.

As shown in fig. 5, that is, when the waveform diagram of fig. 2 is in the state B, the enable signal En is at a high level, the first scan signal Sn-1 is at a high level, and the second scan signal Sn is at a high level. The transistors that are cross-hatched in the figure are not conductive at present, i.e. seven transistors are not conductive except for the second transistor M2.

At this time, the fourth node N4 maintains the voltage of the initialization voltage Vin.

As shown in fig. 6, that is, when the waveform diagram of fig. 2 is in the C state, the enable signal En is at a high level, the first scan signal Sn-1 is at a high level, and the second scan signal Sn is at a low level. The transistors crossed in the figure are not conducting at present, i.e. the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the tenth transistor M10 are not conducting.

At this time, the data signal voltage is written to the fourth node N4 through the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 until the second transistor M2 enters a cut-off region and the fifth node N5 maintains the reference voltage ref. At this time, the voltages of the fourth node N4 and the fifth node N5 satisfy the following formula:

Vn4＝Vdata+Vth

Vn5＝Vref

where Vn4 is the voltage of the fourth node N4, Vn5 is the voltage of the fifth node N5, Vdata is the voltage of the data signal dl5, Vth is the threshold voltage of the second transistor M2, and Vref is the reference voltage ref.

As shown in fig. 7, that is, when the waveform diagram of fig. 2 is in the D state, the enable signal En is at a high level, the first scan signal Sn-1 is at a high level, and the second scan signal Sn is at a high level. The transistors crossed in the drawing are not conductive at present, i.e., all eight transistors from the first transistor M1 to the tenth transistor M10 are not conductive.

At this time, the fourth node N4 remains Vdata + Vth, and the fifth node N5 remains Vref.

As shown in fig. 8, that is, when the waveform diagram of fig. 2 is in the E state, the enable signal En is at a low level, the first scan signal Sn-1 is at a high level, and the second scan signal Sn is at a high level. The transistors cross in the figure are not conducting at present, i.e. the first transistor M1, the third transistor M3, the seventh transistor M7, the ninth transistor M9 are not conducting.

At this time, the positive ELVDD voltage is written to the fifth node N5, and the voltage at the fourth node N4 also changes due to the coupling effect of the capacitor C. The voltages of the fourth node N4 and the fifth node N5 satisfy the following equations:

Vn5＝Velvdd＝Vs

Vn4＝Vdata+Vth+Velvdd-Vref＝Vg

wherein Vs is the source voltage of the second transistor M2, Vg is the gate voltage of the second transistor M2, and Velvdd is the voltage of the positive electrode of the voltage source. The current Id from the second transistor M2 to the fifth transistor M5, i.e., the current value flowing through the light emitting diode XD satisfies the following formula:

Id＝μCW/L(Vsg+Vth)^2

＝μCW/L(Vref-Vdata)^2

where C is the amount of capacitance of the capacitor in the DC circuit, W is the electrical work, and M is the electrical permeability. As can be seen from the above current formula, this current value is independent of the ELVDD voltage source.

FIG. 9 is a schematic diagram of the current variation at different voltages without using the pixel compensation circuit of the present invention. FIG. 10 is a schematic diagram of the current variation at different voltages after the pixel compensation circuit of the present invention is used. Fig. 9 and 10 show the change of current when the pixel compensation circuit of the present invention is not used and when the compensation circuit of the present invention is used, respectively.

As shown in fig. 9, when the voltage of the voltage source positive electrode ELVDD is 5.1V and 4.6V, respectively, and the current Id changes, it can be seen that the current change value reaches 70nA when the voltage of ELVDD changes by 0.5V. As shown in fig. 10, in order to change the current Id when the voltage of the voltage source positive electrode ELVDD is 5.1V and 4.6V, respectively, after the pixel compensation circuit of the present invention is used, it can be seen that the current change value is only 3nA when the voltage of ELVDD changes by 0.5V.

As can be seen from fig. 9 and 10, the pixel compensation circuit of the present invention reduces the current variation value from 70nA to 3nA, which greatly improves the current variation.

In a comparative example of voltage variation of one voltage source positive electrode ELVDD, the following table shows:

as can be seen from the above table, when the ELVDD varies by 0.5V, Vgs (the voltage between the gate and the source of the second transistor M2) driving the second transistor M2 varies by only 0.003V, and the current decision and Vgs are well compensated by the ELVDD voltage.

The invention also provides a display device which comprises the pixel compensation circuit. The display device adopting the pixel compensation circuit can effectively improve the brightness uniformity of the display panel, and the working principle of the display device is the principle of the pixel compensation circuit, which is not repeated herein.

a plurality of scan lines for transmitting scan signals; and

each stage of pixel circuit includes:

Similarly, the display device can effectively improve the brightness uniformity of the display panel, and the working principle of the display device, namely the principle of the pixel compensation circuit, is not described herein again.

In summary, in the pixel compensation circuit and the display device of the invention, the TFT device composition circuit which is as few as possible is used to compensate the voltage drop of the voltage source due to the resistance of the routing, so that the driving current of the OLED display device is not affected by the voltage drop of the voltage source on the display panel, the deviation between the driving current value at different positions of the display panel and the currently set driving current value is reduced as much as possible, the brightness uniformity of the display panel is improved, and the viewing experience of the user is improved.

The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes and modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention.

Claims

1. A pixel compensation circuit, comprising:

a third transistor, wherein the third transistor is a PMOS transistor, a first pole of the third transistor is coupled to the second node, a second pole of the third transistor is coupled to the fourth node, gates of the third transistors are coupled to the second scan signal, and the third transistor is configured to switch a current path between the second node and the fourth node in response to the second scan signal;

a seventh transistor, wherein the seventh transistor is a PMOS transistor, a first pole of the seventh transistor is coupled to the initialization signal, a second pole of the seventh transistor is coupled to the fourth node, gates of the seventh transistors are coupled to the first scan signal, and the seventh transistor is configured to switch a current path between the fourth node and the seventh node in response to the previous scan signal;

2. The pixel compensation circuit of claim 1, wherein the first, second, fifth, sixth, ninth, and tenth transistors are all PMOS transistors.

3. A display device comprising the pixel compensation circuit according to claim 1 or 2.

4. A display device, comprising:

a plurality of scan lines for transmitting scan signals; and

each stage of pixel circuit includes:

a third transistor, wherein the third transistor is a PMOS transistor, a first pole of the third transistor is coupled to the second node, a second pole of the third transistor is coupled to the fourth node, gates of the third transistors are coupled to the second scan signal, and the third transistor is configured to switch a current path between the second node and the fourth node in response to the current scan signal;

a seventh transistor, wherein the seventh transistor is a PMOS transistor, a first pole of the seventh transistor is coupled to the initialization signal, a second pole of the seventh transistor is coupled to the fourth node, gates of the seventh transistors are coupled to the first scan signal, and the seventh transistor is configured to switch a current path between the fourth node and the initialization signal in response to the previous scan signal;

a ninth transistor for switching a current path between a fifth node and a reference voltage in response to a present-stage scan signal;