CN112528577B - Clock reset circuit management method, device and computer storage medium - Google Patents

Abstract

The embodiment of the present application discloses a management method, device and computer storage medium for a clock reset circuit. The method comprises: obtaining a design file of the clock reset circuit; obtaining configuration information of ports and submodules in each module of the clock reset circuit from the design file according to a preset basic functional unit; generating a global link table of the clock reset circuit according to the configuration information corresponding to each module, wherein the global link table is a description of the link relationship of the modules in the clock reset circuit using the basic functional unit; generating a block diagram file of the clock reset circuit according to the global link table.

Description

Management method, device and computer storage medium for clock reset circuit

Technical Field

The embodiments of the present application relate to the field of information processing, and in particular to a management method, device and computer storage medium for a clock reset circuit.

Background Art

With the development of integrated circuit technology, the scale of circuit integration is getting larger and larger; the popularization of information and communication technology has made the scope of integrated circuit application wider and wider, and the demand has become more and more diverse; making the design of integrated circuits more and more complex, and the circuit design of multiple clock domains, multiple reset domains, and multiple power domains is becoming more and more common. With the continuous surge of intelligent and customized needs, the design of SOC (System On Chip) is also becoming more and more common. In circuit design, especially SOC design, the design of clock reset is accompanied by multiple clock domains, and the demand for multiple reset domains is becoming larger and larger, and the complexity is getting higher and higher; at the same time, the addition of DFT (Design For Test, text design) technology has further aggravated the complexity of clock reset design. The introduction of SOC design makes clock reset dynamically configurable, and the complexity is further aggravated.

Clock reset design is related to whether the entire chip can be used normally, and a reliable verification method for clock reset is becoming more and more important. At present, most verification methods focus on monitoring the quality of clock signals, the quality of reset signals, the impact of asynchronous clock design on circuits, and how to build the verification environment of the entire SOC system.

In circuit design, a module is often designed to centrally manage the clock reset of the system (CRM ClockReset Module); this design is in line with the methodology of chip design, modularized and cohesive; it is adopted by most design manufacturers. For the design verification of the entire clock reset system, the following methods are used in related technologies:

1. The dynamic simulation method is used to detect the output of the clock reset under different configurations of the clock reset and to check the quality of the clock reset;

2. Manual inspection method: manual review, peer review of code design; adding assertions for clock reset to check and confirm;

3. Write the link relationship of the clock reset as an assertion and check it through the formal verification tool.

The above methods are widely used in the industry. In addition, there are certain inadequacies in the verification method that only uses dynamic simulation. For example, swapping the order of Buf and clock gating does not affect the final clock output, but it may cause inconsistency with the original design intention; it is necessary to combine manual or assertion methods. The assertion verification method requires that the manual writing of link relationship assertions and manual review have similar workloads.

In the process of manual inspection, it is necessary to analyze the code design and connection status line by line, or use some general tools (Verdi) to check the connection relationship and compare it with the system block diagram of the clock reset design. This operation method is inefficient on the one hand, and on the other hand, general tools need to manually track the clock reset links that cross levels layer by layer.

Summary of the invention

In order to solve any of the above technical problems, the embodiments of the present application provide a management method, device and computer storage medium for a clock reset circuit.

In order to achieve the purpose of the embodiment of the present application, the embodiment of the present application provides a management method of a clock reset circuit, including:

Obtain the design file of the clock reset circuit;

According to the preset basic functional units, obtaining configuration information of ports and submodules in each module of the clock reset circuit from the design file;

Generate global link information of the clock reset circuit according to the configuration information corresponding to each module, wherein the global link information is description information of link relationships of modules in the clock reset circuit using the basic functional units;

A block diagram file of the clock reset circuit is generated according to the global link information.

In an exemplary embodiment, generating the global link information of the clock reset circuit according to the configuration information corresponding to each module includes:

Generate link information based on a basic clock reset unit corresponding to each module according to configuration information corresponding to each module, wherein the link information includes link information between a port of each module and a submodule within the module and link information between submodules within the module;

According to the link information corresponding to each module, determining one or at least two groups of modules having a link path;

The link information of one or at least two groups of modules having a link path is processed to obtain global link information based on a basic clock reset unit.

In an exemplary embodiment, the step of determining one or at least two groups of modules having a link path according to link information corresponding to each module includes:

Obtain the name information of the signal transmitted by the port in the link information corresponding to each module;

Query whether there is a port transmitting a signal with the same name among the ports of the clock reset circuit;

After finding a port that transmits a signal with the same name, a target module corresponding to the port is determined, and the target module is regarded as a group of modules that have a link path.

In an exemplary embodiment, after generating a block diagram file of the clock reset circuit according to the global link information, the method further includes:

Obtaining a checking strategy for a clock reset circuit;

According to the detection strategy, the design information described in the block diagram file is checked.

In an exemplary embodiment, after generating a block diagram file of the clock reset circuit according to the global link information, the method further includes:

Obtain a debugging strategy for a clock reset circuit;

According to the debugging strategy, the design information described in the block diagram file is modified.

A management device for a clock reset circuit includes a processor and a memory, wherein the memory stores a computer program, and the processor calls the computer program in the memory to implement the following operations, including:

Obtain the design file of the clock reset circuit;

According to the preset basic functional units, obtaining configuration information of ports and submodules in each module of the clock reset circuit from the design file;

Generate global link information of the clock reset circuit according to the configuration information corresponding to each module, wherein the global link information is description information of link relationships of modules in the clock reset circuit using the basic functional units;

A block diagram file of the clock reset circuit is generated according to the global link information.

In an exemplary embodiment, the processor calls the computer program in the memory to implement the operation of generating the global link information of the clock reset circuit according to the configuration information corresponding to each module, including:

Generate link information based on a basic clock reset unit corresponding to each module according to configuration information corresponding to each module, wherein the link information includes link information between a port of each module and a submodule within the module and link information between submodules within the module;

According to the link information corresponding to each module, determining one or at least two groups of modules having a link path;

The link information of one or at least two groups of modules having a link path is processed to obtain global link information based on a basic clock reset unit.

In an exemplary embodiment, the processor calls the computer program in the memory to implement the operation of determining one or at least two groups of modules having a link path according to the link information corresponding to each module, including:

Obtain the name information of the signal transmitted by the port in the link information corresponding to each module;

Query whether there is a port transmitting a signal with the same name among the ports of the clock reset circuit;

After finding a port that transmits a signal with the same name, a target module corresponding to the port is determined, and the target module is regarded as a group of modules that have a link path.

In an exemplary embodiment, after the processor calls the computer program in the memory to implement the operation of generating a block diagram file of the clock reset circuit according to the global link information, the processor calls the computer program in the memory to further implement the following operations, including:

Obtaining a checking strategy for a clock reset circuit;

According to the detection strategy, the design information described in the block diagram file is checked.

In an exemplary embodiment, after the processor calls the computer program in the memory to implement the operation of generating a block diagram file of the clock reset circuit according to the global link information, the processor calls the computer program in the memory to further implement the following operations, including:

Obtain a debugging strategy for a clock reset circuit;

According to the debugging strategy, the design information described in the block diagram file is modified.

A computer storage medium, wherein the computer readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement any of the methods described above.

The embodiments provided in the embodiments of this application,

Other features and advantages of the embodiments of the present application will be described in the subsequent description, and partly become apparent from the description, or can be understood by implementing the embodiments of the present application. The purpose and other advantages of the embodiments of the present application can be achieved and obtained by the structures specifically pointed out in the description, claims and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are used to provide further understanding of the technical solutions of the embodiments of the present application and constitute a part of the specification. Together with the embodiments of the embodiments of the present application, they are used to explain the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions of the embodiments of the present application.

FIG1 is a flow chart of a method for managing a clock reset circuit provided in an embodiment of the present application;

FIG2 is a structural diagram of a management device for a clock reset circuit provided in an embodiment of the present application;

FIG. 3 is a schematic diagram of a computer storage medium provided in an embodiment of the present application.

DETAILED DESCRIPTION

In order to make the purpose, technical solution and advantages of the embodiments of the present application more clear, the embodiments of the present application will be described in detail in conjunction with the accompanying drawings. It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other arbitrarily.

FIG1 is a flow chart of a method for managing a clock reset circuit provided in an embodiment of the present application. The method shown in FIG1 includes:

Step 101, obtaining a design file of a clock reset circuit;

Step 102: According to the preset basic functional units, obtain the configuration information of the ports and submodules in each module of the clock reset circuit from the design file;

In an exemplary embodiment, the configuration information of each module is determined by the name of each module, and the configuration information includes at least one of the following: the name of the signal linked to the port, the input and output properties of the port, the instantiation name of the sub-module instantiated in the module, the module definition name, the port name of the module, and the instantiation link name of the port;

In an example embodiment, the basic functional unit may be a clock buffer (Buf), a clock gate, a clock divider, a clock multiplexer, a DFT clock multiplexer, a DFT clock buffer, a reset controller, etc.;

Step 103: Generate global link information of the clock reset circuit according to the configuration information corresponding to each module, wherein the global link information is description information of the link relationship of the modules in the clock reset circuit using the basic functional unit;

In an exemplary embodiment, the configuration information describes the components included in the clock reset circuit in the basic functional unit; using the configuration information and the port information in the configuration information, the link information of the basic functional unit is determined, and the link relationship of the components in the clock reset circuit is determined;

Step 104: Generate a block diagram file of the clock reset circuit according to the global link information.

The method provided in the embodiment of the present application obtains the design file of the clock reset circuit, obtains the configuration information of the ports and sub-modules in each module in the clock reset circuit from the design file according to the pre-set basic functional units, generates the global link information of the clock reset circuit according to the configuration information corresponding to each module, and generates the block diagram file of the clock reset circuit according to the global link information, thereby achieving the purpose of automatically generating the clock reset block diagram and overcoming the problem of long time for manual block diagram drawing in the related art.

The method provided in the embodiment of the present application is described below:

In an exemplary embodiment, generating the global link information of the clock reset circuit according to the configuration information corresponding to each module includes:

Generate link information based on a basic clock reset unit corresponding to each module according to configuration information corresponding to each module, wherein the link information includes link information between a port of each module and a submodule within the module and link information between submodules within the module;

According to the link information corresponding to each module, determining one or at least two groups of modules having a link path;

The link information of one or at least two groups of modules having a link path is processed to obtain global link information based on a basic clock reset unit.

According to the configuration information of the port in the module, the sub-module connected to the port is determined, and then the link information between the sub-modules is determined according to the name of the signal between the sub-modules via the port, so as to obtain the link information of each module; after obtaining the link information of each module, one or at least two groups of modules having a link path are determined with the help of the characteristics of the signal transmitted between the modules; after determining the link relationship between the modules, the link of the modules is iterated to obtain the global link information of the clock reset circuit.

In an exemplary embodiment, the step of determining one or at least two groups of modules having a link path according to link information corresponding to each module includes:

Obtain the name information of the signal transmitted by the port in the link information corresponding to each module;

Query whether there is a port transmitting a signal with the same name among the ports of the clock reset circuit;

After finding a port that transmits a signal with the same name, a target module corresponding to the port is determined, and the target module is regarded as a group of modules that have a link path.

When designing a clock reset circuit, an example name of the transmission signal is set for the port of the module to distinguish the transmitted signal. When determining the link information between modules, the name of the signal transmitted by the port can be used to determine the connected modules, so as to achieve the purpose of automatically obtaining the link information between modules by cleverly utilizing the existing information.

In an exemplary embodiment, after generating a block diagram file of the clock reset circuit according to the global link information, the method further includes:

Obtaining a checking strategy for a clock reset circuit;

According to the detection strategy, the design information described in the block diagram file is checked.

The checking strategy can be the checking rules input by the user, for example, clock gating is placed before the divider; reset needs to pass through the output, etc.; after obtaining the checking strategy, the structure diagram defined by the checking strategy is parsed; the structure diagram can be obtained by parsing, the obtained block diagram file can be compared, the design can be checked, and the illegal parts in the block diagram file can be output.

After the offending part is output in the block diagram file, the offending part selected by the user is received, and the offending part is modified according to the structure diagram corresponding to the inspection rule.

In an exemplary embodiment, after generating a block diagram file of the clock reset circuit according to the global link information, the method further includes:

Obtain a debugging strategy for a clock reset circuit;

According to the debugging strategy, the design information described in the block diagram file is modified.

The debug strategy is used to confirm whether the clock or reset can work properly in the chip;

After obtaining the debugging strategy, the clock reset signal can be set to the chip pin for observation, and the MUX design of automatically adding the clock and reset for debugging can be realized, thereby improving design efficiency.

The method provided in the embodiment of the present application is described below:

In order to solve at least one of the problems of low efficiency of manual code tracing in the prior art and inconvenience of using circuit diagram-assisted tracing for multi-level clock reset design, the embodiments of the present application provide the following solutions, including:

Step 201, configuring a basic functional unit (module) in a clock reset system;

In an example embodiment, the basic functional unit may be a clock buffer (Buf), a clock gate, a clock divider, a clock multiplexer, a DFT clock multiplexer, a DFT clock buffer, a reset controller, etc.;

Step 202: After obtaining the design file of the clock reset circuit, obtain the configuration information of the ports and submodules in each module from the design file;

In an exemplary embodiment, the design file of the clock reset circuit may be in HDL format or Verilog format.

In an exemplary embodiment, the HDL file is analyzed by regular expressions to extract required information from the HDL file.

In an exemplary embodiment, the configuration information of the ports and submodules may be obtained by:

Clear the comments in the module description information in the design file to remove invalid information;

Extract the name information of the module, the name information of the signal transmitted by the port, and the input and output properties of the port; and extract the instantiation name of the sub-module instantiated in the module, the definition name of the module, the port name of the module, and the instantiation link name of the port; and so on, traverse all modules of the clock reset design until the basic functional unit is parsed, and then stop analyzing its internal design.

Step 203: Determine a global link table based on a basic clock reset unit of a clock reset circuit according to the configuration information of ports and submodules corresponding to each module; wherein the global link table includes link information between ports and submodules of each module and link information between submodules within each module;

In an exemplary embodiment, the global link relationship is continuously iterated based on the example name matching of the port link. For example, if the example name of the signal transmitted by port 1 of module 1 and port 1 of module 2 is the same, and the example name of the signal transmitted by port 2 of module 2 and port 1 of module 3 is the same, then by iterating the link information of the above three modules, it can be determined that module 1, module 2 and module 3 are connected in sequence.

In step D, it is displayed by means of a graphic language; step 204, using a preset graphic generation strategy, the global link table is processed to obtain a design block diagram file corresponding to the global link table;

In an exemplary embodiment, the global link table is based on the link information described by the basic clock reset unit, and the clock reset block diagram can be generated correspondingly by using the icon of the basic clock reset unit stored in the graphic generation strategy.

In an exemplary embodiment, a SVG-based graphics system may be used, displayed in HTML, and opened through a browser.

After obtaining the block diagram file, you can use it for any of the following purposes, including:

The output block diagram can be delivered to the chip product as a design manual. Compared with manually drawn block diagrams, the block diagram output by the method provided in the embodiment of the present application can ensure a more regular drawing style, or customize the display effects with different levels of detail according to needs to meet different needs; such as hiding the clock BUF, displaying the reset source of the clock divider, etc.

The generated block diagram file is manually compared with the block diagram file used in the clock reset system design; since the generated block diagram and the block diagram used in the design are highly similar, they are easy to compare, thereby improving the efficiency of manual inspection.

It is possible to detect violations in the design based on the design rules defined by the user. For example, if all resets need to be synchronized with the clock, it will detect whether the reset signal has passed through the synchronizer. Otherwise, it will report an error to guide the design engineer, or automatically add a synchronizer based on the user's operation request.

After the clock reset design is completed, in order to confirm whether the clock or reset can work normally in the chip, the clock reset signal is sent to the pin of the chip for observation. By using the present invention, according to the clock and reset signals specified by the use case, the MUX logic of the clock signal and the reset signal is added in the design, so as to achieve the purpose of automatically adding the MUX design of the clock and reset for debugging, and improve the design efficiency.

Compared with the prior art, the method provided in the embodiment of the present application has achieved progress in the method of verifying the clock reset system, achieved the effect of improving the clock reset verification, saved the time of clock reset system verification, and improved the efficiency of clock reset verification. At the same time, it also plays a beneficial role in assisting development and design, reducing the work of developing and adjusting the reset block diagram; and the design of automatically adding debugging logic has brought objective beneficial effects on the testing and use of the chip.

FIG2 is a structural diagram of a clock reset circuit management device provided in an embodiment of the present application. The device shown in FIG2 includes a processor 201 and a memory 202, wherein the memory 202 stores a computer program, and the processor 201 calls the computer program in the memory 202 to implement the following operations, including:

Obtain the design file of the clock reset circuit;

According to the preset basic functional units, obtaining configuration information of ports and submodules in each module of the clock reset circuit from the design file;

Generate global link information of the clock reset circuit according to the configuration information corresponding to each module, wherein the global link information is description information of link relationships of modules in the clock reset circuit using the basic functional units;

A block diagram file of the clock reset circuit is generated according to the global link information.

In an exemplary embodiment, the processor 201 calls the computer program in the memory 202 to implement the operation of generating the global link information of the clock reset circuit according to the configuration information corresponding to each module, including:

Generate link information based on a basic clock reset unit corresponding to each module according to configuration information corresponding to each module, wherein the link information includes link information between a port of each module and a submodule within the module and link information between submodules within the module;

According to the link information corresponding to each module, determining one or at least two groups of modules having a link path;

The link information of one or at least two groups of modules having a link path is processed to obtain global link information based on a basic clock reset unit.

In an exemplary embodiment, the processor 201 calls the computer program in the memory 202 to implement the operation of determining one or at least two groups of modules having a link path according to the link information corresponding to each module, including:

Obtain the name information of the signal transmitted by the port in the link information corresponding to each module;

Query whether there is a port transmitting a signal with the same name among the ports of the clock reset circuit;

After finding a port that transmits a signal with the same name, a target module corresponding to the port is determined, and the target module is regarded as a group of modules that have a link path.

In an exemplary embodiment, after the processor 201 calls the computer program in the memory 202 to implement the operation of generating a block diagram file of the clock reset circuit according to the global link information, the processor 201 calls the computer program in the memory 202 to further implement the following operations, including:

Obtaining a checking strategy for a clock reset circuit;

According to the detection strategy, the design information described in the block diagram file is checked.

In an exemplary embodiment, after the processor 201 calls the computer program in the memory 202 to implement the operation of generating a block diagram file of the clock reset circuit according to the global link information, the processor 201 calls the computer program in the memory 202 to further implement the following operations, including:

Obtain a debugging strategy for a clock reset circuit;

According to the debugging strategy, the design information described in the block diagram file is modified.

The device provided in the embodiment of the present application obtains the design file of the clock reset circuit, obtains the configuration information of the ports and sub-modules in each module in the clock reset circuit from the design file according to the pre-set basic functional units, generates a global link table of the clock reset circuit according to the configuration information corresponding to each module, and generates a block diagram file of the clock reset circuit according to the global link table, thereby achieving the purpose of automatically generating a clock reset block diagram and overcoming the problem of long time required for manual block diagram drawing in related technologies.

Fig. 3 is a schematic diagram of a computer storage medium provided in an embodiment of the present application. The computer readable storage medium shown in Fig. 3 stores one or more programs, and the one or more programs can be executed by one or more processors to implement any of the methods described above.

The computer storage medium provided in the embodiment of the present application obtains the design file of the clock reset circuit, obtains the configuration information of the ports and sub-modules in each module in the clock reset circuit from the design file according to the pre-set basic functional units, generates a global link table of the clock reset circuit according to the configuration information corresponding to each module, and generates a block diagram file of the clock reset circuit according to the global link table, thereby achieving the purpose of automatically generating a clock reset block diagram and overcoming the problem of long time required for manual block diagram drawing in related technologies.

It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules/units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those of ordinary skill in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

Claims (9)

1. A method for managing a clock reset circuit, comprising: Obtain the design file of the clock reset circuit; According to the preset basic functional units, obtaining configuration information of ports and submodules in each module of the clock reset circuit from the design file; Generate global link information of the clock reset circuit according to the configuration information corresponding to each module, wherein the global link information is description information of link relationships of modules in the clock reset circuit using the basic functional units; Generate a block diagram file of the clock reset circuit according to the global link information; The step of generating the global link information of the clock reset circuit according to the configuration information corresponding to each module includes: Generate link information based on a basic clock reset unit corresponding to each module according to configuration information corresponding to each module, wherein the link information includes link information between a port of each module and a submodule within the module and link information between submodules within the module; According to the link information corresponding to each module, determining one or at least two groups of modules having a link path; The link information of one or at least two groups of modules having a link path is processed to obtain global link information based on a basic clock reset unit. 2. The method according to claim 1, characterized in that the step of determining one or at least two groups of modules having a link path according to the link information corresponding to each module comprises: Obtain the name information of the signal transmitted by the port in the link information corresponding to each module; Query whether there is a port transmitting a signal with the same name among the ports of the clock reset circuit; After finding a port that transmits a signal with the same name, a target module corresponding to the port is determined, and the target module is regarded as a group of modules that have a link path. 3. The method according to claim 1, characterized in that after generating the block diagram file of the clock reset circuit according to the global link information, the method further comprises: Obtaining a checking strategy for a clock reset circuit; The design information described in the block diagram file is checked according to the checking strategy. 4. The method according to claim 1, characterized in that after generating the block diagram file of the clock reset circuit according to the global link information, the method further comprises: Obtain a debugging strategy for the clock reset circuit; According to the debugging strategy, the design information described in the block diagram file is modified. 5. A management device for a clock reset circuit, comprising a processor and a memory, wherein the memory stores a computer program, and the processor calls the computer program in the memory to implement the following operations, including: Obtain the design file of the clock reset circuit; According to the preset basic functional units, obtaining configuration information of ports and submodules in each module of the clock reset circuit from the design file; Generate global link information of the clock reset circuit according to the configuration information corresponding to each module, wherein the global link information is description information of link relationships of modules in the clock reset circuit using the basic functional units; Generate a block diagram file of the clock reset circuit according to the global link information; The processor calls the computer program in the memory to implement the operation of generating the global link information of the clock reset circuit according to the configuration information corresponding to each module, including: Generate link information based on a basic clock reset unit corresponding to each module according to configuration information corresponding to each module, wherein the link information includes link information between a port of each module and a submodule within the module and link information between submodules within the module; According to the link information corresponding to each module, determining one or at least two groups of modules having a link path; The link information of one or at least two groups of modules having a link path is processed to obtain global link information based on a basic clock reset unit. 6. The device according to claim 5, wherein the processor calls the computer program in the memory to implement the operation of determining one or at least two groups of modules having a link path according to the link information corresponding to each module, comprising: Obtain the name information of the signal transmitted by the port in the link information corresponding to each module; Query whether there is a port transmitting a signal with the same name among the ports of the clock reset circuit; After finding a port that transmits a signal with the same name, a target module corresponding to the port is determined, and the target module is regarded as a group of modules that have a link path. 7. The device according to claim 5, characterized in that after the processor calls the computer program in the memory to implement the operation of generating the block diagram file of the clock reset circuit according to the global link information, the processor calls the computer program in the memory to further implement the following operations, including: Obtaining a checking strategy for a clock reset circuit; The design information described in the block diagram file is checked according to the checking strategy. 8. The device according to claim 5, characterized in that after the processor calls the computer program in the memory to implement the operation of generating the block diagram file of the clock reset circuit according to the global link information, the processor calls the computer program in the memory to further implement the following operations, including: Obtain a debugging strategy for the clock reset circuit; According to the debugging strategy, the design information described in the block diagram file is modified. 9. A computer storage medium, wherein the computer readable storage medium stores one or more programs, wherein the one or more programs can be executed by one or more processors to implement the method according to any one of claims 1 to 4.