CN112510036B - A kind of IGBT device and intelligent power module - Google Patents

Abstract

The application discloses an IGBT device and an intelligent power module. The IGBT device includes: a substrate, a first IGBT cell, a second IGBT cell and a first interlayer insulating layer, the first IGBT cell and the second IGBT cell are sequentially stacked on the substrate, and the first The interlayer insulation layer is used for isolation, wherein the first IGBT cell and the second IGBT cell share the emitter, the collector and the gate electrode. In this way, the withstand voltage performance and current handling capability of the IGBT device can be improved, the on-resistance can be reduced, and the power consumption of the IGBT device can be reduced.

Description

A kind of IGBT device and intelligent power module

technical field

The present application relates to the technical field of semiconductors, in particular to an IGBT device and an intelligent power module.

Background technique

Insulated Gate Bipolar Transistor (IGBT) is a composite fully-controlled voltage-driven power semiconductor device composed of a bipolar transistor (BJT) and an insulated gate field effect transistor (MOSFET), and has a MOSFET device Due to the advantages of high input impedance and low turn-on voltage drop of power transistors, IGBTs are currently widely used in various fields as a new type of power electronic device due to the advantages of small driving power and low saturation voltage.

IGBTs can generally be divided into lateral IGBTs and vertical IGBTs. The IGBT based on the SOI process usually adopts a lateral structure (SOI-LIGBT). With the development of semiconductor technology, SOI-LIGBT and its drive control circuit can be integrated together, and become an important research direction of current intelligent power module. Improving the performance of SOI-LIGBT has also become one of the focuses of research.

The inventors of the present application have found in the long-term research and development process that the current SOI-LIGBT has insufficient withstand voltage performance and current handling capability.

Contents of the invention

The technical problem mainly solved by this application is how to improve the withstand voltage performance and current handling capability of the IGBT device, and then reduce the power consumption of the IGBT device.

In order to solve the above technical problems, a technical solution adopted by the present application is to provide an IGBT device. The IGBT device includes: a substrate, a first IGBT cell, a second IGBT cell and a first interlayer insulating layer, the first IGBT cell and the second IGBT cell are sequentially stacked on the substrate, and the first The interlayer insulation layer is used for isolation, wherein the first IGBT cell and the second IGBT cell share the emitter, the collector and the gate electrode.

In order to solve the above technical problems, another technical solution adopted by the present application is to provide an intelligent power module. The intelligent power module is integrated with an IGBT device and its driving control circuit, and the IGBT device is the above-mentioned IGBT device.

The beneficial effects of the embodiments of the present application are: the IGBT device of the present application includes: a substrate, a first IGBT cell, a second IGBT cell and a first interlayer insulating layer, and the first IGBT cell and the second IGBT cell are stacked in sequence It is arranged on the substrate and isolated by the first interlayer insulating layer, wherein the first IGBT cell and the second IGBT cell share the emitter, the collector and the gate electrode. The IGBT device of the embodiment of the present application is provided with two IGBT cells, and the two IGBT cells share the emitter, collector and gate electrode, that is, the two IGBT cells are arranged in parallel, so that two IGBT cells are formed when the IGBT device is turned on. Conductive channels arranged in parallel, therefore, compared with existing IGBT devices, the IGBT device of the embodiment of the present application has a wider conductive channel when it is turned on; at the same time, the first IGBT cell is stacked against the second IGBT cell layer setting, there is a field plate effect between the two, which can improve the withstand voltage capability of the second IGBT cell, and the second IGBT cell has a field plate effect on the first IGBT cell, which can improve the withstand voltage of the first IGBT cell ability. Therefore, the embodiment of the present application can increase the withstand voltage and current density of the IGBT device, reduce the on-resistance, and thus reduce the power consumption of the IGBT device.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the accompanying drawings required in the embodiments. Obviously, the accompanying drawings in the following description are only some of the present application. Embodiments, for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without any creative effort.

Fig. 1 is the structural representation of an embodiment of the IGBT device of the present application;

Fig. 2 is the structural representation of an embodiment of the IGBT device of the present application;

Fig. 3 is the structural representation of an embodiment of the IGBT device of the present application;

Fig. 4 is the structural representation of an embodiment of the IGBT device of the present application;

Fig. 5 is a schematic structural diagram of an embodiment of an intelligent power module of the present application.

Detailed ways

The application will be described in further detail below in conjunction with the accompanying drawings and embodiments. In particular, the following examples are only used to illustrate the present application, but not to limit the scope of the present application. Likewise, the following embodiments are only some of the embodiments of the present application but not all of them, and all other embodiments obtained by those skilled in the art without creative efforts fall within the protection scope of the present application.

The present application first proposes an IGBT device, as shown in FIG. 1 , which is a schematic structural diagram of an embodiment of the IGBT device of the present application. The IGBT device 10 of this embodiment includes: a substrate 20, a first IGBT cell 30, a second IGBT cell 40, and a first interlayer insulating layer 50, and the first IGBT cell 30 and the second IGBT cell 40 are stacked in sequence On the substrate 20, the substrate 20 is used to support the first IGBT cell 30 and the second IGBT cell 40; and the first IGBT cell 30 and the second IGBT cell 40 are isolated by the first interlayer insulating layer 50 , wherein the first IGBT cell 30 and the second IGBT cell 40 are respectively in contact with the emitter 60, the collector 70 and the gate electrode 80, that is, the first IGBT cell 30 and the second IGBT cell 40 share the emitter 60, the collector electrode 70 and gate electrode 80 .

Wherein, the substrate 20 of this embodiment may be a direct-copper-bonded substrate (Direct-Copper-Bonded, DCB) or an insulated metal substrate (Insulated-Metal-Substrate, IMS), etc.; the first interlayer insulating layer 50 may be is an oxide layer, for example, when the IGBT device is made of a silicon wafer, the first interlayer insulating layer 50 may be a SiO ₂ layer.

When the IGBT device 10 is turned on, the first IGBT cell 30 forms a first conductive channel, and the second IGBT cell 40 forms a second conductive channel.

Different from the prior art, the IGBT device 10 of this embodiment is provided with a first IGBT cell 30 and a second IGBT cell 40, and the first IGBT cell 30 and the second IGBT cell 40 share the emitter 60 and the collector 70 And the gate electrode 80, that is, the first IGBT cell 30 and the second IGBT cell 40 are arranged in parallel, so that when the IGBT device 10 is turned on, two conductive channels arranged in parallel are formed. Therefore, compared with the existing IGBT device, The IGBT device 10 of the present embodiment has a wider conductive channel when it is turned on; meanwhile, the first IGBT cell 30 is stacked with the second IGBT cell 40, and there is a field plate effect between the two, which can improve the second IGBT cell 40. The withstand voltage capability of the IGBT cell 40 , the second IGBT cell 40 has a field plate effect on the first IGBT cell 30 , which can improve the withstand voltage capability of the first IGBT cell. Therefore, this embodiment can increase the withstand voltage and current density of the IGBT device 10 , reduce the on-resistance, and thus reduce the power consumption of the IGBT device 10 .

Optionally, as shown in FIG. 1 , the IGBT device 10 of this embodiment further includes: a gate insulating layer 90, the gate insulating layer 90 is arranged on the same layer as the second IGBT cell 40, and the gate electrode 80 is embedded in the gate insulating layer 90 , that is, the gate electrode 80 is surrounded by a gate insulating layer 90 .

It can be seen from the above analysis that the second IGBT cell 40 is stacked on the side of the first IGBT cell 30 facing away from the substrate 20, therefore, the gate insulating layer 90 of this embodiment is in the same layer as the second IGBT cell 40 Setting, not only can reduce the thickness of the IGBT device 10 , but also can ensure that the first IGBT cell 30 and the second IGBT cell 40 share the gate electrode 80 disposed in the gate insulating layer 90 .

The gate electrode 80 can be led out of the IGBT device 10 through wires; in other embodiments, the gate electrode can also be arranged on the side of the second IGBT cell away from the first IGBT cell, so as to facilitate the lead out of the gate electrode.

The gate insulating layer 90 and the first interlayer insulating layer 50 of this embodiment are mutually independent semiconductor structure layers; the process and material of the gate insulating layer 90 are the same as the first interlayer insulating layer 50, and the gate insulating layer 90 In contact with the first interlayer insulating layer 50 .

In another embodiment, as shown in FIG. 2 , the difference between the IGBT device 10 of this embodiment and the IGBT device 10 of the embodiment of FIG. 1 is that the gate insulating layer 210 and the first interlayer insulating layer 220 of this embodiment are integrated , both are formed by the same process.

Compared with the embodiment in FIG. 1 , the gate insulating layer 210 and the first interlayer insulating layer 220 are integrally provided in this embodiment, which can simplify the process and save costs.

Continuing to refer to FIG. 1 , optionally, the IGBT device 10 of this embodiment further includes: a second interlayer insulating layer 110 , and the second interlayer insulating layer 110 is disposed between the substrate 20 and the first IGBT cell 30 . The second interlayer insulating layer 110 is used to isolate the substrate 20 from the semiconductor structures on the substrate 20 .

The second interlayer insulating layer 110 in this embodiment may be a buried oxide layer. In this embodiment, the buried oxide layer may be formed by a silicon-on-insulator (SOI) process.

In an application scenario, in the SOI process, high-energy, large-dose oxygen can be implanted into silicon to form a buried oxide layer using oxygen injection isolation technology; the buried oxide layer divides the original silicon wafer into two parts, and the thin silicon wafer on the upper part It is used to form semiconductor structures such as the first IGBT cell 30 and the second IGBT cell 40 of this embodiment, and the lower part of the silicon wafer is used to form the substrate 20 of this embodiment.

In another application scenario, in the SOI process, two silicon wafers grown with oxide layers can be bonded together, and the two oxide layers are pasted together by bonding to form a buried oxide layer, and the upper silicon wafer is used to form The semiconductor structures such as the first IGBT cell 30 and the second IGBT cell 40 in this embodiment, and the underlying silicon wafer are used to form the substrate 20 in this embodiment.

Of course, in other application scenarios, other SOI processes may also be used to form the buried oxide layer of this embodiment, such as smart lift-off technology.

In this embodiment, the buried oxide layer is formed by the SOI process, which can improve the latch-up effect of the IGBT device 10, reduce the parasitic effect of the IGBT device 10, and do not need to make a well, which can simplify the process and reduce the size of the IGBT device 10, which is beneficial to the IGBT device. 10 and the miniaturization of intelligent power modules.

When the IGBT device 10 of this embodiment is made of a silicon wafer, the buried oxide layer may be a SiO ₂ layer.

Optionally, as shown in FIG. 1, the first IGBT cell 30 of this embodiment includes: a first drift region 301, a first body region 302, and a first emitter region 303; wherein, the first body region 302 and the first One side of the drift region 301 is in contact; the first emitter region 303 is in contact with the first body region 302 , and the first emitter region 303 is isolated from the first drift region 301 by the first body region 302 .

Wherein, the first body region 302 may be in direct contact with the first drift region 301 or indirectly through a conductive layer; the first emitter region 303 may be in direct contact with the first body region 302 or indirectly through a conductive layer.

The first body region 302 in this embodiment is arranged in an L shape, and both inner sides of the L-shaped first body region 302 are in contact with the first emission region 303; the L-shaped first body region 302 can isolate the first emission region 303 and the second interlayer insulating layer 110; this structure can prevent the generation of parasitic channels on the back of the first body region 302.

Further, the first drift region 301 of this embodiment further extends to between the first body region 302 and the second interlayer insulating layer 110, that is, both outer sides of the L-shaped first body region 302 are connected to the first drift region. region 301; this structure can further improve the parasitic channel problem on the back of the first body region 302.

In other embodiments, to reduce the thickness of the first IGBT cell, the first emitter region may be in contact with the second interlayer insulating layer and/or the first body region may be in contact with the first drift region.

Further, as shown in FIG. 1 , the first IGBT cell 30 of this embodiment further includes: a first buffer zone 304 and a first collector region 305; One side is in contact; the first collector region 305 is in contact with the first buffer region 304 , and the first buffer region 304 isolates the first collector region 305 from the first drift region 301 .

Among them, the first buffer region 304 may be in direct contact with the first drift region 301 or indirectly through a conductive layer; the first collector region 305 may be in direct contact with the first buffer region 304 or indirectly through a conductive layer.

In this embodiment, the first body region 302 and the first emission region 303 are arranged on one side of the first drift region 301, and are arranged on the same layer as the first drift region 301; the first buffer region 304 and the first collector region 305 are arranged On the other side of the first drift region 301 and in the same layer as the first drift region 301 ; this structure can reduce the thickness of the first IGBT cell 30 .

Further, the first buffer zone 304 in this embodiment is arranged in an L shape, and the first drift region 301 further extends between the first buffer zone 304 and the second interlayer insulating layer 110, that is, an L-shaped first buffer zone Both outer sides of 304 are in contact with the first drift region 301, and both inner sides of the L-shaped first buffer zone 304 are in contact with the first collector region 305; this structure can improve the first buffer zone 304 Parasitic channel issues on the back.

In other embodiments, in order to reduce the thickness of the first IGBT cell, the first buffer zone may be in contact with the second interlayer insulating layer.

In this embodiment, the first drift region 301 has the first doping type, the first emitter region 303 has the first doping type, and the doping concentration of the first emitter region 303 is greater than the doping concentration of the first drift region 301, the second The integral region 302 has a second doping type, and the first doping type is different from the second doping type; further, the first buffer zone 304 in this embodiment has the first doping type, and the first collector region 305 has a second doping type.

Specifically, as shown in FIG. 1 , the first doping type of this embodiment is N-type doping, and the second doping type is P-type doping, that is, the first IGBT cell 30 is composed of N-type doping drift region, It consists of N-type doped emitter region, N-type doped buffer region, P-type doped body region and P-type doped collector region. The first IGBT cell 30 in this embodiment has an NPN structure, and when the first IGBT cell 30 is turned on, an N channel is formed.

Further, this embodiment does not limit the doping type of the substrate 20 , and the substrate 20 may be N-type doped or P-type doped.

Specifically, when the first IGBT cell 30 is turned on, the minority carriers injected by the emitter 60 are holes, and the minority carriers injected by the collector 70 are electrons; when the voltage applied to the gate electrode 80 is greater than the threshold voltage , the emitter 60 injects high-concentration electrons into the N-type doped drift region through the N-type doped emitter region and the P-type doped body region, and through the N-type doped buffer region and the P-type doped collector region, thereby forming electrons At the same time, the collector 70 injects high-concentration holes into the N-type doped drift region through the P-type doped collector region and N-type doped buffer zone, and recombines with the high-concentration electrons in the N-type doped drift region to form hole current. The sum of electron current and hole current constitutes the saturation current capability of the first IGBT cell 30 .

In another embodiment, the first doping type is P-type doping, and the second doping type is N-type doping, that is, the first IGBT cell is composed of a P-type doping drift region and a P-type doping emitter region. , a PNP structure composed of a P-type doped buffer, an N-type doped body region, and an N-type doped collector region. When the first IGBT cell is turned on, a P channel is formed; specifically, when the first IGBT cell is turned on, the minority carriers injected into the emitter are electrons, and the minority carriers injected into the collector are holes ; When the voltage applied on the gate electrode is greater than the threshold voltage, the emitter injects high-concentration holes into the P-type doped drift region through the P-type doped emitter region and the N-type doped body region, and passes through the P-type doped buffer, The N-type doped collector area forms holes; at the same time, the collector injects high-concentration electrons into the P-type doped drift region through the N-type doped collector area and the P-type doped buffer zone, and is mixed with the P-type doped The high-concentration holes in the drift region recombine to form a hole current. The sum of electron current and hole current constitutes the saturation current capability of the first IGBT cell.

Optionally, as shown in FIG. 1, the first IGBT cell 30 of this embodiment further includes a third body region 306, the third body region 306 is in contact with the first body region 302 and the first emitter region 303, and passes through the first body region 302 and the first emitter region 303. The body region 302 is isolated from the first drift region 301 , the doping type of the third body region 306 is the same as that of the first body region 302 , and the doping concentration of the third body region 306 is greater than that of the first body region 302 .

Wherein, the third body region 306 may be in direct contact with the first body region 302 and the first emitter region 303 or indirectly through a conductive layer.

The first IGBT cell 30 of this embodiment can provide a minority carrier extraction channel when the first IGBT cell 30 is turned off by setting the third body region 306 , so the turn-off speed of the first IGBT cell 30 can be accelerated.

In another embodiment, as shown in FIG. 3, the difference between the IGBT device 10 of this embodiment and the IGBT device 10 of the embodiment of FIG. 1 at least includes: the first IGBT cell 30 of this embodiment further includes: a body region 330, The region 330 is in contact with the first buffer region 304 , the first collector region 305 and the first interlayer insulating layer 50 respectively.

Compared with the embodiment in FIG. 1, the first IGBT cell 30 of this embodiment can provide a minority carrier extraction channel when the first IGBT cell 30 is turned off by setting the body region 330, so that the first IGBT cell 30 can be accelerated. shutdown speed.

Continuing to refer to FIG. 1, optionally, as shown in FIG. 1, the second IGBT cell 40 of this embodiment includes: a second drift region 401, a second body region 402, and a second emitter region 403; wherein, the second body The region 402 is in contact with one side of the second drift region 401 ; the second emitter region 403 is in contact with the second body region 402 and is isolated from the second drift region 401 by the second body region 402 .

Wherein, the second body region 402 may be in direct contact with the second drift region 401 or indirectly through a conductive layer; the second emitter region 403 may be in direct contact with the second body region 402 or indirectly through a conductive layer.

The second body region 402 of this embodiment is arranged in an L shape, and the inner side of the L-shaped second body region 402 is in contact with the second emission region 403; the L-shaped second body region 402 can isolate the second emission region 403 from the The second drift region 401 ; this structure can prevent parasitic channels from being generated on the back of the second body region 402 .

Furthermore, the second drift region 401 of this embodiment further extends to between the second body region 402 and the first interlayer insulating layer 50, that is, the two outer sides of the L-shaped second body region 402 are connected to the second drift region. The contact of the region 401 can further improve the parasitic channel problem at the back of the second body region 402 .

In other embodiments, to reduce the thickness of the second IGBT cell, the second emitter region may be in contact with the first interlayer insulating layer and/or the second body region may be in contact with the second drift region.

Optionally, as shown in FIG. 1 , the orthographic projection of the first body region 302 on the substrate 20 in this embodiment is farther away from the second drift region 401 than the orthographic projection of the second body region 402 on the substrate 20 The gate electrode 80 is disposed adjacent to the surface of the first body region 302 facing away from the substrate 20 , and adjacent to the surface of the second body region 402 facing away from the second drift region 401 .

It can be seen from the above analysis that in order to reduce the thickness of the IGBT device 10 and ensure that the first IGBT cell 30 and the second IGBT cell 40 share the gate electrode 80, the gate insulating layer 90 is provided in the same layer as the second IGBT cell 40, so In this embodiment, the first body region 302 and the second body region 402 are staggered so that the electrical performance of the first IGBT cell 30 is similar to that of the second IGBT cell 40 .

Further, as shown in FIG. 1 , the second IGBT cell 40 of this embodiment further includes: a second buffer zone 404 and a second collector region 405, wherein the second buffer zone 404 and the second drift region 401 are One side is in contact; the second collector region 405 is in contact with the second buffer region 404 and is isolated from the second drift region 401 by the second buffer region 404 .

Wherein, the second buffer region 404 is in direct contact with the second drift region 401 or indirectly through a conductive layer; the second collector region 405 is in direct contact with the second buffer region 404 or indirectly through a conductive layer.

In this embodiment, the second drift region 401 has the first doping type, the second emission region 403 has the first doping type, and the doping concentration of the second emission region 403 is greater than the doping concentration of the second drift region 401, the second The second body region 402 has the second doping type; further, the second buffer region 404 in this embodiment has the first doping type, and the second collector region 405 has the second doping type.

Specifically, as shown in FIG. 1, the second IGBT cell 40 of this embodiment consists of an N-type doped drift region, an N-type doped emitter region, an N-type doped buffer region, a P-type doped body region, a P-type The composition of the doped collector region, that is, the second IGBT cell 40 of this embodiment is an NPN structure, and an N channel is formed when the second IGBT cell 40 is turned on.

Specifically, when the second IGBT cell 40 is turned on, the minority carriers injected by the emitter 60 are holes, and the minority carriers injected by the collector 70 are electrons; when the voltage applied to the gate electrode 80 is greater than the threshold voltage , the emitter 60 injects high-concentration electrons into the N-type doped drift region through the N-type doped emitter region and the P-type doped body region, and through the N-type doped buffer region and the P-type doped collector region, thereby forming electrons At the same time, the collector 70 injects high-concentration holes into the N-type doped drift region through the P-type doped collector region and N-type doped buffer zone, and recombines with the high-concentration electrons in the N-type doped drift region to form hole current. The sum of the electron current and the hole current constitutes the saturation current capability of the second IGBT cell 40 .

In another embodiment, the first doping type is P-type doping, and the second doping type is N-type doping, that is, the second IGBT cell is composed of a P-type doping drift region and a P-type doping emitter region. , a PNP structure composed of a P-type doped buffer, an N-type doped body region, and an N-type doped collector region. When the first IGBT cell is turned on, a P channel is formed; specifically, when the second IGBT cell is turned on, the minority carriers injected into the emitter are electrons, and the minority carriers injected into the collector are holes ; When the voltage applied on the gate electrode is greater than the threshold voltage, the emitter injects high-concentration holes into the P-type doped drift region through the P-type doped emitter region and the N-type doped body region, and passes through the P-type doped buffer, The N-type doped collector area forms holes; at the same time, the collector injects high-concentration electrons into the P-type doped drift region through the N-type doped collector area and the P-type doped buffer zone, and is mixed with the P-type doped The high-concentration holes in the drift region recombine to form a hole current. The sum of electron current and hole current constitutes the saturation current capability of the second IGBT cell.

The doping type of the second IGBT cell 40 in this embodiment is the same as that of the first IGBT cell 30 , so that the two can share the emitter 60 , the collector 70 and the gate electrode 80 .

In this embodiment, the second body region 402 and the second emitter region 403 are arranged on one side of the second drift region 401, while the second buffer region 404 and the second collector region 405 are arranged on the other side of the second drift region 401. side, and the same layer as the second drift region 401 can reduce the thickness of the second IGBT cell 40 .

In other embodiments, the second buffer region can also extend to between the second collector region and the second drift region and/or the second drift region can also extend to between the second buffer region and the second interlayer insulating layer .

In this embodiment, the first emission region 303 and the second emission region 403 are arranged on the same side, so that the first IGBT cell 30 and the second IGBT cell 40 share the emitter 60; the first collector region 305 and the second collector region 405 are arranged on the same side, so that the first IGBT cell 30 and the second IGBT cell 40 share the collector 70 .

The second drift region 401 of the second IGBT cell 40 in this embodiment forms a field plate effect on the first drift region 301 of the first IGBT cell 30, and the first IGBT cell can be improved by adjusting the electric field distribution of the first drift region 301. The withstand voltage capability of the cell 30; similarly, the first drift region 301 of the first IGBT cell 30 forms a field plate effect on the second drift region 401 of the second IGBT cell 40, and the electric field distribution of the second drift region 401 can be adjusted The withstand voltage capability of the second IGBT cell 40 is improved.

Further, as shown in FIG. 1 , the orthographic projection of the first collector region 305 on the substrate 20 in this embodiment is farther away from the second drift region than the orthographic projection of the second collector region 405 on the substrate 20 The direction of 401 is staggered. This structure can facilitate the arrangement of the collector electrode 70 and the second IGBT unit cell 40 on the same layer, and can reduce the thickness of the IGBT device 10 .

Optionally, as shown in FIG. 1, the second IGBT cell 40 of this embodiment further includes a fourth body region 406, the fourth body region 406 is in contact with the second body region 402 and the second emitter region 403, and passes through the fourth body region 406 The second body region 402 is isolated from the second drift region 401 , the doping type of the fourth body region 406 is the same as that of the second body region 402 , and the doping concentration of the fourth body region 406 is greater than that of the second body region 402 .

Wherein, the fourth body region 406 is in direct contact with the second body region 402 and the second emitter region 403 or indirectly through a conductive layer.

The second IGBT cell 40 of this embodiment can provide a minority carrier extraction channel when the second IGBT cell 40 is turned off by setting the fourth body region 406 , thus speeding up the turn-off speed of the second IGBT cell 40 .

In another embodiment, as shown in FIG. 3, the difference between the IGBT device 10 of this embodiment and the IGBT device 10 of the embodiment of FIG. 1 further includes: the second IGBT cell 40 of this embodiment further includes: a body region 440, a body The region 440 is in contact with the second buffer region 404 , the second collector region 405 and the first interlayer insulating layer 50 respectively.

Compared with the embodiment in FIG. 1, the second IGBT cell 40 of this embodiment can provide a minority carrier extraction channel when the second IGBT cell 40 is turned off by setting the body region 440, so that the second IGBT cell 40 can be accelerated. shutdown speed.

Optionally, as shown in FIG. 1 , the emitter 60 of this embodiment includes a first sub-electrode 61, the first sub-electrode 61 is disposed on the side of the gate electrode 80 away from the first drift region 301, and is connected to the first emitter region 303 away from the substrate 20 side surface contact; emitter 60 further includes a second sub-electrode 62, the second sub-electrode 62 is connected to the first sub-electrode 61, arranged on the side of the gate electrode 80 away from the substrate 20, and with The second emitter region 403 is in surface contact with a side away from the substrate 20 .

Wherein, the first sub-electrode 61 is in direct contact with the first emitter region 303 or indirectly through a conductive layer; the second sub-electrode 62 is in direct contact with the second emitter region 403 or indirectly through a conductive layer.

In this embodiment, the first sub-electrode 61 is arranged on the same layer as the second IGBT cell 40 to facilitate contact with the first emission region 303 of the first IGBT cell 30; the second sub-electrode 62 is arranged on the second IGBT cell 40 , so as to be in contact with the second emitter region 403 of the second IGBT cell 40 and to lead out the emitter 60 .

Furthermore, the first sub-electrode 61 is further in contact with the surface of the third body region 306 facing away from the substrate 20 , and the second sub-electrode 62 is further in contact with the surface of the fourth body region 406 facing away from the substrate 20 .

Optionally, as shown in FIG. 1 , the first sub-electrode 61 and the second sub-electrode 62 in this embodiment are integrated, which can simplify the process and ensure that the electrical performance of the first IGBT cell 30 is the same as that of the second IGBT cell 40. and the first sub-electrode 61 and the second sub-electrode 62 are connected in an L shape, which can reduce the size of the IGBT device 10 .

In another embodiment, as shown in FIG. 4 , the difference between the IGBT device 10 of this embodiment and the IGBT device 10 of the embodiment of FIG. 1 at least includes: the first sub-electrode 61 of this embodiment can also extend to the third body region 306 A side away from the first emission region 303 and in contact with the third body region 306 .

This structure makes the electrical performance of the first IGBT cell 30 similar to that of the second IGBT cell 40 .

Please continue to refer to FIG. 1 , optionally, the collector electrode 70 of this embodiment is in contact with the surface of the first collector region 305 facing away from the substrate 20 , and is in contact with the side of the second collector region 405 away from the second drift region 401 . side surface contact.

Wherein, the collector electrode 70 is in direct contact with the first collector region 305 and the second collector region 405 or indirectly through a conductive layer.

In this embodiment, the collector electrode 70 and the second IGBT cell 40 are arranged in the same layer, which can reduce the thickness of the IGBT device 10 and facilitate the extraction of the collector electrode 70 .

In another embodiment, as shown in FIG. 4, the difference between the IGBT device 10 of this embodiment and the IGBT device 10 of the embodiment of FIG. One side of the first buffer zone 304 and is in contact with the first collector region 305 and the first buffer zone 304 .

This structure makes the electrical performance of the first IGBT cell 30 similar to that of the second IGBT cell 40 .

Different from the prior art, the IGBT device 10 of this embodiment is provided with two IGBT cells, and the two IGBT cells share the emitter 60, the collector 70 and the gate electrode 80, that is, the two IGBT cells are arranged in parallel, When the IGBT device 10 is turned on, two conductive channels arranged in parallel are formed. Therefore, compared with the existing IGBT device, the IGBT device 10 of this embodiment has a wider conductive channel when it is turned on. Therefore, this embodiment can increase the withstand voltage and current density of the IGBT device 10 , reduce the on-resistance, and thus reduce the power consumption of the IGBT device 10 .

It should be noted that the shape and position of the semiconductor structure of each layer of the IGBT device in the embodiment of the present application and the electrode structure can be appropriately changed according to the specific product design.

The IGBT device in the above embodiments of the present application includes two IGBT cells to form two conductive channels. In other embodiments, the number of IGBT cells in the IGBT device is not limited, and the number of IGBT cells may be more than two.

The present application further proposes an intelligent power module, as shown in FIG. 5 , which is a schematic structural diagram of an embodiment of the intelligent power module of the present application. The intelligent power module of this embodiment includes: an IGBT device 10 and its driving control circuit 51 , and the IGBT device 10 works under the driving control of the driving control circuit 51 . Wherein, the IGBT device 10 is the IGBT device 10 of the above-mentioned embodiment, which will not be repeated here.

Intelligent power module is a semiconductor device composed of high-speed, low-power IGBT, gate drive and corresponding protection circuit. It has the advantages of high current density, low saturation voltage and high voltage resistance of high-power transistors, and field effect transistors The advantages of high input impedance, high switching frequency and low drive power. Moreover, the logic, control, detection and protection circuits are integrated inside the intelligent power module, which is convenient to use, not only reduces the size and development time of the system, but also greatly enhances the reliability of the system; the intelligent power module of this embodiment can be used in household appliances , rail transit, power systems and other fields.

Different from the prior art, the IGBT device of this application includes: a substrate, a first IGBT cell, a second IGBT cell, and a first interlayer insulating layer, and the first IGBT cell and the second IGBT cell are sequentially stacked on the substrate on the bottom, and is isolated by the first interlayer insulating layer, wherein the first IGBT cell and the second IGBT cell share the emitter, the collector and the gate electrode. The IGBT device of the embodiment of the present application is provided with two IGBT cells, and the two IGBT cells use an emitter, a collector, and a gate electrode, that is, the two IGBT cells are arranged in parallel, so that two IGBT cells are formed when the IGBT device is turned on. Conductive channels arranged in parallel, therefore, compared with existing IGBT devices, the IGBT device of the embodiment of the present application has a wider conductive channel when it is turned on; at the same time, the first IGBT cell is stacked against the second IGBT cell layer setting, there is a field plate effect between the two, which can improve the withstand voltage capability of the second IGBT cell, and the second IGBT cell has a field plate effect on the first IGBT cell, which can improve the withstand voltage of the first IGBT cell ability. Therefore, the embodiment of the present application can increase the withstand voltage and current density of the IGBT device, reduce the on-resistance, and thus reduce the power consumption of the IGBT device.

Further, the embodiment of the present application adopts the SOI process to form the IGBT device, which can improve the latch-up effect of the IGBT device, reduce the parasitic effect of the IGBT device, and do not need to make a well, which can simplify the process and reduce the size of the IGBT device, which is beneficial to the IGBT device. and the miniaturization of intelligent power modules.

The above is only the implementation of the application, and does not limit the patent scope of the application. Any equivalent mechanism or equivalent process conversion made by using the specification and drawings of the application, or directly or indirectly used in other related technologies fields, are all included in the scope of patent protection of this application in the same way.

Claims (8)

1. An IGBT device, characterized in that the IGBT device comprises a substrate, a first IGBT cell, a second IGBT cell and a first interlayer insulating layer, and the first IGBT cell and the second The IGBT cells are sequentially stacked on the substrate and separated by the first interlayer insulating layer, wherein the first IGBT cell and the second IGBT cell share the emitter, collector and gate electrode; The IGBT device further includes a gate insulating layer, the gate insulating layer is arranged on the same layer as the second IGBT cell, and the gate electrode is embedded in the gate insulating layer; The first IGBT cell includes: first drift zone; a first bulk region in contact with one side of the first drift region; a first emitter region in contact with the first body region and isolated from the first drift region by the first body region; The second IGBT cell includes: second drift zone; a second body region in contact with one side of the second drift region; a second emitter region in contact with the second body region and isolated from the second drift region by the second body region; Wherein, the orthographic projection of the first body region on the substrate is staggered in a direction away from the second drift region compared with the orthographic projection of the second body region on the substrate, and the gate An electrode is disposed adjacent to a surface of the first body region facing away from the substrate, and is disposed adjacent to a surface of the second body region facing away from the second drift region. 2. The IGBT device according to claim 1, wherein the emitter comprises a first sub-electrode and a second sub-electrode, and the first sub-electrode is disposed at a position where the gate electrode is away from the first drift region and is in contact with the surface of the first emitter region away from the substrate, the second sub-electrode is connected to the first sub-electrode, and is arranged on the side of the gate electrode away from the substrate one side, and is in contact with the surface of the side of the second emission region away from the substrate. 3. The IGBT device according to claim 2, wherein the first sub-electrode and the second sub-electrode are integrally arranged and connected in an L-shape. 4. The IGBT device according to claim 2, wherein the first drift region, the first emitter region, the second drift region and the second emitter region have a first doping type, And the doping concentration of the first emitter region is greater than the doping concentration of the first drift region, the doping concentration of the second emitter region is greater than the doping concentration of the second drift region, and the first body region and the second body region have a second doping type different from the first doping type. 5. The IGBT device according to claim 4, wherein the first IGBT cell further comprises a third body region, the third body region is connected to the first body region and the first emitter region is in contact with, and is isolated from the first drift region by the first body region, the third body region has the second doping type, and the doping concentration of the third body region is greater than that of the first the doping concentration of the body region, the first sub-electrode is further in contact with the surface of the third body region away from the substrate; The second IGBT cell further includes a fourth body region, the fourth body region is in contact with the second body region and the second emitter region, and communicates with the second drift region through the second body region region isolation, the fourth body region has the second doping type, and the doping concentration of the fourth body region is greater than the doping concentration of the second body region, and the second sub-electrode is further connected to the The fourth body region is in surface contact with a side away from the substrate. 6. The IGBT device according to claim 1, characterized in that, the IGBT device further comprises a second interlayer insulating layer, the second interlayer insulating layer is arranged between the first IGBT cell and the substrate bottom, wherein the first drift region further extends to between the first body region and the second interlayer insulating layer, and/or the second drift region further extends to the second body region and the first interlayer insulating layer. 7. The IGBT device according to claim 1, wherein the first IGBT cell further comprises: a first buffer zone in contact with the other side of the first drift region; a first collector region in contact with the first buffer region and isolated from the first drift region by the first buffer region; The second IGBT cell further includes: a second buffer zone in contact with the other side of the second drift region; a second collector region in contact with the second buffer region and isolated from the second drift region by the second buffer region; Wherein, the orthographic projection of the first collector region on the substrate is staggered in a direction away from the second drift region compared with the orthographic projection of the second collector region on the substrate, so The collector electrode is in contact with a surface of the first collector region away from the substrate, and is in contact with a surface of the second collector region away from the second drift region. 8. An intelligent power module, characterized in that the intelligent power module comprises: an IGBT device and a driving control circuit thereof, and the IGBT device is the IGBT device according to any one of claims 1 to 7.

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