CN107785415A - A kind of SOI RC LIGBT devices and preparation method thereof - Google Patents

Abstract

The invention provides a SOI-RC-LIGBT device and its preparation method, comprising an N-type substrate, a buried oxide layer, an N-type drift region, a trench gate structure, a P-type base region, an N ⁺ source region and a P ⁺ contact region, emitter, oxide layer, N-type buffer zone, P-type collector region; there are N-type strips on the surface of the N-type drift region between the P-type base region and the N-type buffer zone, and there are N-type strips in the drift region below the N-type strips P-type buried layer; there is a dielectric groove structure between the right side of the N-type strip and the right side of the P-type buried layer, and the left side of the N-type buffer layer and the left side of the P-type collector region; the N-type strip and the dielectric groove There is an N+ collector region between the structures; the SOI-RC-LIGBT proposed by the present invention can improve the breakdown voltage of the device while eliminating the snapback phenomenon of the IGBT conduction characteristic, reduce the forward conduction voltage drop of the device, and increase the turn-off speed , to reduce the turn-off loss, and at the same time, improve the reverse recovery characteristics of the integrated freewheeling diode.

Description

A kind of SOI-RC-LIGBT device and its preparation method

technical field

The invention belongs to the technical field of power semiconductor devices, and in particular relates to a reverse conduction lateral insulated gate bipolar transistor (RC-LIGBT) device based on SOI (Silicon On Insulator) technology and a preparation method thereof.

Background technique

Semiconductor power devices are the basic electronic components for energy control and conversion in power electronic systems. The continuous development of power electronics technology has opened up a wide range of application fields for semiconductor power devices. MOS-type semiconductor power devices marked by IGBT, VDMOS, and CoolMOS are the mainstream of devices in the field of power electronics today. Among them, the most representative semiconductor power device is IGBT.

IGBT (Insulated Gate Bipolar Transistor, Insulated Gate Bipolar Transistor) is a voltage-controlled MOS/BJT composite device. In terms of structure, the structure of IGBT is very similar to that of VDMOS, except that the N ⁺ substrate of VDMOS is adjusted to P ⁺ substrate, but the conductance modulation effect introduced overcomes the contradiction between the inherent on-resistance and breakdown voltage of VDMOS itself, thus Make IGBT have the main advantages of bipolar power transistor and power MOSFET at the same time: high input impedance, low input driving power, low conduction voltage, large current capacity, fast switching speed, etc. It is precisely because of the unique and irreplaceable performance advantages of IGBT that it has been widely used in many fields since the launch of practical products, such as: new energy technology, advanced transportation tools represented by motor vehicles and high-speed rail, hybrid vehicles, Household appliances and other fields.

As a power device, the IGBT with a vertical structure occupies a large area in an intelligent power integrated circuit, and the process is difficult to be compatible with other devices in the circuit, which affects the overall performance and reliability. And LIGBT (Lateral Insulated Gate Bipolar Transistor, lateral insulated gate bipolar transistor) can effectively solve the above problems. Transient substrate surge current during junction-isolated LIGBT switching, dynamic and static cross effects between devices (including between multiple LIGBTs, between LIGBTs and CMOS, bipolar devices), etc., make it difficult to apply to multiple In a LIGBT monolithically integrated intelligent power integrated circuit. The SOI (Silicon On Insulator) process adopts dielectric isolation, basically no substrate current leakage, which eliminates the problems caused by inter-device parasitic effects and latch-up effects on chip reliability, and effectively reduces the traditional PN junction isolation structure. The chip area is conducive to achieving higher performance, lower power consumption, and faster speed, while helping to reduce costs.

In the power system, the IGBT usually needs to be used with a free wheeling diode (Free Wheeling Diode) to ensure the safety and stability of the system. Therefore, in traditional IGBT modules or single-transistor devices, FWD is usually connected in reverse parallel with it. This solution not only increases the overall production cost, but also the parasitic effect generated by the metal wiring used in the packaging process will affect the overall performance. In order to solve this problem, in 2002, E.Napoli et al proposed an IGBT capable of reverse conduction called RC-IGBT (Reverse Conducting-Insulated Gate Bipolar Transistor), by introducing N ⁺ collector area on the collector side The method realizes the integration of IGBT and diode. The traditional SOI-RC-LIGBT is shown in Figure 1, in which the P-type base region, drift region, N-type buffer layer, and N ⁺ collector region form a parasitic diode structure, and the parasitic diode conducts current in the freewheeling mode. However, the introduction of the N ⁺ collector region has an adverse effect on the forward conduction characteristics. Among them, the channel region, drift region, N-type buffer layer, and N ⁺ collector region form a parasitic VDMOS structure. The electrons injected into the drift region flow out directly from the N ⁺ collector region, resulting in the failure of the collector junction to open, and the conductance modulation effect cannot be formed in the drift region, and the device exhibits VDMOS characteristics. When the electron current increases to a certain value, the collector junction is opened, and the P ⁺ collector region injects holes into the drift region to form a conductance modulation effect. At this time, as the current increases, the forward voltage drop drops rapidly, making the current -The voltage curve presents a negative resistance (Snapback) phenomenon. This will prevent the IGBTs from being fully turned on in parallel applications, causing reliability issues.

Contents of the invention

In view of the shortcomings of the prior art described above, the purpose of the present invention is to suppress the Snapback phenomenon of the traditional SOI-RC-LIGBT as shown in Figure 1, improve the stability of the whole system, and propose a SOI-RC-LIGBT device and its preparation method.

In order to realize the foregoing invention object, the technical scheme of the present invention is as follows:

An SOI-RC-LIGBT device, comprising: an N-type substrate, a buried oxide layer, and an N-type drift region arranged sequentially from bottom to top; one end of the N-type drift region is provided with a gate dielectric layer and a gate electrode. Trench gate structure, the gate electrode is located inside one side of the gate dielectric layer; the other side of the gate dielectric layer inside the N-type drift region is provided with a P-type base region, and the inside of the P-type base region is provided with a N ⁺ source region and P ⁺ contact region, the sides of the P-type base region and the N ⁺ source region are in contact with the side surfaces of the gate dielectric layer; there is an emitter above the N ⁺ source region and the P ⁺ contact region, and the An oxide layer is above the gate dielectric layer and the gate electrode; an N-type buffer zone is provided at the end of the N-type drift region away from the trench gate structure, and a P-type collector region is provided above the inside of the N-type buffer zone; The surface of the N-type drift region between the P-type base region and the N-type buffer zone has an N-type strip, and there is a P-type buried layer in the drift region below the N-type strip; the P-type buried layer is not connected to the P-type base. The region is in contact; the right side of the N-type strip and the right side of the P-type buried layer have a dielectric groove structure between the left side of the N-type buffer layer and the left side of the P-type collector region; the N-type strip There is an N+ collector region between the dielectric groove structure; part of the upper surface of the N+ collector region, and the upper surface of the dielectric groove structure and the P-type collector region are collectors; the depth of the dielectric groove structure is not less than N The depth of the type strip and the P-type collector region; the concentration of the N-type strip and the P-type buried layer is greater than the concentration of the N-type drift region.

The present invention introduces the composite structure formed by P-type buried layer and dielectric groove on the surface of the device, and combines the LDMOS part formed by the MOS structure on the left side of the device, the N-type drift region, the N-type strip and the N ⁺ collector region with the MOS part formed by the left side of the device. structure, N-type drift region, N-type buffer layer and P-type collector region to form the LIGBT part phase separation, and through the Triple RESURF function provided by the P-type buried layer and buried oxide layer, the N-type strip, P-type buried layer and The doping concentration of the N-type drift region can improve the distribution of the electric field on the surface of the device and increase the breakdown voltage of the device. When the device is forward-conducting, the channel is turned on, and when the voltage V _CE between the collector and the emitter is less than the turn-on voltage (~0.7V) of the collector junction corresponding to the P-type collector region and the N-type buffer layer, the electron flow Pass through the channel, N-type drift region, N-type strip and N ⁺ collector region, and flow out from the collector, showing the unipolar conduction mode corresponding to LDMOS. The presence of high-concentration N-type strips greatly reduces the on-resistance of LDMOS, and a large current can be obtained under a certain collector current. When V _CE increases to the open voltage of the collector junction, the P-type collector region begins to inject holes into the N-type drift region, forming a conductance modulation effect, and the LIGBT is turned on, showing the bipolar conduction mode corresponding to the IGBT. Since the P-type buried layer and the dielectric trench structure isolate the LDMOS part from the LIGBT part, a mixed conduction mode of LDMOS and LIGBT is formed. Therefore, this structure can achieve a smooth rise in V _CE during forward conduction and completely eliminate the Snapback phenomenon. . And the anti-parallel diode composed of P-type base region, N-type drift region, N-type strip and N ⁺ collector region realizes the reverse conduction performance of LIGBT.

As a preferred manner, the P-type buried layer is composed of a plurality of regions whose concentration decreases from left to right.

As a preferred manner, the N-type bar is composed of multiple regions whose concentrations increase sequentially from left to right.

As a preferred mode, on the basis of the trench MOS structure composed of the trench gate structure and the P-type base region, N+ source region and P+ contact region, a second gate dielectric layer and a second gate electrode are added. The planar gate structure and the planar MOS structure formed by the planar gate structure, the P-type base region and the second N+ source region form a composite double gate structure composed of the planar gate structure and the trench gate structure.

As a preferred manner, the depth of the dielectric trench structure is greater than the depths of the P-type buried layer and the N-type buffer zone.

The high-concentration N-type strips, P-type buried layer and N-type drift region are all depleted before device breakdown.

The structure of the present invention is not only applicable to bulk silicon (Si), but also can be used for semiconductor materials such as silicon carbide (SiC), gallium arsenide (GaAs) or gallium nitride (GaN); the structure is not limited to SOI technology, and can also be used for bulk silicon and junction isolation technologies.

In order to achieve the above-mentioned purpose of the invention, the present invention also provides a method for preparing the above-mentioned SOI-RC-LIGBT device, which includes the following steps in turn:

Preparation of SOI material, phosphorus implantation and well pushing of N-type buffer layer, etching of trench gate, growth of gate oxide layer, deposition and etching of N+ polysilicon, boron implantation and well pushing of P-type base area, P-type High-energy boron implantation in the buried layer, arsenic implantation and push-well in the surface N-type layer, arsenic implantation in the N+ source region and N+ collector region, boron implantation and push-well in the P+ contact region, etching of rectangular grooves, silicon dioxide Deposition and etching, boron implantation and low temperature annealing of P-type collector area, BPSG deposition and reflow, etching of contact holes, deposition and etching of aluminum layer.

As a preferred mode, the preparation method of the SOI-RC-LIGBT device further includes the following steps:

Step 1: Prepare a silicon-on-insulator material, wherein the thickness of the substrate is 300-500 microns, the doping concentration is 10 ^{14-10 15} /cm ³ , the thickness of the buried oxide layer on the substrate is 0.5-3 microns, SOI The thickness of the layer is 5-20 microns, and the doping of the SOI layer is 5e14cm ^-3 -1e15cm ^-3 ;

The second step: photolithography, ion-implanting N-type impurities in the right area of the silicon wafer surface and annealing to make an N-type buffer layer, the thickness of the formed N-type buffer layer is 2 to 4 microns;

The third step: photolithography, etch the groove on the left side of the silicon wafer surface, and thermally oxidize and grow the gate oxide layer on the silicon wafer surface, and deposit the gate electrode material; photolithography, etch the unnecessary gate electrode material and gate The oxide layer forms the gate electrode;

The fourth step: photolithography, on the left side of the drift region on the surface of the silicon wafer, ion-implant P-type impurities and anneal to make a P-type base region, and the thickness of the formed P-type base region is 2 to 3 microns;

The fifth step: photolithography, in the middle of the drift region on the surface of the silicon wafer, a P-type buried layer is formed by implanting P-type impurities with high-energy ions. The depth of the P-type buried layer from the surface is 0.5-1 micron, the thickness is 0.5-1 micron, and the concentration is 5e15cm ^-3 ～1e16cm ^-3 ;

Step 6: photolithography, by ion implanting N-type impurities in the middle of the drift region on the surface of the silicon wafer and annealing to make N-type stripe regions, the concentration of the formed N-type stripe regions is 5e15cm ^-3 ~ 1e16cm ^-3 ;

The seventh step: photolithography, making N ⁺ source region and N ⁺ collector region by ion implanting N-type impurities on the surface of the silicon wafer;

The eighth step: photolithography, ion-implanting P-type impurities on the surface of the silicon wafer and annealing to make a P-type contact region, the thickness of the formed N-type source region and P-type contact region is about 0.2 to 0.3 microns;

Step 9: photolithography, etching and filling medium to form a dielectric groove, the depth of the formed dielectric groove structure is 1-2 microns, and the width is 0.1-0.5 microns;

Step 10: Photolithography, in the right area of the silicon wafer surface, ion-implant P-type impurities and anneal at low temperature to make a P-type collector region, and the thickness of the formed P-type collector region is 0.3-0.5 microns;

The eleventh step: depositing, photolithography, and etching a dielectric layer to form a dielectric layer;

The twelfth step: Depositing, photolithography, and etching metal to form a metal emitter and a metal collector on the surface of the device; that is, the SOI-RC-LIGBT device is prepared.

Working principle of the present invention and beneficial effect:

Based on the structure of the traditional SOI-RC-LIGBT, the invention introduces a compound structure formed by N-type strips, P-type buried layers and dielectric groove structures on the surface of the N-type drift region of the device. The N-type strip, P-type buried layer, N-type drift region and buried oxide layer form a TripleRESURF structure, which can improve the distribution of the electric field on the surface of the device, increase the breakdown voltage of the device, and improve the N-type strip, P The doping concentration of the N-type buried layer and the N-type drift region. In forward conduction, the present invention introduces a P-type buried layer and a dielectric trench structure on the surface of the device to combine the LDMOS part formed by the left MOS structure, the N-type drift region, and the N ⁺ collector region with the MOS formed by the left side of the device. Structure, N-type drift region, N-type buffer layer and the LIGBT part formed by the P-type collector region are separated. When the device is forward-conducting, the channel is turned on, and when the voltage V _CE between the collector and the emitter is less than the turn-on voltage (~0.7V) of the collector junction corresponding to the P-type collector region and the N-type buffer layer, the electron flow Pass through the channel, N-type drift region, N-type strip and N ⁺ collector region, and flow out from the collector, showing the unipolar conduction mode corresponding to LDMOS. The presence of high-concentration N-type strips greatly reduces the on-resistance of LDMOS, and a large current can be obtained under a certain collector current. When V _CE increases to the open voltage of the collector junction, the P-type collector region begins to inject holes into the N-type drift region, forming a conductance modulation effect, and the LIGBT is turned on, showing the bipolar conduction mode corresponding to the IGBT. Since the P-type buried layer and the dielectric trench structure isolate the LDMOS part from the LIGBT part, a mixed conduction mode of LDMOS and LIGBT is formed. Therefore, this structure can achieve a smooth rise in V _CE during forward conduction and completely eliminate the Snapback phenomenon. . At the same time, due to the existence of high-concentration N-type strips, the component of LDMOS in the entire collector current increases, which reduces the excess carrier injection in the N-type drift region at a certain current, and at the same time can obtain Small forward voltage drop. When the device is turned off, due to the lateral expansion of the depletion layer in the P-type RESURF layer, the depletion layer in the drift region expands quickly, which improves the turn-off speed of the device and reduces the turn-off loss of the device. When on, the LDMOS component in the entire collector current is large, which reduces the excess carrier injection in the N-type drift region under a certain current, further improves the turn-off speed of the device, and reduces the turn-off loss of the device; At the same time, the anti-parallel diode composed of P _body base region, N-type drift region, N-type strip and N ⁺ collector region realizes the reverse conduction performance of LIGBT. When anti-parallel diodes are freewheeling, the existence of the P-type buried layer improves the reverse recovery characteristics of the diodes.

FIG. 5 is a comparison diagram of conduction characteristics between a conventional SOI-RC-LIGBT and the SOI-RC-LIGBT of the present invention. It can be seen from the figure that in terms of forward conduction characteristics, the traditional SOI-RC-LIGBT without N-type buffer layer has a Snapback phenomenon, and the Snapback phenomenon of the traditional SOI-RC-LIGBT with an N-type buffer layer concentration of 5e15cm ^-3 is relatively Seriously, the Snapback phenomenon of the traditional SOI-RC-LIGBT with an N-type buffer layer concentration of 1e16cm ^-3 is even more serious. The SOI-RC-LIGBT proposed by the present invention completely eliminates the Snapback phenomenon under the condition that the concentration of the N-type strip and the P-type buried layer are both 5e15cm ^-3 and the concentration of the N-type buffer layer is 1e16cm ^-3 . At the same time, in terms of reverse conduction characteristics, the conduction characteristics of the SOI-RC-LIGBT body-integrated diode proposed by the present invention are better than those of the traditional SOI-RC-LIGBT body-integrated diode.

Fig. 6 is a comparison diagram of the breakdown characteristics of the traditional SOI-RC-LIGBT and the SOI-RC-LIGBT of the present invention. It can be seen from the figure that the breakdown voltage BV of the traditional SOI-RC-LIGBT without the N-type buffer layer is only 137V, and the BV of the traditional SOI-RC-LIGBT with the N-type buffer layer concentration of 5e15cm ^-3 is 169V, and the N-type The BV of the traditional SOI-RC-LIGBT with a buffer layer concentration of 1e16cm ^-3 reaches 211V. The SOI-RC-LIGBT proposed by the present invention has a concentration of 5e15cm ^-3 in both the N-type strip and the P-type buried layer, and the concentration of the N-type buffer layer is Under the condition of 1e16cm ^-3 , the breakdown voltage BV reaches 273V, and compared with the conventional SOI-RC-LIGBT with the same N-type buffer layer concentration, the increase of BV is about 30%.

Fig. 7 is a comparison chart of the reverse recovery characteristics of the traditional SOI-RC-LIGBT and the integrated diode in the SOI-RC-LIGBT of the present invention. It can be seen from the figure that the reverse recovery characteristic of the SOI-RC-LIGBT diode proposed by the present invention is softer than that of the traditional structure, which avoids the oscillation problem in the reverse recovery process of the traditional structure.

In summary, the SOI-RC-LIGBT proposed by the present invention can improve the breakdown voltage of the device, reduce the forward conduction voltage drop of the device, increase the turn-off speed, and reduce the turn-off speed while eliminating the snapback phenomenon of the IGBT conduction characteristic. break loss. At the same time, the reverse recovery characteristics of the integrated freewheeling diode are improved.

Description of drawings

Figure 1 is a schematic diagram of the structure of a traditional SOI-RC-LIGBT.

Fig. 2 is a schematic structural diagram of the SOI-RC-LIGBT of Example 1 of the present invention.

Fig. 3 is a schematic structural diagram of the SOI-RC-LIGBT of Example 4 of the present invention.

Fig. 4 is a schematic diagram of the preparation process of a SOI-RC-LIGBT proposed by the present invention.

FIG. 5 is a comparison diagram of conduction characteristics between a conventional SOI-RC-LIGBT and the SOI-RC-LIGBT of the present invention.

Fig. 6 is a comparison diagram of the breakdown characteristics of the traditional SOI-RC-LIGBT and the SOI-RC-LIGBT of the present invention.

Fig. 7 is a comparison chart of the reverse recovery characteristics of the traditional SOI-RC-LIGBT and the integrated diode in the SOI-RC-LIGBT of the present invention.

Among them, 1 is the oxide layer, 2 is the N ⁺ source region, 3 is the emitter electrode, 4 is the P ⁺ contact region, 5 is the P-type base region, 6 is the gate electrode, 7 is the gate dielectric layer, 8 is the buried oxide layer, 9 is N-type substrate, 10 is surface oxide layer 2, 11 is P-type collector region, 12 is collector electrode, 13 is N ⁺ collector region, 14 is N-type buffer layer, 15 is N-type drift region, 16 17 is a P-type buried layer, 18 is a dielectric groove structure, 2-1 is a second N ⁺ source region, 6-1 is a second gate electrode, and 7-1 is a second gate dielectric layer.

In Figure 5 to Figure 7, "Conventional SOI-RC-LIGBT" is the traditional SOI-RC-LIGBT, "New SOI-RC-LIGBT" is the SOI-RC-LIGBT of the present invention, and "Nbuffer" is the N-type buffer layer Concentration, "BV" means breakdown voltage.

Detailed ways

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

Example 1

An SOI-RC-LIGBT device, comprising: an N-type substrate 9, a buried oxide layer 8, and an N-type drift region 15 arranged sequentially from bottom to top; one end of the N-type drift region 15 is provided with a gate dielectric layer 7 A trench gate structure composed of a gate electrode 6, the gate electrode 6 is located inside one side of the gate dielectric layer 7; the other side of the gate dielectric layer 7 inside the N-type drift region 15 is provided with a P-type base region 5, An N ⁺ source region 2 and a P ⁺ contact region 4 are arranged above the inside of the P-type base region 5, and the side surfaces of the P-type base region 5 and the N ⁺ source region 2 are in contact with the side surfaces of the gate dielectric layer 7; There is an emitter 3 above the N ⁺ source region 2 and the P ⁺ contact region 4, and an oxide layer 1 is above the gate dielectric layer 7 and the gate electrode 6; the inside of the N-type drift region 15 is far away from one end of the trench gate structure An N-type buffer area 14 is provided, and a P-type collector region 11 is arranged above the inside of the N-type buffer area 14; it is characterized in that: the N-type drift between the P-type base area 5 and the N-type buffer area 14 There is an N-type strip 16 on the surface of the region 15, and there is a P-type buried layer 17 in the drift region below the N-type strip 16; the P-type buried layer 17 is not in contact with the P-type base region 5; the N-type strip 16 There is a dielectric trench structure 18 between the right side and the right side of the P-type buried layer 17, and the left side of the N-type buffer layer 14 and the left side of the P-type collector region 11; the N-type strip 16 and the dielectric trench structure 18 There is an N+ collector region 13 between them; part of the upper surface of the N+ collector region 13, and the upper surfaces of the dielectric groove structure 18 and the P-type collector region 11 are collector electrodes 12; the depth of the dielectric groove structure 18 is not The depth is less than the N-type strip 16 and the P-type collector region 11 ; the concentration of the N-type strip 16 and the P-type buried layer 17 is greater than the concentration of the N-type drift region 15 .

The depth of the dielectric trench structure 18 is greater than the depths of the P-type buried layer 17 and the N-type buffer zone 14 .

Specifically, the thickness of the N-type drift region 15 is 5-20 microns, and the doping is 5e14cm ^- 3-1e15cm ^-3 ; the depth of the P-type buried layer 17 from the surface is 0.5-1 micron, the thickness is 0.5-1 micron, and the concentration 5e15cm ^-3 ~ 1e16cm ^-3 ; the concentration of N-type strips 16 is 5e15cm ^-3 ~ 1e16cm ^-3 ; the distance between the P-type buried layer 17 and the P-type base region 5 is 0.5-2 microns, and the depth of the dielectric groove structure 18 is 1-2 microns, the width is 0.1-0.5 microns, and the junction depth of the P-type collector region 11 is 0.3-0.5 microns.

Example 2

This embodiment is basically the same as Embodiment 1, except that the P-type buried layer 17 is composed of a plurality of regions whose concentrations decrease from left to right.

Example 3

This embodiment is basically the same as Embodiment 1, except that the N-type strip 16 is composed of a plurality of regions whose concentrations increase from left to right.

Example 4

This embodiment is basically the same as Embodiment 1, except that: on the basis of the trench MOS structure composed of the trench gate structure and the P-type base region 5, the N+ source region 2 and the P+ contact region 4, an additional The planar gate structure composed of the second gate dielectric layer 7-1 and the second gate electrode 6-1, and the planar MOS structure formed by the planar gate structure, the P-type base region 5, and the second N+ source region 2-1 , forming a composite double gate structure composed of a planar gate structure and a trench gate structure.

Example 5

The preparation method of the SOI-RC-LIGBT device of embodiment 1-4, comprises the following steps successively:

Preparation of SOI material, phosphorus implantation and well pushing of N-type buffer layer, etching of trench gate, growth of gate oxide layer, deposition and etching of N+ polysilicon, boron implantation and well pushing of P-type base area, P-type High-energy boron implantation in the buried layer, arsenic implantation and push-well in the surface N-type layer, arsenic implantation in the N+ source region and N+ collector region, boron implantation and push-well in the P+ contact region, etching of rectangular grooves, silicon dioxide Deposition and etching, boron implantation and low temperature annealing of P-type collector area, BPSG deposition and reflow, etching of contact holes, deposition and etching of aluminum layer.

Example 6

The preparation method of the described SOI-RC-LIGBT device of embodiment 1-4, comprises the following steps in turn:

Step 1: Prepare a silicon-on-insulator material, wherein the thickness of the substrate is 300-500 microns, the doping concentration is 10 ^{14-10 15} /cm ³ , the thickness of the buried oxide layer on the substrate is 0.5-3 microns, SOI The thickness of the layer is 5-20 microns, and the doping of the SOI layer is 5e14cm ^-3 -1e15cm ^-3 ;

The second step: photolithography, the N-type buffer layer 14 is formed by ion-implanting N-type impurities in the right area of the silicon wafer surface and annealed, and the thickness of the formed N-type buffer layer 14 is 2 to 4 microns;

The third step: photolithography, etch the groove on the left side of the silicon wafer surface, and thermally oxidize and grow the gate oxide layer on the silicon wafer surface, and deposit the gate electrode material; photolithography, etch the unnecessary gate electrode material and gate The oxide layer forms the gate electrode;

The fourth step: photolithography, on the left side of the drift region on the surface of the silicon wafer, ion-implant P-type impurities and anneal to make a P-type base region, and the thickness of the formed P-type base region is 2 to 3 microns;

The fifth step: photolithography, in the middle of the drift region on the surface of the silicon wafer, a P-type buried layer is formed by implanting P-type impurities with high-energy ions. The depth of the P-type buried layer from the surface is 0.5-1 micron, the thickness is 0.5-1 micron, and the concentration is 5e15cm ^-3 ～1e16cm ^-3 ;

Step 6: photolithography, by ion implanting N-type impurities in the middle of the drift region on the surface of the silicon wafer and annealing to make N-type stripe regions, the concentration of the formed N-type stripe regions is 5e15cm ^-3 ~ 1e16cm ^-3 ;

The seventh step: photolithography, making N ⁺ source region and N ⁺ collector region by ion implanting N-type impurities on the surface of the silicon wafer;

The eighth step: photolithography, ion-implanting P-type impurities on the surface of the silicon wafer and annealing to make a P-type contact region, the thickness of the formed N-type source region and P-type contact region is about 0.2 to 0.3 microns;

Step 9: photolithography, etching and filling medium to form a dielectric groove, the depth of the formed dielectric groove structure 18 is 1-2 microns, and the width is 0.1-0.5 microns;

Step 10: Photolithography, in the right area of the silicon wafer surface, ion-implant P-type impurities and anneal at low temperature to make a P-type collector region, and the thickness of the formed P-type collector region is 0.3-0.5 microns;

The eleventh step: depositing, photolithography, and etching a dielectric layer to form a dielectric layer;

The twelfth step: Depositing, photolithography, and etching metal to form a metal emitter and a metal collector on the surface of the device; that is, the SOI-RC-LIGBT device is prepared.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention shall still be covered by the claims of the present invention.

Claims (7)

1. a SOI-RC-LIGBT device, comprising: an N-type substrate (9), a buried oxide layer (8) and an N-type drift region (15) arranged successively from bottom to top; said N-type drift region (15) ) is provided with a trench gate structure consisting of a gate dielectric layer (7) and a gate electrode (6), and the gate electrode (6) is located inside one side of the gate dielectric layer (7); the N-type drift A P-type base region (5) is provided on the other side of the gate dielectric layer (7) inside the region (15), and an N ⁺ source region (2) and a P ⁺ contact region ( 4), the sides of the P-type base region (5) and the N ⁺ source region (2) are in contact with the side surfaces of the gate dielectric layer (7); the N ⁺ source region (2) and the P ⁺ contact region ( 4) There is an emitter (3) on the top, and an oxide layer (1) is above the gate dielectric layer (7) and the gate electrode (6); the inside of the N-type drift region (15) is away from one end of the trench gate structure An N-type buffer zone (14) is provided, and a P-type collector region (11) is arranged above the inside of the N-type buffer zone (14); it is characterized in that: between the P-type base zone (5) and the N-type buffer zone ( The surface of the N-type drift region (15) between 14) has an N-type strip (16), and there is a P-type buried layer (17) in the drift region below the N-type strip (16); the P-type buried layer (17) not in contact with the P-type base region (5); the right side of the N-type strip (16) and the right side of the P-type buried layer (17), and the left side and the N-type buffer layer (14) There is a dielectric groove structure (18) between the left side of the P-type collector region (11); there is an N+ collector region (13) between the N-type strip (16) and the dielectric groove structure (18); the N+ Part of the upper surface of the collector region (13), and the upper surface of the dielectric groove structure (18) and the P-type collector region (11) are collector electrodes (12); the depth of the dielectric groove structure (18) is not less than N The depth of the type strip (16) and the P-type collector region (11); the concentration of the N-type strip (16) and the P-type buried layer (17) is greater than the concentration of the N-type drift region (15). 2 . The SOI-RC-LIGBT device according to claim 1 , characterized in that: the P-type buried layer ( 17 ) is composed of a plurality of regions whose concentrations decrease sequentially from left to right. 3 . 3. The SOI-RC-LIGBT device according to claim 1, characterized in that: the N-type strip (16) is composed of a plurality of regions whose concentrations increase sequentially from left to right. 4. A kind of SOI-RC-LIGBT device according to claim 1, is characterized in that: by described trench gate structure and P-type base region (5), N+ source region (2) and P+ contact region (4) On the basis of the trench MOS structure formed, the planar gate structure consisting of the second gate dielectric layer (7-1) and the second gate electrode (6-1) and the planar gate structure and the The planar MOS structure formed by the P-type base region (5) and the second N+ source region (2-1) forms a composite double-gate structure composed of a planar gate structure and a trench gate structure. 5. A SOI-RC-LIGBT device according to claim 1, characterized in that: the depth of the dielectric trench structure (18) is greater than the depth of the P-type buried layer (17) and the N-type buffer zone (14). 6. according to the preparation method of the SOI-RC-LIGBT device described in any one of claim 1 to 5, it is characterized in that: comprise the following steps successively: Preparation of SOI material, phosphorus implantation and well pushing of N-type buffer layer, etching of trench gate, growth of gate oxide layer, deposition and etching of N+ polysilicon, boron implantation and well pushing of P-type base area, P-type High-energy boron implantation in the buried layer, arsenic implantation and push-well in the surface N-type layer, arsenic implantation in the N+ source region and N+ collector region, boron implantation and push-well in the P+ contact region, etching of rectangular grooves, silicon dioxide Deposition and etching, boron implantation and low temperature annealing of P-type collector area, BPSG deposition and reflow, etching of contact holes, deposition and etching of aluminum layer. 7. according to the preparation method of the SOI-RC-LIGBT device described in any one of claim 1 to 5, it is characterized in that: comprise the steps: Step 1: Prepare a silicon-on-insulator material, wherein the thickness of the substrate is 300-500 microns, the doping concentration is 10 ^{14-10 15} /cm ³ , the thickness of the buried oxide layer on the substrate is 0.5-3 microns, SOI The thickness of the layer is 5-20 microns, and the doping of the SOI layer is 5e14cm ^-3 -1e15cm ^-3 ; The second step: photolithography, ion-implanting N-type impurities in the right area of the silicon wafer surface and annealing to make an N-type buffer layer, the thickness of the formed N-type buffer layer is 2 to 4 microns; The third step: photolithography, etch the groove on the left side of the silicon wafer surface, and thermally oxidize and grow the gate oxide layer on the silicon wafer surface, and deposit the gate electrode material; photolithography, etch the unnecessary gate electrode material and gate The oxide layer forms the gate electrode; The fourth step: photolithography, on the left side of the drift region on the surface of the silicon wafer, ion-implant P-type impurities and anneal to make a P-type base region, and the thickness of the formed P-type base region is 2 to 3 microns; The fifth step: photolithography, in the middle of the drift region on the surface of the silicon wafer, a P-type buried layer is formed by implanting P-type impurities with high-energy ions. The depth of the P-type buried layer from the surface is 0.5-1 micron, the thickness is 0.5-1 micron, and the concentration is 5e15cm ^-3 ～1e16cm ^-3 ; Step 6: photolithography, by ion implanting N-type impurities in the middle of the drift region on the surface of the silicon wafer and annealing to make N-type stripe regions, the concentration of the formed N-type stripe regions is 5e15cm ^-3 ~ 1e16cm ^-3 ; The seventh step: photolithography, making N ⁺ source region and N ⁺ collector region by ion implanting N-type impurities on the surface of the silicon wafer; The eighth step: photolithography, ion-implanting P-type impurities on the surface of the silicon wafer and annealing to make a P-type contact region, the thickness of the formed N-type source region and P-type contact region is about 0.2 to 0.3 microns; Step 9: photolithography, etching and filling medium to form a dielectric groove, the depth of the formed dielectric groove structure is 1-2 microns, and the width is 0.1-0.5 microns; Step 10: Photolithography, in the right area of the silicon wafer surface, ion-implant P-type impurities and anneal at low temperature to make a P-type collector region, and the thickness of the formed P-type collector region is 0.3-0.5 microns; The eleventh step: depositing, photolithography, and etching a dielectric layer to form a dielectric layer; The twelfth step: Depositing, photolithography, and etching metal to form a metal emitter and a metal collector on the surface of the device; that is, the SOI-RC-LIGBT device is prepared.