CN112490121A - Metal-assisted electrochemical p-type/insulating silicon carbide etching method - Google Patents
Metal-assisted electrochemical p-type/insulating silicon carbide etching method Download PDFInfo
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- CN112490121A CN112490121A CN202011502971.8A CN202011502971A CN112490121A CN 112490121 A CN112490121 A CN 112490121A CN 202011502971 A CN202011502971 A CN 202011502971A CN 112490121 A CN112490121 A CN 112490121A
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- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
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- H—ELECTRICITY
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
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Abstract
The invention relates to a p-type/insulation-type silicon carbide etching method of metal-assisted electrochemistry, which divides an etching process into three stages, wherein the first stage comprises the following steps: sputtering a metal film on the surface of the p-type/insulation-type silicon carbide and carrying out graphical treatment; and a second stage: laser scanning is carried out before etching, and the light receiving position exceeds the photochemical etching melting threshold value, so that the depth-to-width ratio of etching can be effectively improved; and a third stage: soaking p-type/insulation-type silicon carbide single crystal chip in H2O2Etching reaction is carried out in HF solution, and photochemical reaction is carried out with the assistance of ultraviolet light. The invention adopts inert metals such as Pt, W, Ti and the like as metal masks and adopts H2O2And HF is used as an etching solution, no metal element exists in the etching solution, the etching solution and the metal mask can not react in the etching process, and metal particles of the metal mask can not be released into the etching solution, so that metal pollution is effectively avoided.
Description
Technical Field
The invention relates to the technical field of silicon carbide etching, in particular to a p-type/insulating type silicon carbide etching method based on metal-assisted electrochemistry.
Background
SiC is a new-generation semiconductor material having excellent material characteristics such as three times the energy band width, 10 times the high insulating and electric field resistance, 2 times the saturated electron velocity, and 3 times the excellent thermal conductivity as compared with silicon materials; the power consumption is relatively low, the generated heat is less, and the efficiency is high.
SiC single crystals are very inert materials to chemical agents, and wet etching of SiC single crystals is very difficult. Neither acid nor base can corrode SiC single crystals at room temperature.
The current SiC etching methods mainly include dry plasma reactive ion etching and molten salt wet etching. Among them, dry plasma reactive ion etching of SiC single crystals is easy, but obtaining a mask material with a high selectivity ratio is challenging; the metal mask material can effectively improve the etching selection ratio, but in the etching process, metal particles sputtered from the metal mask can generate non-volatile metal byproducts, so that metal pollution in the whole device process is formed. Compared with wet process equipment, dry process equipment is relatively invested, element is mostly adopted as reaction gas, and the atmospheric environment is destroyed by reaction tail gas, so tail gas treatment is also a difficulty of the process. The molten salt wet etching method is to etch SiC single crystal at 450-600 deg.CoKOH, NaOH or Na meltable under C2O2And (6) corrosion. In these molten salts, SiC is first oxidized, and then the oxide is removed by the molten salt. The low aspect ratio of the molten salt wet etching method is not favorable for the preparation of the micro-electromechanical structure with the nanometer scale, and can easily cause serious K, Na contamination.
Therefore, the present invention was made in view of the above problems of the silicon carbide etching method, and the present invention was made.
Disclosure of Invention
The invention aims to provide a metal-assisted electrochemical p-type/insulating silicon carbide etching method which can effectively avoid metal pollution.
In order to achieve the purpose, the invention adopts the technical scheme that:
a metal-assisted electrochemical p-type/insulating silicon carbide etching method comprises the following steps:
step 1, cleaning a silicon carbide single crystal chip;
step 2, sputtering a metal film on the surface of the p-type/insulation-type silicon carbide single crystal chip and carrying out graphical treatment, wherein the metal film is a Pt, W or Ti film; after patterning, heating to 1200 ℃ at 800 ℃ for 20-30 minutes under argon, maintaining the temperature for 10-15 minutes, and then annealing;
step 3, performing laser scanning on the p-type/insulation-type silicon carbide single crystal chip;
specifically, a p-type/insulation-type silicon carbide single crystal chip is placed on a moving platform, and the whole area is scanned by femtosecond laser;
step 4, carrying out photochemical etching treatment on the p-type/insulation-type silicon carbide single crystal chip after laser scanning;
specifically, mixing H2O2Mixing with HF to form etching solution, placing the etching solution in an ultrasonic cleaning tank, soaking the laser-scanned p-type/insulating silicon carbide single crystal chip in the etching solution for 30-90 min, and applying forward bias voltage with a metal mask as an electrode while soaking.
In the step 2, before sputtering the metal film, the surface of the silicon carbide single crystal chip is sputtered by argon plasma, and cleaning is performed.
In the step 2, the thickness of the metal film is 150-300 nm.
In the step 3, the laser wavelength is 351--2(ii) a The laser spot diameter D was 10 ± 1 μm, the scanning speed was v, the laser pulse frequency f, and the number of accumulated pulses n = (D × f)/v.
In said step 4, H2O2The mixing ratio with HF is 1: 1.
in said step 4, H2O2In a concentration of 0.06mol L-1The concentration of HF was 1.31molL-1。
In the step 4, the positive bias voltage is applied to be 0.45-5 mV.
After the scheme is adopted, the etching process is divided into three stages, wherein the first stage comprises the following steps: sputtering a metal film on the surface of the p-type/insulation-type silicon carbide and carrying out graphical treatment; and a second stage: laser scanning is carried out before etching, and the light receiving position exceeds the photochemical etching melting threshold value, so that the depth-to-width ratio of etching can be effectively improved; and a third stage: soaking p-type/insulation-type silicon carbide single crystal chip in H2O2Etching reaction is carried out in HF solution, and photochemical reaction is carried out with the assistance of ultraviolet light. The invention adopts inert metals such as Pt, W, Ti and the like as metal masks and adopts H2O2And HF is used as an etching solution, no metal element exists in the etching solution, the etching solution and the metal mask can not react in the etching process, and metal particles of the metal mask can not be released into the etching solution, so that metal pollution is effectively avoided.
Drawings
FIG. 1 is a flow chart of a sputtering process of the present invention;
FIG. 2 is a schematic view of a laser scanning process of the present invention;
fig. 3 is a schematic diagram of an etching reaction of p-type/insulating silicon carbide.
Detailed Description
The invention discloses a metal-assisted electrochemical p-type/insulating silicon carbide etching method, which specifically comprises the following steps:
step 1, cleaning the silicon carbide single crystal chip. The cleaning here is performed by a conventional liquid cleaning method, for example, RCA cleaning or the like.
Step 2, sputtering is carried out on the surface of the p-type/insulation type silicon carbide single crystal chip, as shown in fig. 1, specifically as follows:
2.1, sputtering the surface of the silicon carbide single crystal chip by using argon plasma, and cleaning;
and 2.2, sputtering a metal film on the surface of the p-type/insulation type silicon carbide single crystal chip by PECVD (physical deposition), wherein the metal film is a Pt, W or Ti film, and the film thickness is 150-300 nm. The metal film is used as a mask, which can be used as a catalyst in a subsequent etching reaction process to improve the etching efficiency.
And 2.3, after the metal film is sputtered, carrying out patterning treatment on the metal film, wherein the patterned part can expose the surface of the silicon carbide single crystal chip.
And 2.4, raising the temperature to 1200 ℃ at 800 ℃ for 20-30 minutes under argon, maintaining the temperature for 10-15 minutes, and then annealing. The conductivity of the metal film and the p-type/insulation type silicon carbide single crystal chip can be effectively improved through the treatment, and the higher the conductivity is, the higher the subsequent etching rate is.
And 3, performing laser scanning on the p-type/insulating type silicon carbide single crystal chip.
Specifically, as shown in fig. 2, a silicon carbide single crystal chip was placed on a two-dimensionally controlled moving stage, moved to a fineness of 40 to 50nm, and scanned over the entire area with a femtosecond laser. The laser wavelength is 351-353nm, and the light intensity is 100-150wcm-2(ii) a The laser spot diameter D was 10 ± 1 μm, the scanning speed was v, the laser pulse frequency f, and the number of accumulated pulses n = (D × f)/v.
Generally, the number of pulses and the light intensity are proportional to the aspect ratio of etching and the etching rate, and the larger the number of pulses, the larger the light intensity, the larger the aspect ratio of etching on the silicon carbide single crystal chip, and the faster the etching rate.
In the laser scanning process, for the part without the metal film coverage, laser enters the silicon carbide single crystal chip and gathers energy on the etching surface, and the energy is greater than the melting threshold of the silicon carbide, so that the static state of the etching surface is changed; and at the position where the metal film is provided, the laser energy is weakened, and the energy entering the silicon carbide after passing through the metal film is less than the melting threshold of the silicon carbide, so that the crystalline state of the part is not changed.
And 4, carrying out photochemical etching treatment on the p-type/insulating type silicon carbide single crystal chip subjected to laser scanning.
Specifically, as shown in FIG. 3, H is2O2Mixing with HF to form etching solution, placing the etching solution in an ultrasonic cleaning tank, soaking the laser-scanned p-type/insulating silicon carbide single crystal chip in the etching solution for 30-90 min, and applying forward bias voltage with a metal mask as an electrode while soaking. Meanwhile, ultrasonic oscillation may be applied.
In this embodiment, H2O2In a concentration of 0.06mol L-1The concentration of HF was 1.31molL-1The mixing ratio of the two is 1: 1. wherein H2O2As an oxidizing agent, it reacts silicon carbide to silicon dioxide, which further reacts with HF to H2SiF 6. The application of a positive bias to p-type/insulating silicon carbide causes hole electrons to be generated at its surface. In this example, the positive bias was applied at 0.45-5 mV. In general, the bias voltage is proportional to the etching rate, and the larger the bias voltage, the more hole electrons and the more hole electrons are formed on the p-type/insulating silicon carbide surface, and the faster the etching rate is.
The ultrasonic oscillation can make the etching solution more uniform, so that the etching speed and the etching effect of each part on the single crystal chip are relatively consistent.
In summary, the key point of the present invention is that the etching process is divided into three stages, the first stage: sputtering a metal film on the surface of the p-type/insulation-type silicon carbide and carrying out graphical treatment; and a second stage: laser scanning is carried out before etching, and the light receiving position exceeds the photochemical etching melting threshold value, so that the depth-to-width ratio of etching can be effectively improved; and a third stage: soaking p-type/insulation-type silicon carbide single crystal chip in H2O2The etching reaction is carried out in HF solution, and the electrochemical reaction is carried out with the assistance of bias voltage. The invention adopts inert metals such as Pt, W, Ti and the like as metal masks and adopts H2O2And HF is used as an etching solution, no metal element exists in the etching solution, the etching solution and the metal mask can not react in the etching process, and metal particles of the metal mask can not be released into the etching solution, so that metal pollution is effectively avoided.
The above description is only exemplary of the present invention and is not intended to limit the technical scope of the present invention, so that any minor modifications, equivalent changes and modifications made to the above exemplary embodiments according to the technical spirit of the present invention are within the technical scope of the present invention.
Claims (7)
1. A metal-assisted electrochemical p-type/insulation type silicon carbide etching method is characterized by comprising the following steps: the method comprises the following steps:
step 1, cleaning a silicon carbide single crystal chip;
step 2, sputtering a metal film on the surface of the p-type/insulation-type silicon carbide single crystal chip and carrying out graphical treatment, wherein the metal film is a Pt, W or Ti film; after patterning, heating to 1200 ℃ at 800 ℃ for 20-30 minutes under argon, maintaining the temperature for 10-15 minutes, and then annealing;
step 3, performing laser scanning on the p-type/insulation-type silicon carbide single crystal chip;
specifically, a p-type/insulation-type silicon carbide single crystal chip is placed on a moving platform, and the whole area is scanned by femtosecond laser;
step 4, carrying out photochemical etching treatment on the p-type/insulation-type silicon carbide single crystal chip after laser scanning;
specifically, mixing H2O2Mixing with HF to form etching solution, placing the etching solution in an ultrasonic cleaning tank, soaking the laser-scanned p-type/insulating silicon carbide single crystal chip in the etching solution for 30-90 min, and applying forward bias voltage with a metal mask as an electrode while soaking.
2. The method of claim 1, wherein the p-type/insulating-type silicon carbide etching process comprises: in the step 2, before sputtering the metal film, the surface of the silicon carbide single crystal chip is sputtered by argon plasma, and cleaning is performed.
3. The method of claim 1, wherein the p-type/insulating-type silicon carbide etching process comprises: in the step 2, the thickness of the metal film is 150-300 nm.
4. The method of claim 1, wherein the p-type/insulating-type silicon carbide etching process comprises: in the step 3, the laser wavelength is 351--2(ii) a The laser spot diameter D was 10 ± 1 μm, the scanning speed was v, the laser pulse frequency f, and the number of accumulated pulses n = (D × f)/v.
5. The method of claim 1, wherein the p-type/insulating-type silicon carbide etching process comprises: in said step 4, H2O2The mixing ratio with HF is 1: 1.
6. a metal-assisted electrochemical p-type/insulating silicon carbide etching method according to claim 1 or 5, wherein: in said step 4, H2O2In a concentration of 0.06mol L-1The concentration of HF was 1.31molL-1。
7. The method of claim 1, wherein the p-type/insulating-type silicon carbide etching process comprises: in the step 4, the positive bias voltage is applied to be 0.45-5 mV.
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| CN202011502971.8A CN112490121A (en) | 2020-12-18 | 2020-12-18 | Metal-assisted electrochemical p-type/insulating silicon carbide etching method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115637432A (en) * | 2022-09-30 | 2023-01-24 | 东莞赛诺高德蚀刻科技有限公司 | Method for manufacturing workpiece with pores and high-aspect-ratio grooves and metal workpiece |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10256428A1 (en) * | 2002-12-02 | 2004-06-17 | Technische Universität Carolo-Wilhelmina Zu Braunschweig | Structuring surface of electrically conducting semiconductor material comprises applying metal mask on surface of semiconductor material, anodically oxidizing regions not protected, and further processing |
| TW200731018A (en) * | 2006-02-07 | 2007-08-16 | Univ Tsing Hua | Method and apparatus for photoelectrochemical etching |
| WO2011009654A1 (en) * | 2009-07-22 | 2011-01-27 | Robert Bosch Gmbh | Semiconductor arrangement having a silicon carbide substrate and method for the production thereof |
| CN104118842A (en) * | 2014-07-02 | 2014-10-29 | 上海师范大学 | Silicon carbide mesoporous array material and manufacturing method of silicon carbide mesoporous array material |
| JP2017212262A (en) * | 2016-05-23 | 2017-11-30 | 株式会社豊田中央研究所 | Etching solution, etching apparatus, and etching method used for photoelectrochemical etching of silicon carbide (SiC) substrate |
| CN111071986A (en) * | 2019-12-30 | 2020-04-28 | 北京航空航天大学 | A method for preparing silicon carbide multilevel microstructure assisted by laser modification and an acceleration sensor |
-
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- 2020-12-18 CN CN202011502971.8A patent/CN112490121A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10256428A1 (en) * | 2002-12-02 | 2004-06-17 | Technische Universität Carolo-Wilhelmina Zu Braunschweig | Structuring surface of electrically conducting semiconductor material comprises applying metal mask on surface of semiconductor material, anodically oxidizing regions not protected, and further processing |
| TW200731018A (en) * | 2006-02-07 | 2007-08-16 | Univ Tsing Hua | Method and apparatus for photoelectrochemical etching |
| WO2011009654A1 (en) * | 2009-07-22 | 2011-01-27 | Robert Bosch Gmbh | Semiconductor arrangement having a silicon carbide substrate and method for the production thereof |
| CN104118842A (en) * | 2014-07-02 | 2014-10-29 | 上海师范大学 | Silicon carbide mesoporous array material and manufacturing method of silicon carbide mesoporous array material |
| JP2017212262A (en) * | 2016-05-23 | 2017-11-30 | 株式会社豊田中央研究所 | Etching solution, etching apparatus, and etching method used for photoelectrochemical etching of silicon carbide (SiC) substrate |
| CN111071986A (en) * | 2019-12-30 | 2020-04-28 | 北京航空航天大学 | A method for preparing silicon carbide multilevel microstructure assisted by laser modification and an acceleration sensor |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115637432A (en) * | 2022-09-30 | 2023-01-24 | 东莞赛诺高德蚀刻科技有限公司 | Method for manufacturing workpiece with pores and high-aspect-ratio grooves and metal workpiece |
| CN115637432B (en) * | 2022-09-30 | 2023-08-22 | 东莞赛诺高德蚀刻科技有限公司 | Manufacturing method of workpiece with holes and high-aspect-ratio grooves and metal workpiece |
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