CN112352305B - Chip packaging structure and chip packaging method - Google Patents

Abstract

The present application provides a chip packaging structure and a chip packaging method. The chip packaging structure includes a chip 11 and a plastic packaging material 12 that fully wraps the chip. Wherein, the chip 11 is provided with a conductor column 111, and the first end of the conductor column 111 is coupled to the internal circuit of the chip 11 through the plastic encapsulation material, and the second end of the conductor column 111 is used for the chip 11 to couple the external circuit. . It can be seen that the chip packaging structure fully wraps the chip 11 through the plastic packaging material 12, which can balance the stress between the chip 11 and the plastic packaging material 12 in all directions while protecting all sides of the chip 11, thereby avoiding stress on the chip 11 in a certain direction. Problems such as cracking and chipping of the chip 11 caused by excessive size improve the long-term reliability of the packaged chip structure.

Description

Chip packaging structure and chip packaging method

technical field

The present application relates to the technical field of chip packaging, in particular to a chip packaging structure and a chip packaging method.

Background technique

Wafer Level Chip Scale Packaging (WLCSP for short), that is, wafer-level chip packaging, is different from the traditional chip packaging method of cutting first and then packaging and testing. WLCSP is to package and package on the entire wafer first. Test, and then cut into IC particles one by one, so the packaged volume is equal to the original size of the IC die. The WLCSP packaging method can reduce the size of the chip module and meet the high-density requirements of the chip for the body space.

Usually a WLCSP packaged chip includes a silicon layer (bare chip), a redistribution layer, a plastic packaging layer, and solder balls for the chip to be electrically connected to an external circuit. Among them, the plastic encapsulation layer usually half-wraps the silicon layer and the rewiring layer. The thermal expansion coefficients of the plastic encapsulation layer, the silicon layer, and the redistribution layer are different. Warped edge deformation, and even lead to chip cracking, chipping and other problems.

Contents of the invention

In the first aspect, the embodiment of the present application provides a chip packaging structure, including: a chip and a plastic packaging material that fully wraps the chip, a conductive post is provided on the chip, the conductive post passes through the plastic packaging material, and the first end of the conductive post is covered. Coupled to the internal circuitry of the chip, the second end of the conductor post is used to couple the chip to external circuitry.

The above-mentioned chip packaging structure fully wraps the chip with the plastic packaging material, which can balance the stress between the chip and the plastic packaging material in all directions while protecting all sides of the chip, thereby avoiding cracking of the chip caused by excessive stress in a certain direction of the chip, It can improve the long-term reliability of the packaged chip structure.

In an implementation of the first aspect, the plastic packaging material is integrally formed, which can avoid the interface between the plastic packaging materials formed many times in the prior art, thereby preventing external water vapor from entering the chip through the interface and causing the chip to be damaged. failure, improve the sealing performance of the plastic packaging structure formed by the plastic packaging material, and improve the long-term reliability of the chip.

In an implementation of the first aspect, the outer surface of the molding material is flush with the end surface of the second end of the conductor post.

Further, the chip packaging structure further includes: solder balls disposed on the second ends of the conductor posts. In the chip packaging structure, the solder balls are located outside the plastic packaging material, which does not restrict the free melting and solidification process of the solder alloy when the solder balls are soldered at high temperature, and improves the firmness of the soldering between the chip and the external circuit.

In an implementation of the first aspect, the chip includes:

bare chip;

a first insulating layer, the first insulating layer covers the bare chip;

a rewiring layer, the rewiring layer is arranged on the surface of the first insulating layer facing away from the bare chip, and fills the first via hole penetrating through the first insulating layer, and is coupled to the internal circuit of the bare chip;

a second insulating layer, the second insulating layer covers the first insulating layer and partially covers the rewiring layer, and opens a second via hole for exposing part of the rewiring layer;

The conductor column fills the second via hole, the first end of the conductor column is electrically connected to the internal circuit of the bare chip, and the end surface of the second end of the conductor column is higher than the surface of the second insulating layer facing away from the bare chip.

Further, the surface of the bare chip may include one or more passive components to enhance the function of the chip.

Further, the thickness of the first insulating layer is 20um-120um.

In the second aspect, the embodiment of the present application also provides a chip packaging method, including:

A plurality of chips are provided, the first surface of the chip is provided with a conductive post, the first end of the conductive post is coupled to the internal circuit of the chip, and the second end of the conductive post is used for coupling the chip to an external circuit;

Bonding the second end of the conductor post on the carrier substrate to fix the chips on the carrier substrate, with gaps between adjacent chips;

forming a plastic encapsulation material that fully wraps the chip;

Cutting the molding material based on the gap between the chips and removing the carrier substrate to obtain multiple chip packaging structures.

The above chip packaging method includes: providing a plurality of chips, the first surface of the chip is provided with a conductor column, the first end of the conductor column is coupled to the internal circuit of the chip, the second end of the conductor column is used for coupling the external circuit of the chip, and the conductor The end surface of the second end of the column is higher than the first surface, and the chip is bonded to the carrier substrate through the second end of the conductor column. There is a gap between the conductor column and the carrier substrate, and the plastic sealing material can fill the space between the conductor column and the carrier substrate. The gap, and then fully wrap the chip, the plastic packaging material that fully wraps the chip can not only protect the various surfaces of the chip, but also balance the stress between the chip and the plastic packaging material in all directions, thereby avoiding the damage of the chip caused by excessive stress in a certain direction. Cracking, chipping and other problems, improve the long-term reliability of the packaged chip structure.

Moreover, the one-time molding of the plastic encapsulation material covering each surface of the chip can avoid the interface between the plastic encapsulation materials formed many times in the prior art, thereby preventing external water vapor from entering the chip through the interface and causing the chip to fail, improving the performance of the chip. The plastic encapsulation material forms the airtightness of the plastic encapsulation structure and improves the long-term reliability of the chip.

In an implementation of the first aspect, after the carrier substrate is removed, solder balls may be formed on the second ends of the conductor posts, so that the chip is coupled to an external circuit through the solder balls. It can be seen that in the chip packaging structure, the solder balls are located outside the plastic packaging material, which does not restrict the free melting and solidification process of the solder alloy during high-temperature soldering, and improves the firmness of the soldering between the chip and the external circuit.

In the first implementation of the first aspect, an implementation manner of providing multiple chips may be:

providing a wafer comprising a plurality of die;

forming a first insulating layer covering the plurality of bare chips on the surface of the wafer;

A first via hole is opened on the first insulating layer. The first via hole is used to expose the signal connection end of the bare chip. The signal connection end is used for coupling the bare chip to an external circuit. The signal connection end can be an internal the input and/or output of the circuit;

forming a rewiring layer on the surface of the first insulating layer facing away from the wafer, the rewiring layer filling the first via hole and connected to the signal connection end;

forming a second insulating layer covering the redistribution layer and the first insulating layer;

Opening a second via hole on the second insulating layer, the second via hole is used to partially expose the rewiring layer;

forming a conductor column filling the second via hole, the first end of the conductor column is electrically connected to the internal circuit of the bare chip, and the end face of the second end of the conductor column is higher than the surface of the second insulating layer facing away from the bare chip;

cutting the first insulating layer, the second insulating layer and the wafer to obtain chips corresponding to the plurality of bare chips one by one.

Further, the bare chip also includes a passive element electrically connected to the bare chip, wherein an implementation manner of forming the first insulating layer covering the plurality of bare chips on the surface of the wafer may be: the first material is composed of The paste is placed on the wafer; the paste is heated and cured to form the first insulating layer.

The above method can form a thicker first insulating layer, so as to realize the integration of passive devices into the chip.

In the third aspect, the embodiment of the present application also provides an integrated circuit device, the integrated circuit device includes: a substrate and a chip, the chip is fully covered by a plastic encapsulation material, the chip is provided with a conductor post, and the conductor post passes through the plastic encapsulation material, The chip is supported on the substrate, the first end of the conductor column is coupled to the internal circuit of the chip, and the second end of the conductor column is coupled to the circuit on the substrate.

In the above-mentioned integrated circuit device, the plastic encapsulation material fully wraps the chip, which can balance the stress between the chip and the plastic encapsulation material in all directions while protecting all sides of the chip, thereby avoiding cracking of the chip caused by excessive stress in a certain direction of the chip , chipping and other issues, and improve the long-term reliability of the packaged chip structure.

In an implementation of the third aspect, the plastic encapsulation material forms an integrally formed structure, which can avoid the interface between the plastic encapsulation materials formed multiple times in the prior art, thereby preventing external water vapor from entering the chip through the interface and causing chip damage. failure, improve the sealing performance of the plastic packaging structure formed by the plastic packaging material, and improve the long-term reliability of the chip.

In yet another implementation of the third aspect, the outer surface of the molding material is flush with the end surface of the second end of the conductor post.

Further, solder balls are provided on the second ends of the conductor posts, and the solder balls are used for direct soldering or soldering with the circuit on the substrate. In the chip packaging structure, the solder balls are located outside the plastic packaging material, which does not restrict the free melting and solidification process of the solder alloy when the solder balls are soldered at high temperature, and improves the firmness of the soldering between the chip and the external circuit.

In yet another implementation of the third aspect, the chip may include:

bare chip;

a first insulating layer, the first insulating layer covers the bare chip;

a rewiring layer, the rewiring layer is arranged on the surface of the first insulating layer facing away from the bare chip, and fills the first via hole penetrating through the first insulating layer, and is coupled to the internal circuit of the bare chip;

a second insulating layer, the second insulating layer covers the first insulating layer and partially covers the rewiring layer, and opens a second via hole for exposing part of the rewiring layer;

The conductor column fills the second via hole, the first end of the conductor column is electrically connected to the internal circuit of the bare chip, and the end surface of the second end of the conductor column is higher than the surface of the second insulating layer facing away from the bare chip.

Further, the surface of the bare chip includes one or more passive devices.

Further, the thickness of the first insulating layer is 20um-120um.

In the fourth aspect, the embodiment of the present application also provides an integrated circuit, the integrated circuit includes: a substrate and a chip, the chip is fully wrapped by a plastic encapsulation material, the chip is provided with a conductor post, the conductor post passes through the plastic encapsulation material, and the chip supports On the substrate, the first end of the conductor column is coupled to the internal circuit of the chip, and the second end of the conductor column is coupled to the circuit on the substrate.

In the above-mentioned integrated circuits, the plastic packaging material fully wraps the chip, which can balance the stress between the chip and the plastic packaging material in all directions while protecting all sides of the chip, thereby avoiding cracking of the chip caused by excessive stress in a certain direction of the chip, It can improve the long-term reliability of the packaged chip structure.

In an implementation of the fourth aspect, the plastic encapsulation material forms an integrated molding structure, which can avoid the interface between the plastic encapsulation materials formed multiple times in the prior art, thereby preventing external water vapor from entering the chip through the interface and causing chip damage. failure, improve the sealing performance of the plastic packaging structure formed by the plastic packaging material, and improve the long-term reliability of the chip.

In yet another implementation of the fourth aspect, the outer surface of the molding material is flush with the end surface of the second end of the conductor post.

Further, solder balls are provided on the second ends of the conductor posts, and the solder balls are used for direct soldering or soldering with the circuit on the substrate. In the chip packaging structure, the solder balls are located outside the plastic packaging material, which does not restrict the free melting and solidification process of the solder alloy when the solder balls are soldered at high temperature, and improves the firmness of the soldering between the chip and the external circuit.

In yet another implementation of the fourth aspect, the chip may include:

bare chip;

a first insulating layer, the first insulating layer covers the bare chip;

a rewiring layer, the rewiring layer is arranged on the surface of the first insulating layer facing away from the bare chip, and fills the first via hole penetrating through the first insulating layer, and is coupled to the internal circuit of the bare chip;

a second insulating layer, the second insulating layer covers the first insulating layer and partially covers the rewiring layer, and opens a second via hole for exposing part of the rewiring layer;

The conductor column fills the second via hole, the first end of the conductor column is electrically connected to the internal circuit of the bare chip, and the end surface of the second end of the conductor column is higher than the surface of the second insulating layer facing away from the bare chip.

Further, the surface of the bare chip includes one or more passive devices.

Further, the thickness of the first insulating layer is 20um-120um.

Description of drawings

FIG. 1 is a schematic structural diagram of a chip packaging structure provided in an embodiment of the present application;

FIG. 2 is a schematic structural diagram of another chip packaging structure provided by the embodiment of the present application;

FIG. 3 is a schematic flow diagram of a chip packaging method provided in an embodiment of the present application;

FIG. 4 is a schematic flow diagram of another chip packaging method provided by the embodiment of the present application;

5A-5O are structural schematic diagrams corresponding to each process of a chip packaging method provided in the embodiment of the present application;

FIG. 6 is a schematic structural diagram of an integrated circuit provided in an embodiment of the present application;

FIG. 7 is a schematic structural diagram of an integrated circuit device provided by an embodiment of the present application.

Detailed ways

For ease of understanding, some concepts and background are briefly introduced first.

Printed Circuit Board (PCB) is an important electronic component, a support for electronic components, and a carrier for electrical connections of electronic components. Because it is made using electronic printing, it is called a "printed" circuit board. The electrical connection between the I/O terminal of the chip and the PCB is realized through board-level surface mount technology (surface mount technology, SMT).

Wafer refers to the silicon wafer used in the production of silicon semiconductor integrated circuits. Because of its circular shape, it is called a wafer. It can be processed into various circuit element structures on silicon wafers, and become IC products with specific electrical functions

Wafer (die) refers to a small piece cut from a wafer, which is a chip. Before the wafer is packaged, the chips on the wafer or the chips cut from the wafer are called bare chips.

Passive components, also known as passive components, refer to components that can work when there is a signal without power supply in the circuit, mainly resistors, inductors and capacitors.

Integrated Passive Devices (Integrated Passive Devices, IPD) integrates discrete passive components inside the substrate to improve device system integration and reduce the size and weight of the entire product.

Half-wrapped, in this application, refers to the part of the surface of the chip wrapped by the plastic encapsulation material, exposing the part of the chip that is not a conductive post, and the conductive post is the connection end for coupling the external circuit on the chip, that is to say, at least one surface of the chip is not covered by the plastic encapsulation material cover. Generally, a chip includes an upper surface, a lower surface, and four sides. For example, in the prior art, the plastic encapsulation material usually wraps the components on the upper surface of the silicon substrate in the chip (such as the internal circuit of the chip, the rewiring layer, etc.), and the silicon lining The lower surface of the bottom is usually not protected by molding compound.

Full wrapping, in this application, refers to wrapping all surfaces of the chip, except for the end surface of the chip on which the conductive post used to couple the external circuit faces away from the chip. In the embodiment of the present application, fully encapsulating the chip with the plastic encapsulation material means that the plastic encapsulation material encloses all parts of the chip except the end surface of the conductor post facing away from the chip.

Usually a WLCSP packaged chip includes a silicon layer (bare chip), a redistribution layer, and solder balls used to electrically connect the chip to external circuits. The encapsulation method of the WLCSP may cause the following problems:

(1) During the chip cutting process, there may be quality problems such as partial cracking and chipping of the silicon layer.

(2) After the chip is packaged, the back of the chip is a bare silicon layer. Due to the brittleness of the silicon material, it cannot withstand the pressure imposed by the subsequent electrical test, so that the WLCSP packaged chip cannot be tested and used directly on the board level, resulting in the use of the WLCSP package. The product defect rate of chips has increased.

(3) Due to the different expansion coefficients of the silicon layer, the rewiring layer, and the plastic packaging material, the "popcorn" problem occurs during the board-level high-temperature process of the WLCSP packaged chip, which affects poor long-term reliability.

The technical solutions in the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application.

In the embodiment of the present application, the chip is a chip to be packaged, which can be a memory (Memory), a micro-electro-mechanical system (Micro-Electro-Mechanical System, referred to as MEMS), a microwave radio frequency chip, an application-specific integrated circuit (Application Specific Integrated Circuit, referred to as ASIC) and other chips . It should be understood that the chips listed here are only illustrative, and this application is not limited thereto.

As shown in FIG. 1 , a schematic diagram of a chip packaging structure, the chip packaging structure includes a chip 11 and a plastic packaging material 12 that fully wraps the chip 11 . Wherein, the chip 11 has opposite first surface and second surface, the first surface of the chip 11 has a conductor column 111, the first end of the conductor column 111 is coupled to the internal circuit of the chip 11, the second end of the conductor column 111 is used for Coupling external circuits to the chip 11. The conductive post 111 passes through the molding material 12 , that is, the second end of the conductive post 111 is higher than the first surface and is exposed outside the molding material 12 . It should be understood that the first end and the second end of the conductor post 111 are opposite ends of the conductor post 111; the external circuit is a circuit other than the chip, which may be a circuit on the substrate.

It can be seen that the chip packaging structure fully wraps the chip 11 through the plastic packaging material 12, which can balance the stress between the chip 11 and the plastic packaging material 12 in all directions while protecting all sides of the chip 11, thereby avoiding stress on the chip 11 in a certain direction. Problems such as cracking and chipping of the chip 11 caused by excessive size improve the long-term reliability of the packaged chip structure.

As shown in the chip packaging structure of FIG. 2 , the chip 11 may be a pre-packaged chip, and the chip 11 includes a bare chip 112 , a first insulating layer 113 , a rewiring layer 114 , a second insulating layer 115 and a conductor post 111 . Wherein, the first insulating layer 113 covers the bare chip 114; the redistribution layer 114 is disposed on the surface of the first insulating layer 113 facing away from the bare chip 112, and fills the first via hole 116 penetrating through the first insulating layer 113, and is coupled to the bare chip 11 internal circuit; the second insulating layer 115 covers the first insulating layer 113 and partially covers the redistribution layer 114, and opens a second via hole 117 for exposing part of the redistribution layer 114; the conductor column 111 fills the second via hole 117 , the first end of the conductive post 111 is electrically connected to the internal circuit of the bare chip 112 , and the end surface of the second end of the conductive post 111 is higher than the surface of the second insulating layer 115 facing away from the bare chip 112 .

Optionally, the chip 11 may be a bare chip. When the chip 11 is prepared, the signal connection end on the first surface of the chip 11 is prepared as a conductor column, and the end surface of the conductor column is higher than the first surface of the chip. Usually, the first surface of the chip 11 is the surface on the chip 11 including the active components. The signal connection section may be an output terminal and/or an input terminal of an internal circuit in the chip 11 .

Optionally, the molding material 12 is integrally formed, thereby avoiding the interface between the molding materials formed multiple times in the prior art, thereby preventing external water vapor from entering the chip through the interface and causing the chip to fail, and improving the performance of the plastic packaging film. Hermeticity, and improve the long-term reliability of the chip.

Optionally, the expansion coefficient of the molding material 12 is smaller than the expansion coefficient of the first insulating layer 113 and the expansion coefficient of the second insulating layer 115. When the chip packaging structure needs to be heated in the subsequent process or when the chip is working, heat will be generated, and the chip 11 Heat will cause expansion, and the plastic encapsulation material 12 can exert a force on the chip 11 inside, and reduce the expansion degree of the chip 11 in a balanced manner, thereby avoiding cracking and chipping of the chip, and further improving the long-term reliability of the packaged chip structure.

Optionally, the outer surface of the molding material 12 is flush with the end surface of the conductor post 111 , as shown in FIG. 1 .

Optionally, the chip package structure further includes solder balls 13 disposed on the second ends of the conductive pillars 111 . In the chip packaging structure, the solder ball 13 is located outside the plastic packaging material, which does not restrict the free melting and solidification process of the solder alloy during high-temperature soldering, and improves the firmness of the soldering between the chip and the external circuit. It can be understood that the solder ball 13 is not a necessary part in the embodiment of the present application. According to the specific usage scenarios of the chip, the chip package structure may not have the solder ball 13, but directly expose the bare chip 112 or the conductor column 111 of the chip package structure, or Conductive post 111 is used after performing surface treatment processes such as Organic Solderability Preservatives (OSP), Electroless Nickel/Immersion Gold (ENIG), and electroless tin plating.

In an embodiment of the present application, the surface of the bare chip 112 includes one or more passive devices to enhance the function of the chip, wherein the passive device may be an integrated passive device 118 (IPD) and/or an independent passive device 119.

It can be understood that when the surface of the bare chip 112 includes one or more passive devices, the thickness of the first insulating layer 113 is greater than the thickness of any one passive device. Optionally, the thickness of the first insulating layer may be 20um-120um.

Optionally, the chip packaging structure may further include a substrate, and the chip wrapped by the packaging material may be disposed on the upper surface of the substrate or hung on the lower surface of the substrate, which is not limited in this embodiment of the present application. The substrate may include circuits, and the solder balls may be connected to the circuits on the substrate through wires, so as to realize the coupling between the internal circuits of the chip and the circuits on the substrate. Optionally, solder balls or conductor posts can also be directly soldered on the substrate.

It should be noted that the first insulating layer 113 or the second insulating layer 115 may be a planarization layer. The first insulating layer 113 or the second insulating layer 115 may be composed of an inorganic insulating material or an organic insulating material. Wherein, the inorganic insulating material may be silicon dioxide (SiO ₂ ), silicon nitride (SiN ₄ ), etc., and the organic insulating material may be high molecular polymer or resin. Usually, the first insulating layer 113 or the second insulating layer 115 is a polymer film, such as photosensitive polyimide (polyimide, PI), polybenzoxazole (ploybenzoxazole, PBO) and the like.

The material of the molding material 12 may be one or a combination of epoxy resin (Epoxy Molding Compound, EMC), polyethylene, polypropylene, polyolefin, polyamide, polyurethane, and the like. For example, the molding material 12 is epoxy resin molding compound.

Please refer to FIG. 3-FIG. 4. FIG. 3 and FIG. 4 are schematic flowcharts of two chip packaging methods provided by the embodiment of the present application. Please also refer to FIGS. 5A-5O , which correspond to the cross-sectional schematic views of the chip packaging structure obtained in each step of the chip packaging method shown in FIG. 4 .

Step S1: providing a plurality of chips, the chip has opposite first surface and second surface, the first surface of the chip is provided with a conductor column, the first end of the conductor column is coupled to the internal circuit of the chip, the conductor column The second terminal is used for coupling the chip to an external circuit. The end surface of the second end of the conductor post is higher than the first surface.

In an embodiment of the present application, the chip may be a bare chip. When the chip is manufactured, the signal connection end on the first surface of the chip is prepared as a conductor column, and the end surface of the conductor column is higher than the first surface of the chip. Typically the first surface of the chip is the surface on the chip that includes the active elements.

Optionally, the first surface of the chip may further include an IPD, and passive components may be integrated on the chip during chip fabrication.

In an embodiment of the present application, the chip may be a chip after a preliminary packaging process, and the preliminary packaging process (ie step S1) may include the following steps:

Step S11 : providing a wafer 51 including a plurality of bare chips 511 . Please also refer to Figure 5A.

In an embodiment of the present invention, the bare chip 511 may include one or more passive devices to enhance the function of the chip. The passive device can be an IPD 512 or an independent passive component 513 can be attached to the surface of the bare chip 511 during chip fabrication.

Step S12 : forming a first insulating layer 52 covering the plurality of bare chips 511 on the surface of the wafer 51 . Please also refer to Figure 5B.

Optionally, the first insulating layer 52 may be a planarization layer. The first insulating layer 52 may be composed of an inorganic insulating material or an organic insulating material. Wherein, the inorganic insulating material may be silicon dioxide (SiO ₂ ), silicon nitride (SiN ₄ ), etc., and the organic insulating material may be high molecular polymer or resin. Usually, the first insulating layer 52 is a polymer film, such as photosensitive polyimide (polyimide, PI), polybenzoxazole (ploybenzoxazole, PBO) and the like.

Wherein, the method for forming the planarized first insulating layer 52 may include but not limited to the following methods:

For the bare chip 511 not including the passive device 512 , the prepared first insulating layer 52 may be thinner, and the first insulating layer 52 may be formed by a spin coating method. The spin coating process usually includes three steps of batching, high-speed rotation, and volatilization to form a film. The thickness of the film is controlled by controlling the time, rotation speed, drop volume, and the concentration and viscosity of the solution used.

For the bare chip 511 with passive devices installed, since the passive device itself has a relatively large thickness, the first insulating layer 52 needs to completely cover the passive device, so that the thickness of the first insulating layer 52 must be greater than that of any passive device. The thickness of the device. At this time, the dry film formed by the first material (such as PI) can be flattened on the wafer, and by heating, the dry film is melted and flows on the wafer so that the formed polymer film tends to be flat. Thin and volatilize the solvent in the dry film, and solidify to form the first insulating layer. The preparation method of the first insulating layer can overcome the disadvantage that the spin-coating method cannot prepare a thicker first insulating layer, and is an important procedure in realizing chip packaging including IPD and passive components.

Optionally, when the wafer 1 includes passive devices, the thickness of the first insulating layer 52 is greater than that of any passive device, and optionally, the thickness of the first insulating layer 52 may be 20um-120um.

It can be understood that the first insulating layer 52 also includes other preparation methods, which are not limited in this embodiment of the present application.

Step S13 : opening a first via hole 520 on the first insulating layer 52 , and the first via hole 520 is used to expose the signal connection end of the bare chip 511 (not shown in the figure). Wherein, the signal connection end is used for coupling the internal circuit of the bare chip 511 to the external circuit, and may include an input end and/or an output end. Please also refer to Figure 5C.

Wherein, the signal connection terminal may be a pad or an electrode provided on the surface of the wafer 51 , and is an input terminal or an output terminal of the bare chip 511 for coupling the bare chip 511 to an external circuit.

If the first insulating layer 52 is an inorganic insulating material, the first via hole 520 may be formed on the first insulating layer 52 by a photolithography process. For example, a photoresist is coated on the first insulating layer 52, the photoresist is partially exposed through a photomask, and the photoresist is partially removed by a developer to form a patterned photoresist, and then the patterned photoresist is In order to etch the first insulating layer 52 as a mask, a first via hole 520 penetrating through the first insulating layer 52 is formed at a position on the first insulating layer 52 that is shielded by the photomask.

If the first insulating layer 52 is photoresist, the first via hole 520 can be formed on the first insulating layer 52 through a photomask and development process. For example, the first insulating layer 52 is a negative photoresist, and the position corresponding to the input end and/or output end of the bare chip on the first insulating layer 52 is blocked by a photomask, and other positions on the first insulating layer 52 are exposed, and then passed The developing solution removes the unexposed photoresist, and forms the first via hole 520 penetrating through the first insulating layer 52 at the position blocked by the photomask on the first insulating layer 52 .

Wherein, the etching or etching process includes dry etching and wet etching, which are selected according to the characteristics of the material to be etched.

It can be understood that the first via hole 520 may also include other forming methods, such as laser drilling, etc., which are not limited in this embodiment of the present application.

Step S14 : forming a redistribution layer 53 on the surface of the first insulating layer 52 away from the wafer 51 , the redistribution layer 53 fills the first via hole 520 and is connected to the signal connection terminal. Please also refer to Figure 5D.

Wherein, the rewiring layer 53 is formed by a conductive material, and the conductive material can be metal, such as copper (Cu), silver (Ag), aluminum (Al) or other metal or metal alloy, etc., and the conductive material can also be indium oxide Tin (ITO), graphite, graphene, etc. are not limited in this embodiment of the present application. Moreover, the redistribution layers 53 on each bare chip 511 are independent and insulated from each other.

One implementation of step S14 may be: forming a first conductive layer on the first insulating layer 52 through a coating process, and then patterning the first conductive layer through a photolithography process to form a redistribution layer 53 .

Step S15 : forming a second insulating layer 54 covering the redistribution layer 53 and the first insulating layer 52 . Please also refer to Figure 5E.

Optionally, the second insulating layer 54 may be a planarization layer. The second insulating layer 54 may be composed of an inorganic insulating material or an organic insulating material. Wherein, the inorganic insulating material may be silicon dioxide (SiO ₂ ), silicon nitride (SiN ₄ ), etc., and the organic insulating material may be high molecular polymer or resin. Usually, the second insulating layer 54 is a polymer film, such as photosensitive polyimide (polyimide, PI), polybenzoxazole (ploybenzoxazole, PBO) and so on.

Usually the thickness of the redistribution layer 53 is small, and the thickness of the second insulating layer 54 covering the redistribution layer 53 is not less than the thickness of the redistribution layer 53 . The method of forming the second insulating layer 54 may include but not limited to the following methods:

A planarized second insulating layer 54 may be formed on the surface of the first insulating layer 52 and the redistribution layer 52 facing away from the wafer 51 by spin coating. The spin coating process usually includes three steps of batching, high-speed rotation, and volatilization to form a film. The thickness of the film is controlled by controlling the time, rotation speed, drop volume, and the concentration and viscosity of the solution used.

The second insulating layer 54 may also be formed on the surface of the first insulating layer 52 and the rewiring layer 53 facing away from the wafer 51 by chemical vapor deposition.

It can be understood that the second insulating layer 54 also includes other preparation methods, which are not limited in this embodiment of the present application.

Optionally, the thickness of the second insulating layer 54 may be 5-30um.

Step S16 : opening a second via hole 540 on the second insulating layer 54 , the second via hole 540 is used to partially expose the redistribution layer 53 . Please also refer to Figure 5F.

Similar to the method for forming the first via hole 520, if the second insulating layer 54 is made of an inorganic insulating material, the second via hole 540 may be formed on the second insulating layer 54 through a photolithography process. Specifically, a photoresist is coated on the second insulating layer 54, the photoresist is partially exposed through a photomask, and then the photoresist is partially removed by a developer to form a patterned photoresist, and then the patterned photoresist is formed. The glue is used as a mask to etch the second insulating layer 54 , and a second via hole 540 penetrating through the second insulating layer 54 is formed at a position on the second insulating layer 54 covered by the photomask.

If the second insulating layer 54 is photoresist, the second via hole 540 can be formed on the second insulating layer 54 through a photomask and development process. Specifically, if the second insulating layer 54 is a negative photoresist, the position corresponding to the part of the rewiring layer 53 on the second insulating layer 54 is blocked by a photomask, and other positions on the second insulating layer 54 are exposed, and then removed by a developer. The unexposed photoresist is formed on the second insulating layer 54 at the position covered by the photomask to form a second via hole 540 penetrating through the second insulating layer 54 .

It can be understood that the second via hole 540 may also include other forming methods, such as laser drilling, etc., which are not limited in this embodiment of the present application.

Step S17: forming a conductor column 55 filling the second via hole 540, the first end of the conductor column 55 is electrically connected to the internal circuit of the bare chip 511, and the end surface of the second end of the conductor column 55 is higher than the second insulating layer 54 The surface facing away from the bare chip 511 . Please also refer to Figure 5G.

Wherein, the conductor column 55 is formed by conductive material, and this conductive material can be metal, as copper (Cu), silver (Ag), tin (Sn), aluminum (Al) or other metal or metal alloy etc., and this conductive material also It may be indium tin oxide (ITO), graphite, graphene, etc., which is not limited in the embodiment of the present application.

One implementation of step S17 may be: forming a second conductive layer on the second insulating layer 54 through a coating process, and then patterning the second conductive layer through a photolithography process to form conductor columns 55 . The diameter of the conductive pillar 55 may be 100-1000um.

The conductor post can also be prepared by other methods, such as electroplating, printing, welding or a combination thereof, which is not limited in this embodiment of the present application.

Step S18: dicing the wafer to obtain chips corresponding to a plurality of bare chips. Cutting can be done by mechanical cutting, laser cutting or a combination thereof. Please refer to Figure 5H and Figure 5I together.

Step S2: bonding the second end of the conductor post 55 to the carrier substrate 56 to fix the chip on the carrier substrate 56, with gaps between adjacent chips. Please also refer to Figure 5J.

Specifically, a carrier substrate 56 is provided, an adhesive layer 57 is coated on the carrier substrate 56 , a chip is turned upside down, and the end surfaces of the conductor posts 55 are bonded to the carrier substrate 56 through the adhesive layer 57 . In the same way, the obtained multiple chips are arranged in an array and bonded to the carrier substrate 56 at intervals. Please also refer to the cross-sectional view of a chip array structure shown in FIG. 5K .

Wherein, the carrying substrate 56 is used for carrying the molding material to form the molding material. The adhesive layer 57 bonds the conductor post 55 and the carrier substrate 56 to fix the chip.

Step S3: forming the plastic encapsulation material 58 that fully wraps the chip. It should be understood that there is a gap between the conductor post 55 and the carrier substrate 56 , and the plastic encapsulation material 58 can fill the gap between the conductor post 55 and the carrier substrate 56 , and the conductor post penetrates the plastic encapsulation material 58 , thereby fully encapsulating the chip. Please also refer to Figure 5L.

Wherein, the material of the plastic sealing material 58 can be a plastic sealing material, and the plastic sealing material is epoxy resin, polyethylene, polypropylene, polyolefin, polyamide, polyurethane and the like. For example, epoxy molding compound (Epoxy Molding Compound, EMC). EMC uses epoxy resin as the base resin, phenolic resin as the curing agent, and some auxiliary additives, such as fillers, flame retardants, colorants, coupling agents, etc. Under the action of heat and curing agent, the epoxy group of the epoxy resin reacts chemically with the phenolic resin to produce cross-linking and curing to make it a thermosetting plastic.

Specifically, the low-viscosity plastic sealing material is poured on the second surface of the carrier substrate 56 and the chip, and the plastic sealing material fills the gap between the first surface of the chip and the carrier substrate 56, and wraps the chip. When the thickness of the plastic sealing material reaches the preset After thickness, the molding material is heated and cured to form the molding material 58 .

It should be understood that the thinner the thickness of the plastic encapsulation material 58 on the surface of the chip, the greater the strength of the plastic encapsulation material 58 in controlling the warpage of the chip. The larger the size of the chip, the greater the degree of its warping deformation. Therefore, it is possible to control the warping deformation of the chip in the chip packaging structure by controlling the thickness of the molding material 58 on the first surface and the second surface of the chip; , to realize the packaging of large-size chips (such as 8mm*8mm chips).

Since the conductor post is usually prepared by coating, its height can be precisely controlled. By controlling the height of the conductor posts, the thickness of the plastic encapsulation material on the first surface of the chip can be precisely controlled, so as to obtain a chip packaged with a specific thickness of the plastic encapsulation material.

Step S4 : cutting the molding material 58 based on the gap before the chips and removing the carrier substrate 56 to obtain multiple chip packaging structures. Please also refer to the chip package structure shown in FIGS. 5M-5O.

Optionally, after steps S3, S4 or in addition to carrying the substrate 56, the method further includes: step S31, forming solder balls 59 on the second ends of the conductor columns 55, that is, ball planting, so that the chip is electrically connected to the outside through the solder balls 59. circuit. The solder balls 59 obtained by this method are located outside the plastic encapsulation material 58, which does not restrict the free melting and solidification process of the solder alloy during high-temperature soldering of the solder balls 59, and improves the firmness of the soldering between the chip and the external circuit.

Optionally, after S4, surface treatment processes such as Organic Solderability Preservatives (OSP), Electroless Nickel/Immersion Gold (ENIG), and electroless tin plating may also be performed on the conductive pillars 111 .

The carrier substrate 56 can be removed first and then cut, or the carrier substrate 56 can be cut first and then removed. The embodiment of the present application is described by taking the carrier substrate 56 first removed, ball planting and then cutting as an example.

After the adhesive layer 57 and the carrier substrate 56 are removed, a chip package structure as shown in FIG. 5M is obtained; when solder balls 59 are formed on the end faces of the conductor posts 55, a chip package structure as shown in FIG. 5N is obtained; The chip package structure shown in FIG. 5O is obtained after cutting the molding material 58 in the gap.

It can be seen that in the chip packaging method provided by the embodiment of the present application, by providing a plurality of chips, the first surface of the chip is provided with a conductive post, the first end of the conductive post is coupled to the internal circuit of the chip, and the second end of the conductive post is connected to the internal circuit of the chip. When the chip is coupled to the external circuit, the end surface of the second end of the conductor post is higher than the first surface, and the chip is bonded to the carrier substrate through the second end of the conductor post. There is a gap between the conductor post and the carrier substrate, and the plastic packaging material can fill the conductor. The gap between the pillar and the carrier substrate, and then fully wrap the chip. The plastic packaging material that fully wraps the chip can not only protect the surface of the chip, but also balance the stress between the chip and the plastic packaging material in all directions, thereby preventing the chip from being in a certain direction. Problems such as chip cracking and chipping caused by excessive stress can improve the long-term reliability of the packaged chip structure.

Moreover, the one-time molding of the plastic packaging material that fully wraps the chip can avoid the interface between the plastic packaging materials formed multiple times in the prior art, thereby preventing external water vapor from entering the chip through the interface and causing the chip to fail, and improving the performance of the plastic packaging material. Form the airtightness of the plastic package structure and improve the long-term reliability of the chip.

Further, since the plastic sealing material formed after curing has strong mechanical strength, it can withstand the pressure of the test.

Further, in the prior art, a large amount of process glue is used in the chip packaging structure, and part of the process glue permanently exists in the obtained chip packaging structure. Due to the different thermal expansion coefficients of semiconductor materials, plastic packaging materials, and adhesive materials, the adhesive material will cause stress on the chip in an environment where the temperature changes, and then cause deformation of the chip. The chip packaging structure obtained by this chip packaging method does not contain process glue. , can avoid the impact of the process adhesive on the chip, and further improve the long-term reliability of the packaged chip structure.

The above-mentioned chip packaging structure or the chip prepared by the chip packaging method can be further applied to integrated circuits. Please refer to FIG. 6. FIG. 6 is a schematic structural diagram of an integrated circuit provided by an embodiment of the present application. The integrated circuit includes: a substrate 61 and a chip 62, the chip 62 is fully wrapped by a plastic packaging material 63, and a conductor is arranged on the chip 62. pillar 621, the conductor pillar 621 passes through the molding material 63, the chip 62 is supported on the substrate 61, the first end of the conductor pillar 621 is coupled to the internal circuit of the chip 62, and the second end of the conductor pillar 621 is coupled to the substrate 61 circuit.

Optionally, the chip 62 may be disposed on the upper surface of the substrate 61 (as shown in FIG. 6 ), or hung on the lower surface of the substrate 61, which is not limited in this embodiment of the present application. It can be understood that a circuit is provided on the substrate 61, and other chips may also be integrated to enhance the function of the integrated circuit.

Wherein, the chip packaging structure formed by the plastic packaging material 63 and the chip 62 can be any one of the above-mentioned chip packaging structures. Please refer to the related descriptions in the embodiments of the above-mentioned chip packaging structure in FIG. 1 and FIG. For example, the chip 62 shown in FIG. 6 is a pre-packaged chip, and the chip 62 includes a conductor post 621 , a bare chip 622 , a first insulating layer 623 , a redistribution layer 624 and a second insulating layer 625 . Regarding the positional relationship of the conductor post 621, the bare chip 622, the first insulating layer 623, the rewiring layer 624, and the second insulating layer 625, please refer to the above-mentioned figure 1 for the conductor post 111, the bare chip 112, the first insulating layer 113, the rewiring layer 625, and The relevant description of the wiring layer 114 and the second insulating layer 115 will not be repeated in this embodiment of the present application.

Usually, the conductor posts 621 of the chip 62 or the solder balls on the conductor posts 621 can be directly soldered to the circuit of the substrate 61 or connected through a wire bonding process, so as to realize the coupling between the internal circuit in the chip 62 and the circuit on the substrate 61 .

In a specific implementation, the integrated circuit may be integrated with a central processing unit (central processing unit, CPU), a memory, and the like.

The chips or integrated circuits formed by the above-mentioned chip packaging structure and chip packaging method can be further applied to integrated circuit devices. Please refer to FIG. 7. FIG. 7 is a schematic structural diagram of an integrated circuit device provided in an embodiment of the present application. The integrated circuit device includes an integrated circuit 71. The integrated circuit 71 may be the integrated circuit shown in FIG. 6. For details, refer to FIG. The relevant descriptions in the integrated circuit described in 6 will not be repeated in this embodiment of the present application.

In a specific implementation, the integrated circuit 71 may be integrated with a CPU, a memory, and the like. Optionally, the integrated circuit device may also include a power management module 72 for supplying power to the integrated circuit 71 . Optionally, the integrated circuit device may further include a communication module 73, an input module 74 and/or an output module 75, and the like. Among them, the communication module 73 is used to realize the communication connection between the integrated circuit device and other devices or the Internet; the input module 74 is used to realize the user to input information to the integrated circuit device, which may include a touch panel, a keyboard, a camera, etc.; the output module 75 It is used to implement the integrated circuit device to output information to the user, and may include a display panel and the like. It should be understood that the power management module 72, the communication module 73, the input module 74 and/or the output module 75 are not necessary components of the integrated circuit device; the power management module 72, the communication module 73, the input module 74 and/or the output module 75 can also be It is integrated in the integrated circuit 71, or provided separately, and coupled to the integrated circuit 71, which is not limited in this embodiment of the present application.

The integrated circuit device in the embodiment of the present application may be an electronic device including an integrated circuit 71, such as a smart phone, a tablet computer, a personal digital assistant, an e-book, a computer, a server, a smart bracelet, a virtual reality (Virtual Reality, VR) device, an enhanced Reality (Augmented Reality, referred to as AR) equipment, digital TV, set-top box, etc. It should be understood that the electronic devices listed here are only illustrative, and the present application does not limit them.

Cross-references can be made between the above different embodiments. For example, when an embodiment briefly describes the technical details of a certain aspect, further reference may be made to the introduction of other embodiments.

It should be understood that, in various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the order of execution, and the execution order of the processes should be determined by their functions and internal logic, and should not be used in the embodiments of the present application. The implementation process constitutes any limitation.

It should also be understood that the various embodiments of the chip packaging method listed above can be performed by robots or numerical control machining, and the equipment software or process used to perform the chip packaging method can be implemented by executing the computer program code stored in the memory. Chip packaging method.

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. Should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (16)

1. A chip packaging structure, characterized in that it comprises: a chip and a plastic packaging material that fully wraps the chip, the chip is provided with a conductor column, the conductor column passes through the plastic packaging material, and the conductor column The first end is coupled to the internal circuit of the chip, and the second end of the conductive post is used for coupling the external circuit of the chip; The chips include: bare chip; a first insulating layer, the first insulating layer covers the bare chip; A rewiring layer, the rewiring layer is provided on the surface of the first insulating layer facing away from the bare chip, and fills the first via hole penetrating through the first insulating layer, and is coupled to the internal circuit of the bare chip ; a second insulating layer, the second insulating layer covers the first insulating layer and partially covers the rewiring layer, and opens a second via hole for exposing part of the rewiring layer; The conductor column fills the second via hole, the first end of the conductor column is coupled to the internal circuit of the bare chip, and the end face of the second end of the conductor column is higher than the second insulating layer facing away from the surface of the die. 2 . The chip package structure according to claim 1 , wherein the plastic encapsulation material forms an integral molding structure. 3 . 3. The chip packaging structure according to claim 1 or 2, wherein the outer surface of the molding material is flush with the end surface of the second end of the conductive post. 4 . The chip package structure according to claim 3 , further comprising: solder balls disposed on the second ends of the conductor posts. 5. The chip packaging structure according to claim 1, wherein the surface of the bare chip includes one or more passive devices. 6. The chip packaging structure according to claim 5, wherein the thickness of the first insulating layer is 20um-120um. 7. An integrated circuit device, comprising a substrate and a chip, the chip is fully wrapped by a plastic packaging material, the chip is provided with a conductor column, the conductor column passes through the plastic packaging material, and the chip is supported on the substrate On, the first end of the conductor post is coupled to the internal circuit of the chip, and the second end of the conductor post is coupled to the circuit on the substrate; Wherein, the chip includes: bare chip; a first insulating layer, the first insulating layer covers the bare chip; A rewiring layer, the rewiring layer is provided on the surface of the first insulating layer facing away from the bare chip, and fills the first via hole penetrating through the first insulating layer, and is coupled to the inside of the bare chip circuit; a second insulating layer, the second insulating layer covers the first insulating layer and partially covers the rewiring layer, and opens a second via hole for exposing part of the rewiring layer; The conductor column fills the second via hole, the first end of the conductor column is coupled to the internal circuit of the bare chip, and the end surface of the second end of the conductor column is higher than the second insulating layer and faces away from the bare chip. chip surface. 8. The integrated circuit device as claimed in claim 7, wherein the molding material forms an integral molding structure. 9. The integrated circuit device according to claim 7 or 8, wherein an outer surface of the molding material is flush with an end surface of the second end of the conductive post. 10. The integrated circuit device according to claim 7 or 8, wherein solder balls are provided on the second ends of the conductor posts, and the solder balls are used for direct soldering with the circuit on the substrate or through wire soldering. 11. The integrated circuit device of claim 7, wherein a surface of the die includes one or more passive devices. 12. The integrated circuit device according to claim 11, wherein the thickness of the first insulating layer is 20um-120um. 13. A chip packaging method, characterized in that, comprising: Provide a plurality of chips, the first surface of the chip is provided with a conductor column, the first end of the conductor column is coupled to the internal circuit of the chip, and the second end of the conductor column is used for the coupling of the chip external circuit; Bonding the second end of the conductor post on the carrier substrate to fix the chips on the carrier substrate, with gaps between adjacent chips; forming a plastic encapsulation material that fully wraps the chip; cutting the molding compound based on the gap and removing the carrier substrate to obtain a plurality of chip packaging structures; Among them, each chip includes: bare chip; a first insulating layer, the first insulating layer covers the bare chip; A rewiring layer, the rewiring layer is provided on the surface of the first insulating layer facing away from the bare chip, and fills the first via hole penetrating through the first insulating layer, and is coupled to the inside of the bare chip circuit; a second insulating layer, the second insulating layer covers the first insulating layer and partially covers the rewiring layer, and opens a second via hole for exposing part of the rewiring layer; The conductor column fills the second via hole, the first end of the conductor column is coupled to the internal circuit of the bare chip, and the end surface of the second end of the conductor column is higher than the second insulating layer and faces away from the bare chip. chip surface. 14. The method according to claim 13, further comprising: forming a solder ball on the second end of the conductor post after the removal of the carrier substrate, so that the chip passes through the The solder balls are coupled to the external circuit. 15. The method according to claim 13 or 14, wherein said providing a plurality of chips comprises: providing a wafer comprising a plurality of die; forming a first insulating layer covering the plurality of bare chips on the surface of the wafer; Opening a first via hole on the first insulating layer, the first via hole is used to expose the signal connection end of the bare chip, and the signal connection end is used to couple the bare chip to an external circuit; forming the rewiring layer on the surface of the first insulating layer facing away from the wafer, the rewiring layer filling the first via hole and connecting to the signal connection end; forming the second insulating layer covering the redistribution layer and the first insulating layer; Opening a second via hole on the second insulating layer, the second via hole is used to partially expose the redistribution layer; forming the conductor column filling the second via hole, the first end of the conductor column is electrically connected to the internal circuit of the bare chip, and the end face of the second end of the conductor column is higher than the second insulating layer a surface facing away from the die; cutting the first insulating layer, the second insulating layer and the wafer to obtain chips corresponding to the plurality of bare chips one by one. 16. The method according to claim 15, wherein the bare chip further includes a passive element electrically connected to the bare chip, and the surface of the wafer is formed to cover the plurality of bare chips. The first insulating layer consists of: placing a dry film of a first material on the wafer; The dry film is heated to cure to form the first insulating layer.

Images