CN112309979A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0158—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including FinFETs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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- H—ELECTRICITY
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/834—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] comprising FinFETs
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Abstract
一种半导体结构及其形成方法，形成方法包括：提供基底，包括器件区以及与器件区相邻的隔离区，器件区用于形成器件鳍部；在基底的器件区上形成第一掩膜层，在基底的隔离区上形成第二掩膜层；以第一掩膜层和第二掩膜层为掩膜刻蚀基底，形成初始衬底和顶部鳍部；去除第二掩膜层，去除第二掩膜层后，第一掩膜层作为鳍部掩膜层；以鳍部掩膜层和隔离区的顶部鳍部为掩膜刻蚀初始衬底，形成衬底、凸出于隔离区衬底的伪鳍部、以及位于器件区顶部鳍部和衬底之间的底部鳍部，底部鳍部和顶部鳍部构成器件鳍部。刻蚀初始衬底时还刻蚀隔离区的顶部鳍部，因此伪鳍部的顶部表面低于底部鳍部的顶部表面，实现鳍切，与采用掩膜进行鳍切的方案相比，增大了工艺窗口。
A semiconductor structure and a method for forming the same, the forming method includes: providing a substrate, including a device region and an isolation region adjacent to the device region, the device region is used to form a device fin; forming a first mask layer on the device region of the substrate , form a second mask layer on the isolation area of the substrate; use the first mask layer and the second mask layer as masks to etch the substrate to form an initial substrate and a top fin; remove the second mask layer, remove After the second mask layer, the first mask layer is used as the fin mask layer; the initial substrate is etched with the fin mask layer and the top fin of the isolation region as the mask to form a substrate, protruding from the isolation region The dummy fins of the substrate, and the bottom fins located between the top fins of the device region and the substrate, the bottom fins and the top fins constitute the device fins. The top fin of the isolation region is also etched when the initial substrate is etched, so the top surface of the dummy fin is lower than the top surface of the bottom fin to realize fin cutting. Compared with the scheme of using a mask for fin cutting, the increase process window.
Description
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
In semiconductor manufacturing, integrated circuit feature sizes continue to decrease with the trend toward very large scale integrated circuits. To accommodate the reduction in feature size, the channel length of MOSFETs has also been correspondingly shortened. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the controllability of the gate to the channel is deteriorated, the difficulty of the gate voltage to pinch off the channel is increased, and the sub-threshold leakage (SCE), which is a so-called short-channel effect, is more likely to occur.
Therefore, in order to better accommodate the reduction of feature sizes, semiconductor processing is gradually beginning to transition from planar MOSFETs to three-dimensional transistors with higher power efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate structure can control the ultrathin body (fin part) at least from two sides, and compared with a planar MOSFET, the gate structure has stronger control capability on a channel and can well inhibit a short-channel effect; and finfets have better compatibility with existing integrated circuit fabrication relative to other devices.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which improve the performance of the semiconductor structure.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a device region and an isolation region adjacent to the device region, and the device region is used for forming a device fin part; forming a first mask layer on the device region of the substrate, and forming a second mask layer on the isolation region of the substrate; etching the substrate with partial thickness by taking the first mask layer and the second mask layer as masks to form an initial substrate and a top fin part protruding out of the initial substrate; after the top fin part is formed, removing the second mask layer, and taking the first mask layer as a fin part mask layer after the second mask layer is removed; and etching the initial substrate with partial thickness by taking the fin mask layer and the top fin part of the isolation region as masks to form a substrate, a pseudo fin part protruding out of the substrate of the isolation region and a bottom fin part positioned between the top fin part of the device region and the substrate, wherein the bottom fin part and the top fin part of the device region form a device fin part.
Optionally, after the first mask layer and the second mask layer are formed, the top surface of the second mask layer is lower than the top surface of the first mask layer; the method for forming the semiconductor structure further comprises the following steps: and in the process of removing the second mask layer, removing the first mask layer with a part of height, wherein the rest first mask layer is used as the fin mask layer.
Optionally, the step of forming the first mask layer and the second mask layer includes: forming a core layer on the substrate; forming a mask side wall on the side wall of the core layer, wherein the mask side wall positioned in the device region is used as the first mask layer; removing the mask side wall with partial height in the isolation region, wherein the rest mask side wall positioned in the isolation region is used as the second mask layer; and removing the mask side wall of the isolation region with partial height, and then removing the core layer.
Optionally, the step of removing the mask sidewall of the isolation region with a partial height includes: forming a shielding layer on the substrate, wherein the shielding layer covers the first mask layer and exposes the mask side wall positioned in the isolation region; etching the mask side wall with partial height in the isolation region by taking the shielding layer as a mask; and removing the shielding layer.
Optionally, the step of forming a mask sidewall on the sidewall of the core layer includes: forming a sidewall film conformally covering the core layer and the substrate; and removing the side wall film on the substrate and on the top of the core layer, and reserving the side wall film on the side wall of the core layer as the mask side wall.
Optionally, an anisotropic etching process is used to remove the mask sidewall with a part of height in the isolation region.
Optionally, after the first mask layer and the second mask layer are formed, the height of the second mask layer is 1/4 to 1/2 of the height of the first mask layer.
Optionally, in the step of forming the first mask layer on the substrate in the device region, the height of the first mask layer is 20nm to 50 nm.
Optionally, in the step of forming the top fin portion, a height of the top fin portion is greater than or equal to an effective height of the device fin portion.
Optionally, the height of the top fin portion is 1 to 1.5 times the effective height of the device fin portion.
Optionally, an anisotropic etching process is used to remove the second mask layer and the first mask layer with a partial height.
Optionally, the anisotropic etching process is an anisotropic dry etching process.
Optionally, the material of any one of the first mask layer and the second mask layer includes one or more of silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride.
Optionally, the material of the core layer is amorphous silicon or amorphous carbon.
Optionally, after forming the device fin portion, the method further includes: and forming an isolation structure on the substrate with the exposed device fin portion, wherein the isolation structure covers the pseudo fin portion, and the top surface of the isolation structure is lower than that of the device fin portion.
Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: the semiconductor device comprises an initial substrate, a first isolation region and a second isolation region, wherein the initial substrate comprises a device region and the isolation region adjacent to the device region, and the device region is used for forming a device fin part; the top fin part is respectively positioned on the device region and the isolation region of the initial substrate, and the material of the top fin part is the same as that of the initial substrate; and the fin part mask layer is positioned at the top of the top fin part of the device area.
Optionally, the height of the top fin is greater than or equal to the effective height of the device fin.
Optionally, the height of the top fin portion is 1 to 1.5 times the effective height of the device fin portion.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the method for forming the semiconductor structure provided by the technical scheme of the embodiment of the invention, after a first mask layer is formed on a substrate of a device region and a second mask layer is formed on the substrate of an isolation region, the first mask layer and the second mask layer are used as masks, the substrate with partial thickness is etched to form an initial substrate and a top fin part protruding out of the initial substrate, then the second mask layer is removed, and after the second mask layer is removed, the first mask layer is used as a fin part mask layer, and correspondingly, when the initial substrate with partial thickness is etched, the fin part mask layer and the top fin part of the isolation region are used as masks; the top Fin portion and the initial substrate are made of the same material, the top Fin portion of the isolation region is correspondingly etched while the initial substrate exposed out of the top Fin portion is etched, after the top Fin portion of the isolation region is completely removed, the initial substrate material below the top Fin portion of the isolation region is further etched, therefore, after a pseudo Fin portion (dummy Fin) and a bottom Fin portion are formed, the top of the pseudo Fin portion is lower than the top of the bottom Fin portion, so that a Fin cutting (Fin Cut) process effect is achieved, compared with a scheme of directly adopting a mask (mask) to perform Fin cutting, a process window is increased, the Fin cutting effect is guaranteed, damage to the device Fin portion can be reduced, and performance of a semiconductor structure is improved.
Drawings
Fig. 1 to 3 are schematic structural diagrams corresponding to respective steps in a method for forming a semiconductor structure;
fig. 4 to 13 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
At present, the performance of the semiconductor structure still needs to be improved. Now, with a method for forming a semiconductor structure, taking a post fin Cut (Cut Last) process in a fin cutting process as an example, the reason for the performance of the semiconductor structure still needs to be improved is analyzed.
Fig. 1 to fig. 3 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure.
Referring to fig. 1, a substrate 10 and a fin (not labeled) protruding from the substrate 10 are formed, the fin including a device fin 12 for forming a device and a dummy fin 11 to be etched.
Referring to fig. 2, a mask layer 20 is formed on the substrate 10, and the mask layer 20 covers the device fin 12 and exposes the dummy fin 11.
Referring to fig. 3, the dummy fin 11 is etched using the mask layer 20 as a mask.
However, as the feature size is reduced, the spacing (space) between adjacent fins is also continuously reduced, which correspondingly reduces the process window of the fin-cutting process, thereby affecting the effectiveness of the fin-cutting process.
For example: under the influence of depth of focus (DOF) or alignment shift (overlay shift) in the photolithography process, on one hand, the mask layer 20 is likely to cover a part of the dummy fin 11, so that fence (nonce) defects are generated due to the fact that a part of the dummy fin 11 is not etched, and the nonce defects are generated, so that the subsequently formed isolation structure cannot completely cover the remaining dummy fin 11, thereby affecting the electrical isolation effect of the isolation structure, and causing the dummy fin 11 exposed out of the isolation structure to form an unnecessary device, and in addition, the presence of the nonce defects also increases noise in the substrate 10. On the other hand, the mask layer 20 is likely to expose a part of the device fin 12, so that the device fin 12 is damaged by etching.
Both of these conditions result in a degradation of the performance of the semiconductor structure.
Moreover, during the etching of the dummy fin 11, the substrate 10 is also easily damaged, thereby further deteriorating the performance of the semiconductor structure.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: the substrate comprises a device region and an isolation region adjacent to the device region, wherein the device region is used for forming a device fin part; forming a first mask layer on the device region of the substrate, and forming a second mask layer on the isolation region of the substrate; etching the substrate with partial thickness by taking the first mask layer and the second mask layer as masks to form an initial substrate and a top fin part protruding out of the initial substrate; after the top fin part is formed, removing the second mask layer, and taking the first mask layer as a fin part mask layer after the second mask layer is removed; and etching the initial substrate with partial thickness by taking the fin mask layer and the top fin part of the isolation region as masks to form a substrate, a pseudo fin part protruding out of the substrate of the isolation region and a bottom fin part positioned between the top fin part of the device region and the substrate, wherein the bottom fin part and the top fin part of the device region form a device fin part.
In the embodiment of the invention, the first mask layer and the second mask layer are used as masks, the substrate with partial thickness is etched to form an initial substrate and a top fin part protruding out of the initial substrate, then the second mask layer is removed, and after the second mask layer is removed, the first mask layer is used as a fin part mask layer; the top fin portion and the initial substrate are made of the same material, the top fin portion of the isolation region is correspondingly etched while the initial substrate exposed by the top fin portion is etched, after the top fin portion of the isolation region is completely removed, the initial substrate material below the top fin portion of the isolation region is further etched, therefore, after the pseudo fin portion and the bottom fin portion are formed, the top of the pseudo fin portion is lower than the top of the bottom fin portion to achieve the fin cutting process effect, compared with a scheme of directly adopting a mask to perform fin cutting, the process window is increased, the fin cutting effect is guaranteed, damage to the device fin portion can be reduced, and performance of a semiconductor structure is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 13 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 4, a substrate 100 is provided, where the substrate 100 includes a device region 100a and an isolation region 100b adjacent to the device region 100a, and the device region 100a is used to form a device fin.
The base 100 is used to prepare a substrate for subsequent formation and a device fin protruding from the substrate.
In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate may also be germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or other materials, and the substrate may also be a silicon-on-insulator substrate or another type of substrate such as a germanium-on-insulator substrate.
In this embodiment, the substrate 100 is an integrated structure. In other embodiments, the substrate may also include a first semiconductor layer and a second semiconductor layer epitaxially grown on the first semiconductor layer, where the first semiconductor layer is used as a substrate, and the second semiconductor layer is used to form a device fin.
Referring to fig. 9, a first mask layer 202 is formed on the device region 100a of the substrate 100, and a second mask layer 201 is formed on the isolation region 100b of the substrate 100.
The subsequent process includes etching a part of the thickness of the substrate 100, and the first mask layer 202 and the second mask layer 201 are used as masks of the etching process.
In this embodiment, after the first mask layer 202 and the second mask layer 201 are formed, the top surface of the second mask layer 201 is lower than the top surface of the first mask layer 202.
And after the base 100 with the partial thickness is etched subsequently, the residual base 100 is used as an initial substrate, and the step of removing the second mask layer 201 is further included after the base 100 with the partial thickness is etched. By making the top surface of the second mask layer 201 lower than the top surface of the first mask layer 202, the second mask layer 201 can be removed by maskless etching to reduce the process complexity. Moreover, while the second mask layer 201 is removed by a maskless etching method, the first mask layer 202 with a partial height is removed, the first mask layer 202 still has a partial thickness residue, and the remaining first mask layer 202 can be used as a mask for subsequent etching of the initial substrate.
It should be noted that after the second mask layer 201 is subsequently removed, the remaining first mask layer 202 serves as a fin mask layer, and the fin mask layer serves as a mask for subsequently etching the initial substrate.
Therefore, after the first mask layer 202 and the second mask layer 201 are formed, the height of the first mask layer 202 is not necessarily too small, and is not necessarily too large. If the height of the first mask layer 202 is too small, after the second mask layer 201 is subsequently removed, the remaining first mask layer 202 is easily caused to be too small, that is, the fin mask layer is easily caused to be too small, so that the fin mask layer cannot play a role in etching a mask; if the height of the first mask layer 202 is too large, process costs and time may be wasted, and the difficulty of the subsequent fin mask layer removal process may be increased. For this reason, in the present embodiment, the height of the first mask layer 202 is 20nm to 50 nm.
Accordingly, the height of the second mask layer 201 is 20nm to 50 nm.
It should be noted that, after the first mask layer 202 and the second mask layer 201 are formed, the ratio of the height of the second mask layer 201 to the height of the first mask layer 202 is not small or large. If the ratio is too large, that is, the height difference between the first mask layer 202 and the second mask layer 201 is too small, after the second mask layer 201 is subsequently removed, the remaining first mask layer 202 is easily caused to be too small in height, that is, the fin portion mask layer is easily caused to be too small in height, so that the fin portion mask layer cannot play a role in etching a mask; if the ratio is too small, that is, the height difference between the first mask layer 202 and the second mask layer 201 is too large, the height of the second mask layer 201 is correspondingly too small under the condition that the height of the fin mask layer meets the process requirement, so that the second mask layer 201 cannot perform the function of etching the mask in the process of etching the substrate 100. Therefore, in the embodiment, the height of the second mask layer 201 is 1/4 to 1/2 of the height of the first mask layer 202.
In this embodiment, the device fin is formed by a self-aligned multi-patterning process to increase the density of the device fins formed on the substrate and further reduce the pitch (pitch) between adjacent device fins, so that the limit of the photolithography resolution is overcome by the photolithography process.
As an example, the self-aligned multi-patterning process is a self-aligned double patterning (SADP) process. In other embodiments, the self-aligned multi-patterning process may also be a self-aligned quad patterning (SAQP) process.
The material of any one of the first mask layer 202 and the second mask layer 201 includes one or more of silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride.
The first mask layer 202 and the second mask layer 201 are high in material density and hardness, and in the subsequent process of etching the substrate 100, the material of the substrate 100 and the material of the first mask layer 202 and the material of the second mask layer 201 have high etching selection ratios, so that the first mask layer 202 and the second mask layer 201 can well play a role in etching masks.
In this embodiment, the first mask layer 202 and the second mask layer 201 are made of silicon nitride.
The steps of forming the first mask layer 202 and the second mask layer 201 are specifically described below with reference to fig. 4 to 9.
Referring to fig. 4, a core layer 110 is formed on the substrate 100.
The core layer 110 is used to provide a process foundation for the subsequent formation of the mask sidewall. The mask side wall is used for preparing for forming a first mask layer and a second mask layer.
After the first mask layer and the second mask layer are formed subsequently, the core layer 110 is also removed, so that the core layer 110 is a material which is easy to remove, and the process for removing the core layer 110 has less damage to the first mask layer, the second mask layer and the substrate 100.
For this reason, in the present embodiment, the material of the core layer 110 is amorphous silicon. Amorphous silicon is a commonly used core layer material in the SADP process. In other embodiments, the material of the core layer may also be amorphous carbon.
Referring to fig. 5, a mask sidewall spacer 200 is formed on a sidewall of the core layer 110.
The mask sidewall spacers 200 located in the device region 100a are used as the first mask layer 202, and the mask sidewall spacers 200 located in the isolation region 100b are used to provide a process basis for the subsequent formation of the second mask layer.
Specifically, the step of forming the mask sidewall spacers 200 includes: forming a sidewall film conformally covering the core layer 110 and the substrate 100; the sidewall films on the substrate 100 and on the top of the core layer 110 are removed, and the sidewall films on the sidewalls of the core layer 110 are remained as the mask sidewall 200.
In this embodiment, the sidewall film is formed by an atomic layer deposition process. The atomic layer deposition process is used for forming a thin film by layer deposition in a monoatomic layer form, is usually used for growing the thin film with controllable atomic scale, has stronger gap filling capacity and step covering capacity, is favorable for improving the forming quality and thickness uniformity of the side wall film, reduces the difficulty in controlling the thickness of the side wall film, and is also favorable for improving the conformal covering effect of the side wall film.
In other embodiments, the sidewall film may also be formed using a chemical vapor deposition process.
In this embodiment, an anisotropic etching process is used to etch the sidewall film along a direction perpendicular to the surface of the substrate 100, so that the sidewall film on the sidewall of the core layer 110 can be remained while removing the sidewall film on the substrate 100 and on the top of the core layer 110. Specifically, the anisotropic etching process is an anisotropic dry etching process, which is a low-cost anisotropic etching process.
In this embodiment, the mask sidewall spacer 200 is made of silicon nitride.
Referring to fig. 6 to 8, the mask sidewall spacers 200 (shown in fig. 6) at a partial height of the isolation region 100b are removed, and the remaining mask sidewall spacers 200 located in the isolation region 100b are used as the second mask layer 201 (shown in fig. 7).
The mask sidewall spacers 200 of a portion of the height in the isolation region 100b are removed, so that the top surface of the second mask layer 201 is lower than the top surface of the first mask layer 202.
Specifically, the step of removing the mask sidewall spacers 200 with a partial height in the isolation region 100b includes: forming a shielding layer 210 on the substrate 100, wherein the shielding layer 210 covers the first mask layer 202 and exposes the mask sidewall spacers 200 located in the isolation region 100 b; and etching the mask side wall 200 with a part of height in the isolation region 100b by using the shielding layer 210 as a mask.
The shielding layer 210 functions as an etching mask for protecting the first mask layer 202, thereby preventing the height of the first mask layer 202 from being affected.
The shielding layer 210 may be a single-layer structure or a stacked-layer structure, and the material of the shielding layer 210 is a material commonly used as an etching mask in the semiconductor field.
In this embodiment, the shielding layer 210 is made of photoresist. In other embodiments, the material of the blocking layer may also be a bottom anti-reflective coating material (BARC).
The shielding layer 210 only needs to expose the mask sidewall spacer 200 located in the isolation region 100 b. In this embodiment, in order to increase the process window for forming the shielding layer 210, the shielding layer 210 covers the substrate 100, the first mask layer 202 and the core layer 110 of the device region 100 a.
In this embodiment, an anisotropic etching process is adopted to remove the mask sidewall 200 with a partial height in the isolation region 100b, so that the mask sidewall 200 of the isolation region 100b can be etched in a direction perpendicular to the surface of the substrate 100, and the influence on the width of the mask sidewall 200 of the isolation region 100b is reduced while the height is reduced.
Specifically, the anisotropic etching process is an anisotropic dry etching process.
As shown in fig. 8, in this embodiment, after forming the second mask layer 201, the method further includes: the masking layer 210 is removed (as shown in fig. 7).
By removing the shielding layer 210, preparation is made for the subsequent steps of removing the core layer 110 and etching the substrate 100.
In this embodiment, an ashing process is used to remove the shielding layer 210.
Referring to fig. 9, after removing the shielding layer 210 (as shown in fig. 7), the method further includes: the core layer 110 is removed (as shown in fig. 8).
The core layer 110 is removed to expose a portion of the substrate 100 in preparation for a subsequent step of etching the substrate 100.
In this embodiment, the core layer 110 is removed by etching using a wet etching process. Specifically, the core layer 110 is made of amorphous silicon, and the etching solution adopted by the wet etching process is Cl2And HBr or TMAH solution. In other embodiments, the core layer may be removed by a dry etching process or a combination of dry etching and wet etching.
Referring to fig. 10, the first mask layer 202 and the second mask layer 201 are used as masks, and the base 100 with a certain thickness is etched to form an initial substrate 101 and a top fin 310 protruding from the initial substrate 101.
The top fin 310 of the device region 100a is used as a part of the device fin, and the top fin 310 of the isolation region 100b is used as a mask for subsequent etching of the initial substrate 101.
The subsequent process further includes removing the second mask layer 201, making the remaining first mask layer 202 serve as a fin mask layer, etching the initial substrate 101 with a partial thickness by using the fin mask layer and the top fin 310 of the isolation region 100b as masks after removing the second mask layer 201, forming a substrate, a pseudo fin protruding from the substrate of the isolation region 100b, and a bottom fin located between the top fin 310 of the device region 100a and the substrate, wherein the bottom fin and the top fin 310 of the device region 100a constitute a device fin.
The top fin portion 310 and the initial substrate 101 are made of the same material, the top fin portion 310 of the isolation region 100b is correspondingly etched while the initial substrate 101 exposed out of the top fin portion 310 is etched, and after the top fin portion 310 of the isolation region 100b is completely removed, the initial substrate 101 material below the top fin portion 310 of the isolation region 100b is continuously etched, so that after a pseudo fin portion and a bottom fin portion are formed, the top surface of the pseudo fin portion is lower than the top surface of the bottom fin portion, a fin cutting process effect is achieved.
In this embodiment, the substrate 100 with a certain thickness is etched by using the first mask layer 202 and the second mask layer 201 as masks and using an anisotropic dry etching process. The anisotropic dry etching process has good etching profile controllability, is favorable for improving the flatness of the side wall of the top fin portion 310 by selecting the anisotropic dry etching process, and is easy to control the height of the top fin portion 310.
It should be noted that although the top surface of the second mask layer 201 is lower than the top surface of the first mask layer 202, the substrate 100 and the second mask layer 201 have a higher etching selectivity, so that the first mask layer 202 and the second mask layer 201 can still perform the same function, and accordingly, the substrate 100 of the device region 100a and the isolation region 100b has the same etching effect in this embodiment.
In this embodiment, after the top fin portion 310 is formed, the height of the top fin portion 310 is greater than or equal to the effective height of the device fin portion. The effective height of the device fin refers to the height covered by the gate structure in the device fin, that is, the height exposed by the isolation structure in the device fin.
The height of the top fin portion 310 is greater than or equal to the effective height of the device fin portion, so that after an isolation structure is formed on the substrate subsequently, the top surface of the isolation structure is flush with the bottom surface of the top fin portion 310, or the top surface of the isolation structure is higher than the bottom surface of the top fin portion 310; after the pseudo fin portion and the bottom fin portion are formed in the subsequent process, the top surface of the pseudo fin portion is lower than the top surface of the bottom fin portion, that is, the top surface of the pseudo fin portion is lower than the bottom surface of the top fin portion 310, so that the isolation structure can completely cover the pseudo fin portion, the pseudo fin portion is prevented from affecting the electrical isolation effect of the isolation structure, and the pseudo fin portion can be prevented from being exposed out of the isolation structure to form an unnecessary device.
Moreover, compare with the scheme through one step of etching formation device fin portion, form the required etching time of top fin portion 310 is shorter, consequently, forms in the etching the polymer that the in-process of top fin portion 310 was accumulated is less, the influence of polymer to the etching orbit is less, thereby is favorable to improving the lateral wall straightness that hangs down of top fin portion 310, and then is favorable to improving the controllability of follow-up grid structure to the channel, improves the barrier reduction (DIBL) effect that short channel effect and drain terminal introduced.
However, the ratio of the top fin 310 height to the device fin effective height is also not necessarily too large. If the ratio is too large, the height of the subsequent dummy fin portion is easily too large, so that the possibility that the dummy fin portion is exposed out of the isolation structure is increased, and the performance of the transistor is further adversely affected. To this end, in the present embodiment, the height of the top fin 310 is 1 to 1.5 times the effective height of the device fin.
The height of the top fin portion 310 can meet the process requirement by reasonably adjusting the etching time of the dry etching process.
Referring to fig. 11, after the top fin 310 is formed, the second mask layer 201 is removed (as shown in fig. 10), and after the second mask layer 201 is removed, the first mask layer 202 (as shown in fig. 10) serves as a fin mask layer 205.
After the second mask layer 201 is removed, the top fin portion 310 of the isolation region 100b is exposed, and the top fin portion 310 of the isolation region 100b and the fin portion mask layer 205 are used as masks for etching the initial substrate 101.
As can be seen from the above description, by removing the second mask layer 201, the process window is increased, so that the fin cutting effect is ensured, and meanwhile, the damage to the fin portion of the device is reduced, thereby improving the performance of the semiconductor structure.
In this embodiment, before the second mask layer 201 is removed, the top surface of the second mask layer 201 is lower than the top surface of the first mask layer 202, so that the second mask layer 201 is removed by using a maskless etching process, thereby simplifying the process complexity and reducing the process cost.
Moreover, compared with the scheme of forming a pattern layer (e.g., a photoresist layer) covering the first mask layer and removing the second mask layer by using the pattern layer as a mask, the present embodiment can avoid the influence of the forming process and the removing process of the pattern layer on the top fin portion 310 by making the top surface of the second mask layer 201 lower than the top surface of the first mask layer 202 and by using a maskless etching manner, thereby facilitating the improvement of the quality of the subsequent fin portion and improving the performance of the semiconductor structure.
Correspondingly, in the process of removing the second mask layer 201, the first mask layer 202 with a partial height is also removed, and the remaining first mask layer 202 serves as the fin mask layer 205. Specifically, the amount of height reduction of the first mask layer 202 is equal to the height of the second mask layer 201.
The height of the first mask layer 202 is 20nm to 50nm, and the height of the second mask layer 201 is 1/4 to 1/2 of the height of the first mask layer 202, so that the thickness of the fin mask layer 205 can still meet the process requirements, and the fin mask layer 205 plays a role in etching a mask in the process of etching the initial substrate 101.
In this embodiment, an anisotropic etching process is adopted to remove the second mask layer 201 and the first mask layer 202 with a partial height. By adopting an anisotropic etching process, the second mask layer 201 and the first mask layer 202 with a part of height are etched and removed along a direction perpendicular to the surface of the initial substrate 101, so that the influence on the width of the fin mask layer 205 is reduced.
Specifically, when the second mask layer 201 and the first mask layer 202 with a part of height are removed by etching, the anisotropic etching process is an anisotropic dry etching process.
The second mask layer 201 and the first mask layer 202 have a higher etching selectivity ratio with respect to the initial substrate 101, so that the loss of the initial substrate 101 is less in the process of removing the second mask layer 201 and the first mask layer 202 with a partial height by etching.
It should be noted that, in other embodiments, according to an actual process condition, the mask sidewall of the isolation region may not be etched, and accordingly, after the initial substrate and the top fin portion protruding from the initial substrate are formed, the second mask layer in the isolation region is removed by using a mask (mask).
Referring to fig. 12, the fin mask 205 and the top fin 310 (shown in fig. 11) of the isolation region 100b are used as masks, the initial substrate 101 (shown in fig. 11) is etched by a certain thickness, and a substrate 102, a dummy fin 330 protruding from the substrate 102 of the isolation region 100b, and a bottom fin 320 located between the top fin 310 of the device region 100a and the substrate 102 are formed.
The bottom fin 320 and the top fin 310 of the device region 100a constitute a device fin 300, and the device fin 300 is used to provide a channel of a transistor. Where the dashed lines in fig. 12 are used to indicate the boundaries of the bottom fin 320 and the top fin 310.
As can be seen from the above description, the top fin portion 310 of the isolation region 100b is also etched while the initial substrate 101 exposed by the top fin portion 310 is etched, so that after the dummy fin portion 330 and the bottom fin portion 320 are formed, the top surface of the dummy fin portion 330 is lower than the top surface of the bottom fin portion 320, so as to achieve the fin cutting process effect.
In this embodiment, an anisotropic dry etching process is used to etch the initial substrate 101 with a partial thickness. The anisotropic dry etching process has good etching profile controllability, and is favorable for improving the flatness of the side wall of the bottom fin portion 320 and easily controlling the height of the bottom fin portion 320.
The height of the bottom fin portion 320 can meet the process requirements by reasonably adjusting the etching time of the dry etching process, so that the height of the device fin portion 300 meets the process requirements.
Moreover, compared with the scheme of forming the device Fin portion by one-step etching, the etching time required for forming the bottom Fin portion 320 is also shorter, which is also beneficial to improving the sidewall verticality of the bottom Fin portion 320, so that the sidewall verticality of the device Fin portion 300 is improved, and further the sidewall verticality of the effective Fin portion (effective Fin) is improved, i.e. the difference between the top width and the bottom width of the effective Fin portion is beneficial to reducing, and the performance of the semiconductor structure is beneficial to improving. The active fin refers to a portion of the device fin 300 that is covered by the gate structure.
Referring to fig. 13 in combination, after the device fin portion 300 is formed, the forming method further includes: forming an isolation structure 103 on the substrate 102 exposed by the device fin 300, wherein the isolation structure 103 covers the dummy fin 330, and a top surface of the isolation structure 103 is lower than a top surface of the device fin 300.
The isolation structure 103 serves as a Shallow Trench Isolation (STI) structure for isolating adjacent devices.
In this embodiment, the isolation structure 103 is made of silicon oxide. In other embodiments, the material of the isolation structure may also be other insulating materials such as silicon nitride or silicon oxynitride.
Specifically, the step of forming the isolation structure 103 includes: forming a layer of isolation material on the substrate 102, the layer of isolation material covering the fin masking layer 205 (as shown in fig. 12); removing the isolation material layer higher than the top of the fin mask layer 205 by adopting a planarization process to expose the top of the fin mask layer 205; removing the fin mask layer 205; after the fin mask layer 205 is removed, the remaining isolation material layer is etched back to form the isolation structure 103.
In this embodiment, by the method, the fin cutting process effect is improved, the process window of the fin cutting process is increased, the feng defect is improved, and the probability that the dummy fin portion 330 is exposed out of the isolation structure 103 is reduced, so that the performance of the semiconductor structure is guaranteed.
Correspondingly, the invention also provides a semiconductor structure formed by adopting the forming method. Referring collectively to fig. 11, a schematic structural diagram of an embodiment of a semiconductor structure of the present invention is shown.
The semiconductor structure includes: an initial substrate 101, wherein the initial substrate 101 includes a device region 100a and an isolation region 100b adjacent to the device region 100a, and the device region 100a is used for forming a device fin; a top fin 310 respectively located on the device region 100a and the isolation region 100b of the initial substrate 101, wherein the top fin 310 and the initial substrate 101 are made of the same material; a fin mask layer 205 is on top of the top fin 310 of the device region 100 a.
And etching the initial substrate 101 with a part of thickness by taking the fin mask layer 205 and the top fin 310 of the isolation region 100b as masks to form a substrate, a pseudo fin protruding from the substrate of the isolation region 100b, and a top fin located between the top fin 310 of the device region 100a and the substrate, wherein the top fin 310 and the top fin of the device region 100a form a device fin. Wherein the device fin is to provide a channel of the transistor.
The top fin portion 310 and the initial substrate 101 are made of the same material, the top fin portion 310 of the isolation region 100b is correspondingly etched while the initial substrate 101 exposed out of the top fin portion 310 is etched, and after the top fin portion 310 of the isolation region 100b is completely removed, the initial substrate 101 material below the top fin portion 310 of the isolation region 100b is continuously etched, so that after a pseudo fin portion and a bottom fin portion are formed, the top of the pseudo fin portion is lower than the top of the bottom fin portion, a fin cutting process effect is achieved.
In this embodiment, the initial substrate 101 is made of silicon. In other embodiments, the material of the initial substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the initial substrate may also be other types of bases such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.
In this embodiment, the initial substrate 101 is a unitary structure. In other embodiments, the initial substrate 101 may also include a first semiconductor layer and a second semiconductor layer epitaxially grown on the first semiconductor layer, where the first semiconductor layer is used as a substrate, and the second semiconductor layer is used to form the bottom fin portion.
The top fin 310 of the device region 100a is used as a part of the device fin, and the top fin 310 of the isolation region 100b is used as a mask for etching the initial substrate 101.
In this embodiment, the top fin portion 310 and the initial substrate 101 are formed by etching the same base, so that the top fin portion 310 and the initial substrate 101 are of an integral structure, and the top fin portion 310 and the initial substrate 101 are made of the same material.
In this embodiment, the height of the top fin 310 is greater than or equal to the effective height of the device fin. The effective height of the device fin refers to the height covered by the gate structure in the device fin, that is, the height exposed by the isolation structure in the device fin.
The height of the top fin portion 310 is greater than or equal to the effective height of the device fin portion, so that after an isolation structure is formed on the substrate subsequently, the top surface of the isolation structure is flush with the bottom surface of the top fin portion 310, or the top surface of the isolation structure is higher than the bottom surface of the top fin portion 310; after the pseudo fin portion and the bottom fin portion are formed in the subsequent process, the top surface of the pseudo fin portion is lower than the top surface of the bottom fin portion, that is, the top surface of the pseudo fin portion is lower than the bottom surface of the top fin portion 310, so that the isolation structure can completely cover the pseudo fin portion, the pseudo fin portion is prevented from affecting the electrical isolation effect of the isolation structure, and the pseudo fin portion can be prevented from being exposed out of the isolation structure to form an unnecessary device.
However, the ratio of the top fin 310 height to the device fin effective height is also not necessarily too large. If the ratio is too large, the height of the subsequent pseudo fin portion is easily too large, so that the possibility that the pseudo fin portion is exposed out of the isolation structure is increased, and the performance of the semiconductor structure is further adversely affected. To this end, in the present embodiment, the height of the top fin 310 is 1 to 1.5 times the effective height of the device fin.
The fin mask layer 205 is used as a mask for etching the initial substrate 101.
The fin mask layer 205 may be made of one or more materials selected from the group consisting of silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride.
The fin mask layer 205 has a higher material density and hardness, and in the subsequent etching process of the initial substrate 101, the material of the initial substrate 101 and the material of the fin mask layer 205 have a higher etching selection ratio, so that the fin mask layer 205 can better play a role in etching a mask.
In this embodiment, the fin mask layer 205 is made of silicon nitride.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (19)
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| US20150206759A1 (en) * | 2014-01-21 | 2015-07-23 | United Microelectronics Corp. | Semiconductor structure and manufacturing method thereof |
| US9337050B1 (en) * | 2014-12-05 | 2016-05-10 | Globalfoundries Inc. | Methods of forming fins for finFET semiconductor devices and the selective removal of such fins |
| CN108807534A (en) * | 2017-05-03 | 2018-11-13 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| US20190189519A1 (en) * | 2017-12-19 | 2019-06-20 | International Business Machines Corporation | Methods and structures for forming uniform fins when using hardmask patterns |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20150206759A1 (en) * | 2014-01-21 | 2015-07-23 | United Microelectronics Corp. | Semiconductor structure and manufacturing method thereof |
| US9337050B1 (en) * | 2014-12-05 | 2016-05-10 | Globalfoundries Inc. | Methods of forming fins for finFET semiconductor devices and the selective removal of such fins |
| CN108807534A (en) * | 2017-05-03 | 2018-11-13 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| US20190189519A1 (en) * | 2017-12-19 | 2019-06-20 | International Business Machines Corporation | Methods and structures for forming uniform fins when using hardmask patterns |
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