CN112289765B - Semiconductor package device - Google Patents
Semiconductor package device Download PDFInfo
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- CN112289765B CN112289765B CN202011553044.9A CN202011553044A CN112289765B CN 112289765 B CN112289765 B CN 112289765B CN 202011553044 A CN202011553044 A CN 202011553044A CN 112289765 B CN112289765 B CN 112289765B
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
- H01L23/49551—Cross section geometry characterised by bent parts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49544—Deformation absorbing parts in the lead frame plane, e.g. meanderline shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
An embodiment of the present application provides a semiconductor package device, which includes: the frame carrier comprises a lead frame carrier and a connecting frame carrier which are connected through a smooth curved surface and are distributed in a staggered manner in the thickness direction of the lead frame carrier; a chip disposed on the lead frame carrier; the packaging body wraps the frame carrier and the chip and is provided with a first outer surface and a second outer surface which are opposite to each other; a lead assembly extending along a length direction of the package body, the lead assembly including a plurality of leads connected to the chip and extending outward from the package body; the volume between the first outer surface of the package and the frame carrier is equal to the volume between the frame carrier and the second outer surface of the package. The application has slowed down the injection mould velocity of flow on frame carrier upper portion and has formed the balance with the injection mould velocity of flow of frame carrier lower part, guarantees to discharge from lead wire position department the air in the encapsulation body at the in-process of moulding plastics, has avoided the formation of the pinhole of moulding plastics in the encapsulation body.
Description
Technical Field
The application belongs to the field of semiconductors, and particularly relates to a semiconductor packaging device.
Background
The to (transistor outline) packaging technology refers to a totally enclosed packaging technology, and is a commonly used packaging method for microelectronic devices. Compared with other packaging technologies, the TO package has the advantages of small parasitic parameters, low cost, simple process and flexible and convenient use, and is therefore mainly used for packaging of Liquid Crystal Displays (LCDs) and light receiving devices and components below low frequency. During operation of an Integrated Circuit (IC), the IC chip generates heat, thereby heating the entire electronic device package containing the chip. As the performance of IC chips decreases with increasing temperature and the structural integrity of the electronic device package decreases due to high thermal stresses, this heat must be dissipated.
Generally, a small gap is left between the leads and the package substrate in view of heat dissipation, thereby ensuring heat dissipation and insulation of the electronic device package.
However, the above gap affects the overall performance of the electronic device package, such as insulation.
Disclosure of Invention
In view of one or more of the problems described above, embodiments of the present application provide a semiconductor package device.
The embodiment of the application provides a semiconductor packaging device, which comprises a frame carrier, a plurality of lead frame carriers and a plurality of connecting frame carriers, wherein the lead frame carriers and the connecting frame carriers are connected through a smooth curved surface and are distributed in a staggered manner in the thickness direction of the lead frame carriers; a chip disposed on the lead frame carrier; the packaging body wraps the frame carrier and the chip and is provided with a first outer surface and a second outer surface which are opposite to each other; a lead assembly extending along a length direction of the package body, the lead assembly including a plurality of leads connected to the chip and extending outward from the package body; the volume between the first outer surface of the package and the frame carrier is equal to the volume between the frame carrier and the second outer surface of the package.
In an alternative embodiment, the first outer surface of the package body comprises a first horizontal surface, an inclined surface and a second horizontal surface which are connected, and a step is formed between the first horizontal surface and the second horizontal surface.
In an optional embodiment, the smooth curved surfaces include at least one arc-shaped curved surface, and an inner arc surface of the arc-shaped curved surface faces the second outer surface of the package body; the projection of the arc-shaped curved surface on the first horizontal plane of the packaging body is overlapped with the projection of the inclined plane on the first horizontal plane of the packaging body.
In an alternative embodiment, the distance between the leadframe carrier and the second outer surface of the package body is 0.3 mm-0.5 mm.
In an alternative embodiment, the lead assembly further comprises a lead bond, one end of the lead bond being connected to the lead and the other end being connected to the chip.
In an alternative embodiment, the connection frame carrier has a connection opening for connection to the component to be mounted.
In an optional embodiment, the internal circuit assembly further comprises a device layer, the device layer being located on the frame carrier, the chip being located on the device layer.
In an alternative embodiment, the wire bond and the wire are connected by a wire bonding or soldering connection.
In an alternative embodiment, the leads include power leads or signal leads.
In an alternative embodiment, at least one of the leads is coated with a flange, the flange being located adjacent to an outer surface of the package body.
The semiconductor packaging device provided by the embodiment of the application comprises the lead frame carriers and the connecting frame carriers which are connected through the smooth curved surfaces and are distributed in a staggered manner in the thickness direction of the semiconductor packaging device, and the semiconductor packaging device is connected with the to-be-mounted part through the connecting frame carriers, so that the mounting strength of the packaging device is improved; by arranging the smooth curved surface, the volume between the first outer surface of the packaging body and the frame carrier is equal to the volume between the frame carrier and the second outer surface of the packaging body, so that when the electronic device packaging is subjected to injection molding packaging, the injection molding time between the first outer surface of the packaging body and the frame carrier is balanced with the injection molding time between the frame carrier and the second outer surface of the packaging body, the injection molding flow speed of the upper part of the frame carrier is reduced, the injection molding flow speed of the lower part of the frame carrier is balanced, the air in the packaging body is discharged from the lead position in the injection molding process, and the formation of injection molding pinholes in the packaging body is avoided.
Drawings
The embodiments of the present application may be better understood from the following description of specific embodiments thereof taken in conjunction with the accompanying drawings, in which:
fig. 1 is a schematic structural diagram of a semiconductor package device according to an embodiment of the present disclosure;
fig. 2 is a schematic view of a frame carrier structure of the semiconductor package device shown in fig. 1.
Reference numerals:
1-frame carrier, 101-connection hole, 11-lead frame carrier, 12-connection frame carrier, 2-chip, 3-package, 301-first outer surface, 302-second outer surface, 31-first horizontal surface, 32-inclined surface, 33-second horizontal surface, 4-lead.
Detailed Description
Features and exemplary embodiments of various aspects of the present application will be described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof. The present application is in no way limited to any specific configuration and algorithm set forth below, but rather covers any modification, replacement or improvement of elements, components or algorithms without departing from the spirit of the present application. In the drawings and the following description, well-known structures and techniques are not shown in order to avoid unnecessarily obscuring the present application.
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art; in the drawings, the thickness of regions and layers may be exaggerated for clarity. The same reference numerals denote the same or similar structures in the drawings, and thus detailed descriptions thereof will be omitted.
Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to provide a thorough understanding of embodiments of the application. One skilled in the relevant art will recognize, however, that the subject matter of the present application can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring major technical ideas of the application.
Because of the packaging design of the TO-220F packaging device, the TO-220F packaging device needs TO be fully sealed and insulated, and the lead assembly and the frame carrier are completely packaged by the packaging body 3, but the heat dissipation problem of the TO-220F packaging device needs TO be considered, so a certain gap needs TO be ensured between the frame carrier and the second outer surface 302 of the packaging body 3, but the gap can cause that the injection flow rate between the frame carrier and the second outer surface 302 of the packaging body 3 during injection molding is much slower than that between a connecting frame and the first outer surface 301 of the packaging body 3 during injection molding, the frame carrier and the second outer surface 302 of the packaging body 3 are finally packaged, air cannot be exhausted, and the pin hole problem of the finally formed packaging device occurs; in view of the above, embodiments of the present application provide a semiconductor package device, which aims to solve the above technical problems.
Referring to fig. 1 and fig. 2, fig. 1 is a schematic structural diagram of a semiconductor package device according to an embodiment of the present disclosure; fig. 2 is a schematic view of a frame carrier structure of the semiconductor package device shown in fig. 1. An embodiment of the present application provides a semiconductor package device, including: a frame carrier 1, a chip 2, a package body 3, and a lead assembly; the frame carrier 1 comprises a lead frame carrier 11 and a connecting frame carrier 12 which are connected through a smooth curved surface and are distributed in a staggered manner in the thickness direction of the frame carrier; the chip 2 is arranged on the lead frame carrier 11; the package 3 is arranged to cover the frame carrier and the chip 2, and the package 3 has a first outer surface 301 and a second outer surface 302 opposite to each other; the lead assembly extends along the length direction of the package body 3, and comprises a plurality of leads 4 connected with the chip 2 and extending outwards from the package body 3; the volume between the first outer surface 301 of the encapsulation 3 and the frame carrier 1 is equal to the volume between the frame carrier 1 and the second outer surface 302 of the encapsulation 3.
According to the semiconductor packaging device provided by the embodiment of the application, the frame carrier 1 comprises the lead frame carrier 11 and the connecting frame carrier 12 which are connected through the smooth curved surface and are distributed in a staggered manner in the thickness direction of the frame carrier, and the connecting frame carrier 12 is connected with the to-be-mounted part, so that the mounting strength of the packaging device is improved; by arranging the smooth curved surface, and the volume between the first outer surface 301 of the package body 3 and the frame carrier 1 is equal to the volume between the frame carrier and the second outer surface 302 of the package body 3, it is ensured that when the electronic device package is subjected to injection molding packaging, the injection molding time between the first outer surface 301 of the package body 3 and the frame carrier 1 is balanced with the injection molding time between the frame carrier and the second outer surface 302 of the package body 3, so that the injection molding flow speed at the upper part of the frame carrier 1 is slowed down and balanced with the injection molding flow speed at the lower part of the frame carrier 1, it is ensured that air in the package body 3 is discharged from the position of the lead 4 in the injection molding process, and the formation of an injection molding pinhole in the package body 3 is avoided.
It should be noted that, resin is injected into the mold during manufacturing of the semiconductor package device provided in the embodiment of the present application, since the smooth curved surface is provided in the present application, not only the gap between the frame carrier 1 and the second outer surface 302 of the package body 3 is not affected, so as to ensure heat dissipation of the semiconductor package device, but also the volume between the frame carrier 1 and the second outer surface 302 of the package body 3 is increased due to the existence of the smooth curved surface, so that the injection molding time between the frame carrier 1 and the first outer surface 301 of the package body 3 during injection molding is balanced with the injection molding time between the frame carrier 1 and the second outer surface 302 of the package body 3, so as to balance the resin solidification molding time between the two, and ensure the use effect of the semiconductor package device.
The semiconductor package device that the correlation technique provided, connecting hole 101 is seted up on packaging body 3, but because packaging body 3's material influence, semiconductor device is long-time with treat the installed part and be connected, can lead to the connecting hole 101 fracture on packaging body 3, and then influence semiconductor package device's use, and this application embodiment is through setting up connection frame carrier 12, be connected with treating the installed part through connection frame carrier 12, the intensity of semiconductor package device has been improved, avoided long-time use to lead to packaging body 3 fracture phenomenon, the life of semiconductor package device has been improved.
The lead assembly provided by the embodiment of the present application may be provided with a plurality of groups of leads 4 according to the requirements of the semiconductor package device, as an example, the number of the leads 4 may be three, or 4, and the like, and the number of the leads 4 is not limited in the embodiment of the present application. One end of each lead 4 is connected with the chip 2, and the other end of each lead extends out of the packaging body 3 and extends outwards along the length direction of the packaging body 3.
The material of the package 3 may be an epoxy molding compound, which has the characteristics of excellent adhesion, excellent electrical insulation, high strength, good heat resistance and chemical resistance, and the like. The packaging body 3 can also be made of an organic silicon packaging material, and the silicon rubber has good thermal aging resistance, ultraviolet aging resistance and insulating property. The packaging body 3 can also be made of polyimide material, and the polyimide material has the advantages of good insulating property, excellent dielectric property, resistance to wetting by organic solvents and moisture and the like.
In an alternative embodiment, the first outer surface 301 of the package body 3 comprises a first horizontal surface 31, an inclined surface 32 and a second horizontal surface 33 which are connected, and a step is formed between the first horizontal surface 31 and the second horizontal surface 33.
The first horizontal surface 31, the inclined surface 32 and the second horizontal surface 33 are integrally formed by injection molding, the height of the first horizontal surface 31 is higher than that of the second horizontal surface 33, and the first horizontal surface 31 and the second horizontal surface 33 form a step in which the first horizontal surface 31 is inclined downward toward the second horizontal surface 33 by the inclined surface 32. The length of the first horizontal surface 31 is greater than the length of the inclined surface 32 and the second horizontal surface 33, and the widths of the first horizontal surface 31, the inclined surface 32 and the second horizontal surface 33 are the same. Specific lengths and widths of the first horizontal surface 31, the inclined surface 32, and the second horizontal surface 33 may be determined according to the requirements of the semiconductor package device, and are not limited in this embodiment of the application.
In an alternative embodiment, the smooth curved surfaces include at least one arc-shaped curved surface, the arc surface of the arc-shaped curved surface faces the second outer surface 302 of the package body 3;
the projection of the arc-shaped curved surface on the first horizontal surface 31 of the package 3 overlaps the projection of the inclined surface 32 on the first horizontal surface 31 of the package 3.
The curved surfaces provided in the embodiment of the present application may be multiple or one curved surface, as long as the smooth curved surfaces are connected with the lead frame carrier 11 and the connection frame carrier 12 to ensure that the volume between the first outer surface 301 of the package body 3 and the frame carrier is equal to the volume between the frame carrier and the second outer surface 302 of the package body 3. It will be understood that when the curved surface is one, the volume between the curved surface, the lead frame carrier 11 and the connection frame carrier 12 and the first outer surface 301 of the package body 3, is equal to the volume between the curved surface, the lead frame carrier 11, the connection frame carrier 12 and the second outer surface 302 of the package body 3. When the curved surface is plural, the volume between the plural curved surfaces, the lead frame carrier 11, and the connection frame carrier 12 and the first outer surface 301 of the package body 3 is equal to the volume between the plural curved surfaces, the lead frame carrier 11, and the connection frame carrier 12 and the second outer surface 302 of the package body 3. The arc of the arc-shaped curved surface faces the second outer surface 302 of the package body 3 to increase the space between the frame carrier and the second outer surface 302 of the package body 3. It is understood that when the plurality of curved surfaces are provided, the curved surfaces of the plurality of curved surfaces may all face the second outer surface 302 of the package body 3, or the curved surfaces of the plurality of curved surfaces may partially face the second outer surface 302 of the package body 3 and partially face away from the second outer surface 302 of the package body 3, as long as a condition that a volume between the first outer surface 301 of the package body 3 and the frame carrier is equal to a volume between the frame carrier and the second outer surface 302 of the package body 3 is satisfied. When the arc curved surfaces are multiple, the arc curved surfaces are smoothly connected. As an example, the plurality of curved surfaces may be integrally formed.
In an alternative embodiment, the distance between the lead frame carrier 11 and the second outer surface 302 of the package body 3 is 0.3 mm-0.5 mm.
A certain distance needs to be maintained between the frame of the lead 4 and the package 3 to ensure heat dissipation between the frame carrier and the package 3, and the gap provided in the embodiment of the present application is between 0.3 mm and 0.5 mm, which may be, for example, 0.3 mm, 0.4 mm, or 0.5 mm.
In an alternative embodiment, the lead assembly further comprises a lead bond, which is connected to the lead 4 at one end and to the chip 2 at the other end.
A plurality of leads 4 are connected to the chip 2 by providing a lead 4 bonding member. The number of wire bonds may be determined according to the number of wires 4, i.e., one wire bond is connected to each wire 4. As one example, the wire bonds may be silicon wires.
In an alternative embodiment, the connection frame carrier 12 has a connection hole 101 thereon, and the connection hole 101 is used for connecting with a member to be mounted.
In the related art, the connection hole 101 is formed in the package body 3, but since the semiconductor package device needs to be mounted on the component to be mounted by a bolt, when the mounting time is long, or the bolt is dismounted for many times, the package body 3 is broken by force, and the use of the semiconductor package device is affected. According to the embodiment of the application, the connecting holes 101 are formed in the connecting frame carrier 12, and the bolts are connected with the to-be-mounted parts through the connecting holes 101 in the connecting frame carrier 12, so that firmness of the semiconductor packaging device is improved. As an example, the number of the connection holes 101 may be determined according to the size of the semiconductor package device or according to the requirement of the component to be mounted, and for example, the number of the connection holes 101 may be one, two, or the like.
In an optional embodiment, the semiconductor device provided in this embodiment further includes a device layer, the device layer is located on the frame carrier, and the chip 2 is located on the device layer.
By providing the device layer, the chip 2 is prevented from being on the device layer, and the chip 2 is isolated from the frame carrier, protecting the chip 2.
In an alternative embodiment, the wire bond is connected to the wire 4 by a wire 4 bonding or soldering connection.
The connection between each lead 4 and the chip 2 may be the same or different. The embodiment of the present application does not limit this.
In an alternative embodiment, the leads 4 comprise power leads or signal leads.
In an alternative embodiment, at least one of the leads 4 is coated with a flange, which is located at a portion of the lead 4 adjacent to the outer surface of the package body 3.
Through setting up the cladding on at least one lead wire 4 and having the flange, the flange is located the position that lead wire 4 and packaging body 3 surface are adjacent, can make between lead wire 4 and the lead wire 4 become from current sharp route to the broken line route along the flange along packaging body 3's creepage route, thereby make the creepage distance between lead wire 4 and the lead wire 4 effectively increase, even when exerting high voltage on packaging body 3, also can guarantee to have sufficient creepage distance between lead wire 4 and the lead wire 4, thereby the dielectric strength of packaging body 3 has been guaranteed, and simultaneously, when packaging body 3 dielectric strength increases, the power of semiconductor package device can correspondingly promote.
It is to be understood, however, that the application is not limited to the particular arrangements and instrumentality described above and shown in the drawings. Also, a detailed description of known process techniques is omitted herein for the sake of brevity. In the above embodiments, several specific steps are described and shown as examples. However, the method processes of the present application are not limited to the specific steps described and illustrated, and those skilled in the art can make various changes, modifications, and additions or change the order between the steps after comprehending the spirit of the present application.
The functional blocks shown in the above-described structural block diagrams may be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, it may be, for example, an electronic circuit, an Application Specific Integrated Circuit (ASIC), suitable firmware, plug-in, function card, or the like. When implemented in software, the elements of the present application are the programs or code segments used to perform the required tasks. The program or code segments may be stored in a machine-readable medium or transmitted by a data signal carried in a carrier wave over a transmission medium or a communication link. A "machine-readable medium" may include any medium that can store or transfer information. Examples of a machine-readable medium include electronic circuits, semiconductor memory devices, ROM, flash memory, Erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, Radio Frequency (RF) links, and so forth. The code segments may be downloaded via computer networks such as the internet, intranet, etc.
The present application may be embodied in other specific forms without departing from its spirit or essential characteristics. For example, the algorithms described in the specific embodiments may be modified without departing from the basic spirit of the application. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
It will be appreciated by persons skilled in the art that the above embodiments are illustrative and not restrictive. Different features which are present in different embodiments may be combined to advantage. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art upon studying the drawings, the specification, and the claims. In the claims, the term "comprising" does not exclude other means or steps; the indefinite article "a" does not exclude a plurality; the terms "first" and "second" are used to denote a name and not to denote any particular order. Any reference signs in the claims shall not be construed as limiting the scope. The functions of the various parts appearing in the claims may be implemented by a single hardware or software module. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
Claims (8)
1. A semiconductor package device, comprising:
the frame carrier (1) comprises a lead frame carrier (11) and a connecting frame carrier (12) which are connected through a smooth curved surface and are distributed in a staggered manner in the thickness direction of the frame carrier;
a chip (2) arranged on the leadframe carrier (11);
the packaging body (3) is used for coating the frame carrier and the chip (2), and the packaging body (3) is provided with a first outer surface (301) and a second outer surface (302) which are opposite;
a lead assembly extending along the length of the package (3), the lead assembly including a plurality of leads (4) connected to the chip (2) and extending outwardly from the package (3);
the volume between the first outer surface (301) of the package (3) and the frame carrier is equal to the volume between the frame carrier and the second outer surface (302) of the package (3);
the first outer surface (301) of the packaging body (3) comprises a first horizontal surface (31), an inclined surface (32) and a second horizontal surface (33) which are connected, and a step is formed between the first horizontal surface (31) and the second horizontal surface (33);
the smooth curved surface comprises at least one arc-shaped curved surface, and the arc surface of the arc-shaped curved surface faces to the second outer surface (302) of the packaging body (3);
the projection of the arc-shaped curved surface on the first horizontal plane (31) of the packaging body (3) is overlapped with the projection of the inclined plane (32) on the first horizontal plane (31) of the packaging body (3).
2. The electronic device package device according to claim 1, wherein the distance between the lead frame carrier (11) and the second outer surface (302) of the package body (3) is 0.3-0.5 mm.
3. The semiconductor package device of claim 1, wherein the lead assembly further comprises a lead bond, the lead bond being connected to the lead (4) at one end and to the chip (2) at the other end.
4. The semiconductor package device of claim 1, wherein the connection frame carrier (12) has a connection hole (101) thereon, the connection hole (101) being used for connection with a member to be mounted.
5. The semiconductor package device of claim 1, wherein the internal circuit assembly further comprises a device layer, the device layer being located on the frame carrier, the chip (2) being located on the device layer.
6. The semiconductor package device according to claim 4, wherein the wire bonding member is connected to the lead (4) by wire bonding or soldering (4).
7. The semiconductor package device according to claim 1, wherein the lead (4) comprises a power supply lead (4) or a signal lead (4).
8. A semiconductor package device according to claim 1, wherein at least one of the leads (4) is coated with a flange at a portion of the lead (4) adjacent to an outer surface of the package body (3).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011553044.9A CN112289765B (en) | 2020-12-24 | 2020-12-24 | Semiconductor package device |
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| JPS55107252A (en) * | 1979-02-09 | 1980-08-16 | Nec Corp | Manufacture of semiconductor device |
| US5197183A (en) * | 1991-11-05 | 1993-03-30 | Lsi Logic Corporation | Modified lead frame for reducing wire wash in transfer molding of IC packages |
| CN203085519U (en) * | 2013-01-14 | 2013-07-24 | 无锡市玉祁红光电子有限公司 | A chip leading wire frame |
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| WO2007010315A2 (en) * | 2005-07-20 | 2007-01-25 | Infineon Technologies Ag | Leadframe strip and mold apparatus for an electronic component and method of encapsulating an electronic component |
| CN109065519B (en) * | 2018-06-13 | 2020-12-25 | 南通通富微电子有限公司 | Semiconductor chip packaging device |
| CN211555856U (en) * | 2020-01-09 | 2020-09-22 | 珠海格力电器股份有限公司 | Semiconductor packaging device and combined semiconductor packaging device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPS55107252A (en) * | 1979-02-09 | 1980-08-16 | Nec Corp | Manufacture of semiconductor device |
| US5197183A (en) * | 1991-11-05 | 1993-03-30 | Lsi Logic Corporation | Modified lead frame for reducing wire wash in transfer molding of IC packages |
| CN203085519U (en) * | 2013-01-14 | 2013-07-24 | 无锡市玉祁红光电子有限公司 | A chip leading wire frame |
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Effective date of registration: 20231120 Address after: No. 6, Lane 1688, Jiugong Road, Jinshan Industrial Zone, Jinshan District, Shanghai, 201500 Patentee after: Ruineng Weien Semiconductor (Shanghai) Co.,Ltd. Address before: 330052 North first floor, building 16, No. 346, xiaolanzhong Avenue, Xiaolan Economic Development Zone, Nanchang County, Nanchang City, Jiangxi Province Patentee before: Ruineng Semiconductor Technology Co.,Ltd. |