CN112269120A - Interface signal loopback test method, apparatus, computer equipment and storage medium - Google Patents
Interface signal loopback test method, apparatus, computer equipment and storage medium Download PDFInfo
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Abstract
The application relates to an interface signal loop test method, an interface signal loop test device, computer equipment and a storage medium. The method comprises the following steps: sending a query instruction to a powered chip to be tested; the chip to be tested is in a low level state; under the condition of receiving the state parameter returned by the chip to be tested, determining that the signal channel corresponding to the chip to be tested is successfully connected; and determining that the connection of the signal channel corresponding to the chip to be tested fails under the condition that the return state parameter of the chip to be tested is not received. By adopting the method, all signals of the production chip or the PCIE interface can be completely tested, including data signals, clocks and reference clock signals, so that the complex process that auxiliary equipment such as an oscilloscope is required for testing is avoided, the PCIE interface hardware and whether an internal module is connected or not can be quickly and efficiently tested, and the test efficiency of the production chip is effectively improved.
Description
Technical Field
The present application relates to the field of computer technologies, and in particular, to a method and an apparatus for testing loop of interface signals, a computer device, and a storage medium.
Background
With the development of computer technology, a pcie (peripheral component interconnect express) interface is widely used in hardware, and communication terminals are more and more common in life of people, and in order to ensure perfect operation of network establishment of communication equipment, many pieces of equipment are required to have a function of loop back test so as to remotely monitor whether the operation of the communication equipment is qualified. Before shipping, a chip or a module of the terminal device needs to perform hardware and interface function access testing, so that testing whether the loop back function of the communication device is qualified before shipping becomes one of important tests.
However, in the current loop test method, it is limited to test only data signals, but not clock signals and reference clock signals, and during the PCIE interface path test, the interface path test can be performed only by accessing the master device and the slave device, or separate tests are performed by using auxiliary devices such as an oscilloscope, which requires a lot of labor and effort to perform the test, and thus, the test efficiency of the chip is low.
Disclosure of Invention
In view of the above, it is desirable to provide an interface signal loop test method, an interface signal loop test apparatus, a computer device, and a storage medium, which can improve the test efficiency of a production chip.
An interface signal loopback test method, the method comprising:
sending a query instruction to a powered chip to be tested; the chip to be tested is in a low level state;
under the condition of receiving the state parameter returned by the chip to be tested, determining that the signal channel corresponding to the chip to be tested is successfully connected;
and determining that the connection of the signal channel corresponding to the chip to be tested fails under the condition that the return state parameter of the chip to be tested is not received.
In one embodiment, the signal channels corresponding to the chips to be tested include a data signal channel and a clock signal channel.
In one embodiment, after sending the query instruction to the powered chip to be tested, the method further includes:
detecting the state parameter of the grounding line corresponding to each clock signal;
determining that the link corresponding to the clock signal is successfully connected under the condition that the state parameter of the grounding line is detected to be in a low level state;
and determining that the link connection corresponding to the clock signal fails under the condition that the state parameter of the grounding line is detected to be in a high-impedance state.
An interface signal loop back test apparatus, the apparatus comprising:
the sending module is used for sending a query instruction to the electrified chip to be tested; the chip to be tested is in a low level state;
the determining module is used for determining that the signal channel corresponding to the chip to be tested is successfully connected under the condition of receiving the state parameter returned by the chip to be tested; and determining that the connection of the signal channel corresponding to the chip to be tested fails under the condition that the return state parameter of the chip to be tested is not received.
A computer device comprising a memory and a processor, the memory storing a computer program, the processor implementing the following steps when executing the computer program:
sending a query instruction to a powered chip to be tested; the chip to be tested is in a low level state;
under the condition of receiving the state parameter returned by the chip to be tested, determining that the signal channel corresponding to the chip to be tested is successfully connected;
and determining that the connection of the signal channel corresponding to the chip to be tested fails under the condition that the return state parameter of the chip to be tested is not received.
A computer-readable storage medium, on which a computer program is stored which, when executed by a processor, carries out the steps of:
sending a query instruction to a powered chip to be tested; the chip to be tested is in a low level state;
under the condition of receiving the state parameter returned by the chip to be tested, determining that the signal channel corresponding to the chip to be tested is successfully connected;
and determining that the connection of the signal channel corresponding to the chip to be tested fails under the condition that the return state parameter of the chip to be tested is not received.
An interface signal loopback test method, the method comprising:
carrying out low level setting operation on a pin corresponding to each clock signal channel of a chip to be tested, and then carrying out power-on operation on the chip to be tested;
sending a query instruction to the chip to be tested;
under the condition of receiving the state parameter returned by the chip to be tested, determining that the signal channel corresponding to the chip to be tested is successfully connected;
and determining that the connection of the signal channel corresponding to the chip to be tested fails under the condition that the return state parameter of the chip to be tested is not received.
In one embodiment, the performing a low level setting operation on the pin of each clock signal channel of the chip to be tested includes:
each clock signal channel is externally connected with a resistor with a preset numerical value;
and carrying out grounding connection operation on the corresponding pin of each clock signal channel.
In one embodiment, after sending the query instruction to the chip to be tested, the method further includes:
detecting the state parameter of the grounding line corresponding to each clock signal;
determining that the link corresponding to the clock signal is successfully connected under the condition that the state parameter of the grounding line is detected to be in a low level state;
and determining that the link connection corresponding to the clock signal fails under the condition that the state parameter of the grounding line is detected to be in a high-impedance state.
An interface signal loop back test apparatus, the apparatus comprising:
the device comprises a setting module, a power-on module and a power-on module, wherein the setting module is used for carrying out low-level setting operation on pins corresponding to each clock signal channel of a chip to be tested and then carrying out power-on operation on the chip to be tested;
the sending module is used for sending a query instruction to the chip to be tested;
the determining module is used for determining that the signal channel corresponding to the chip to be tested is successfully connected under the condition of receiving the state parameter returned by the chip to be tested; and determining that the connection of the signal channel corresponding to the chip to be tested fails under the condition that the return state parameter of the chip to be tested is not received.
A computer device comprising a memory and a processor, the memory storing a computer program, the processor implementing the following steps when executing the computer program:
carrying out low level setting operation on a pin corresponding to each clock signal channel of a chip to be tested, and then carrying out power-on operation on the chip to be tested;
sending a query instruction to the chip to be tested;
under the condition of receiving the state parameter returned by the chip to be tested, determining that the signal channel corresponding to the chip to be tested is successfully connected;
and determining that the connection of the signal channel corresponding to the chip to be tested fails under the condition that the return state parameter of the chip to be tested is not received.
A computer-readable storage medium, on which a computer program is stored which, when executed by a processor, carries out the steps of:
carrying out low level setting operation on a pin corresponding to each clock signal channel of a chip to be tested, and then carrying out power-on operation on the chip to be tested;
sending a query instruction to the chip to be tested;
under the condition of receiving the state parameter returned by the chip to be tested, determining that the signal channel corresponding to the chip to be tested is successfully connected;
and determining that the connection of the signal channel corresponding to the chip to be tested fails under the condition that the return state parameter of the chip to be tested is not received.
According to the interface signal loop test method, the interface signal loop test device, the computer equipment and the storage medium, the inquiry instruction is sent to the electrified chip to be tested, and the chip to be tested is in a low level state. And under the condition of receiving the return state parameters of the chip to be tested, determining that the signal channel corresponding to the chip to be tested is successfully connected. And under the condition that the return state parameters of the chip to be tested are not received, determining that the connection of the signal channel corresponding to the chip to be tested fails. Therefore, all signals of the production chip or the PCIE interface can be completely tested, including data signals, clocks and reference clock signals, the complex process that auxiliary equipment such as an oscilloscope is required to test is avoided, whether the PCIE interface hardware and the internal module are connected or not is rapidly tested, and therefore the testing efficiency of the production chip is effectively improved.
According to the interface signal loop test method, the interface signal loop test device, the computer equipment and the storage medium, after the low level setting operation is carried out on the pin corresponding to each clock signal channel of the chip to be tested, the power-on operation is carried out on the chip to be tested. And sending a query instruction to the chip to be tested, and determining that the signal channel corresponding to the chip to be tested is successfully connected under the condition of receiving the state parameter returned by the chip to be tested. And under the condition that the return state parameters of the chip to be tested are not received, determining that the connection of the signal channel corresponding to the chip to be tested fails. Therefore, after the low-level setting operation is carried out on the clock signal of the PCIE interface, the verification of the signal hardware access can be realized, the complex flow that the auxiliary equipment such as an oscilloscope is required for testing is avoided, and the testing efficiency of the production chip is effectively improved.
Drawings
FIG. 1 is a diagram of an exemplary embodiment of an application environment of a method for loop testing interface signals;
FIG. 2 is a flowchart illustrating a method for loop back testing interface signals according to an embodiment;
FIG. 3A is a diagram illustrating a loopback test performed on a chip under test according to an embodiment;
FIG. 3B is a flowchart illustrating the steps of detecting the state parameter of the ground line corresponding to each clock signal according to one embodiment;
FIG. 4 is a flowchart illustrating a method for loop-back testing interface signals according to another embodiment;
FIG. 5 is a flow chart illustrating the steps of performing a low level set operation on the pins of each clock signal channel of the chip under test in one embodiment;
FIG. 6 is a block diagram of an embodiment of an interface signal loopback test apparatus;
FIG. 7 is a block diagram of an interface signal loopback test device according to another embodiment;
FIG. 8 is a diagram illustrating an internal structure of a computer device according to an embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
The interface signal loop test method provided by the application can be applied to the application environment shown in fig. 1. Wherein, the terminal 102 communicates with the chip 104 to be tested through a network. The terminal 102 sends a query command to the powered chip 104 to be tested, and the chip 104 to be tested is in a low level state. Under the condition that the terminal 102 receives the state parameter returned by the chip 104 to be tested, the signal channel corresponding to the chip 104 to be tested is determined to be successfully connected. The terminal 102 determines that the connection of the signal channel corresponding to the chip 104 to be tested fails when the terminal does not receive the status parameter returned by the chip 104 to be tested. The terminal 102 may be, but is not limited to, various personal computers, notebook computers, smart phones, tablet computers, and portable wearable devices.
In one embodiment, as shown in fig. 2, an interface signal loopback test method is provided, which is described by taking the method as an example applied to the terminal in fig. 1, and includes the following steps:
PCI-express (peripheral component interconnect express) is a high-speed serial computer expansion bus standard, originally named "3 GIO", which was proposed by Intel in 2001, to replace the old PCI, PCI-X and AGP bus standards. PCIe belongs to high-speed serial point-to-point double-channel high-bandwidth transmission, connected devices distribute independent channel bandwidth and do not share bus bandwidth, and the PCIe mainly supports functions of active power management, error reporting, end-to-end reliable transmission, hot plug, quality of service (QOS) and the like.
PCIe is renamed to PCI-Express, which is called PCI-e for short, after being authenticated and issued by PCI-SIG (PCI Special interest group). Its main advantages are high data transmission rate and high development potential. The PCI-e interface is a high-speed communication interface, can be used for communication between board sets and can also be used for communication between board cards. With the wide use of the PCI-e interface in hardware, the chip or the module needs to perform hardware and interface function access testing before shipping, so testing whether the loopback function of the communication device is qualified before shipping becomes one of important tests. Before the chip or the module leaves the factory, a worker can utilize the testing tool to perform access testing on the produced chip so as to ensure that the chip leaves the factory and can normally work.
Specifically, the terminal is exemplified as the test device. The terminal can send a query instruction to the powered chip to be tested, and the chip to be tested is in a low level state. The powered chip to be tested is powered on, namely, the chip to be tested is powered on in a normal voltage range, so that the chip to be tested can be started normally. The low level state is an operation of setting a low level of a signal of the chip to be tested so as to be in the low level state. For example, the user terminal may manually send the query command through the AT command, that is, the user may manually send the query command to AT + GTSET ═ pcie que through the AT command, 0.
And 204, under the condition that the return state parameters of the chip to be tested are received, determining that the signal channel corresponding to the chip to be tested is successfully connected.
After the terminal sends the query instruction to the powered chip to be tested, the terminal determines that the signal channel corresponding to the chip to be tested is successfully connected under the condition that the terminal receives the state parameter returned by the chip to be tested. Specifically, after the terminal sends the query instruction to the powered chip to be tested, when the PCI-e loop test is successful, the state parameter pcielopback ok is returned, that is, when the user terminal receives the state parameter value returned by the chip to be tested, it can be determined that the signal channel corresponding to the chip to be tested is successfully connected, that is, after the user sees the return value, it can be determined that the PCIE loop test is successful.
And step 206, determining that the connection of the signal channel corresponding to the chip to be tested fails under the condition that the return state parameter of the chip to be tested is not received.
After the terminal sends the query instruction to the powered chip to be tested, the terminal determines that the connection of the signal channel corresponding to the chip to be tested fails under the condition that the terminal does not receive the state parameter returned by the chip to be tested. Specifically, after the terminal sends the query instruction to the powered chip to be tested, when the PCI-e loop test is successful, the status parameter pcielopback ok is returned, that is, when the user terminal receives the status parameter value returned by the chip to be tested, the signal channel corresponding to the chip to be tested is determined to be successfully connected, that is, when the user sees the return value, the success of the PCI-e loop test can be confirmed, and if the loop test is unsuccessful, the data is not returned, that is, when the user terminal does not receive the status parameter value returned by the chip to be tested, the connection failure of the signal channel corresponding to the chip to be tested can be determined, that is, when the user does not see the return value, the failure of the PCI-e loop test can be confirmed. In the application, the configuration of the register is carried out on the PCIE module inside the chip or the module to be tested, and the PCIE time sequence inside the module is set to be the RC module, so that the purpose of PCIE communication is realized, and whether the access state is achieved can be rapidly verified. The register configuration refers to the configuration of high and low levels of a circuit in a chip to be tested.
In the conventional PCI-e interface loop test method, only data signals can be tested, clock signals and reference clock signals cannot be tested, and when the clock signals and the reference clock signals are tested on a production line, auxiliary equipment such as code logic or an oscilloscope and the like is required to be tested independently, so that the efficiency of testing production chips on the production line is low, and a user cares whether the loop of the PCI-e interface can be tested efficiently and stably on a module or a chip production line. In this embodiment, by sending the query instruction to the powered chip to be tested, the chip to be tested is in a low level state. And under the condition of receiving the return state parameters of the chip to be tested, determining that the signal channel corresponding to the chip to be tested is successfully connected. And under the condition that the return state parameters of the chip to be tested are not received, determining that the connection of the signal channel corresponding to the chip to be tested fails. Therefore, all signals of the production chip or the PCIE interface can be completely tested, including data signals, clocks and reference clock signals, the complex process that auxiliary equipment such as an oscilloscope is required for testing is avoided, whether the PCIE interface hardware and the internal module are connected or not is rapidly and efficiently tested, and therefore the testing efficiency of the production chip is effectively improved.
In one embodiment, the signal channels corresponding to the chips to be tested comprise a data signal channel and a clock signal channel. Fig. 3A is a schematic diagram illustrating a loop test performed on a certain chip to be tested. Signals transmitted by the PCIE interface belong to differential signals, so RXO _ P and RXO _ M respectively represent positive and negative of the received signal. TXO _ P and TXO _ M represent positive and negative of the transmit signal, respectively. R denotes reception, i.e., a received signal. T denotes send, i.e., transmission information. When the PCIE protocol performs communication, a receive signal and a transmit signal need to be connected, so that the test device can test the transmit-receive signal, and the transmit signal and the receive signal are collectively referred to as a data signal. For example, during the loopback test, the RX-type signal and the TX-type signal are short-circuited, and the terminal is used to test whether the hardware path of the data signal is normal, and during the loopback test, the ioctl returns test data, which is related information of the PCIE connection state. Data link refers to the state of Data connection of the PCIE interface. Meanwhile, in the embodiment of the application, the hardware path verification can be performed on the clock signal, namely the CLK-like signal. For example, during loop back test, CLK-like signals are connected to external devices, and the CLK-like signals are grounded, and the test terminal is used to perform detection on the ground lines of the CLK-like signals, so that a complicated process of testing auxiliary devices such as an oscilloscope is avoided, and verification of hardware paths of the CLK-like signals is achieved. In this embodiment, not only Rx and Tx signals are shorted, and then data transceiving operation is performed, but also the CLK signals are grounded, and the terminal can perform corresponding detection operation on the ground of the CLK signals, so that the hardware path of the signals can be quickly and efficiently verified.
In an embodiment, as shown in fig. 3B, after sending the query instruction to the powered chip to be tested, the method further includes a step of detecting a state parameter of the ground line corresponding to each clock signal, which specifically includes:
And 304, determining that the link corresponding to the clock signal is successfully connected under the condition that the state parameter of the grounding line is detected to be in a low level state.
And step 306, determining that the link connection corresponding to the clock signal fails under the condition that the state parameter of the grounding line is detected to be in a high-impedance state.
After the terminal sends the query instruction to the powered chip to be tested, the terminal can detect the state parameters of the grounding line corresponding to each clock signal. Specifically, the terminal may detect a state parameter of the ground line corresponding to each clock signal. And determining that the link corresponding to the clock signal is successfully connected under the condition that the terminal detects that the state parameter of the grounding line is in a low level state. And determining that the link connection corresponding to the clock signal fails under the condition that the terminal detects that the state parameter of the grounding line is in a high-impedance state. Before the power-on operation is performed on the chip to be tested, the hardware can be adjusted correspondingly. For example, as shown in fig. 3A, PCIE _ CLK _ REQ, REF _ CLK _ P, and REF _ CLK _ M signals may be respectively connected to 50-ohm resistors on a fixture such as a production line, and then connected to a ground signal, where the ground signal is used to connect the pins or signals to ground on a circuit board, and the ground signal is used to pull down the signals. And after the adjusted chip or module to be tested is electrified, the chip or module to be tested is started normally. Further, the terminal may detect a state parameter of the ground line corresponding to each clock signal of the PCIE _ CLK _ REQ, REF _ CLK _ P, and REF _ CLK _ M. And determining that the link corresponding to the PCIE _ CLK _ REQ signal is successfully connected under the condition that the terminal detects that the state parameter of the grounding line corresponding to the PCIE _ CLK _ REQ signal is in a low level state. In the case where the terminal detects that the state parameter of the ground line corresponding to REF _ CLK _ M is in a high impedance state, it is determined that the link connection corresponding to the REF _ CLK _ M signal has failed. Therefore, the PCIE network card equipment is completely simulated by using the register configuration and adjusting the resistance value of the hardware, all signals of the chip or the PCIE can be completely tested, including data signals, clocks and reference clock signals, the verification of hardware paths of all signals is realized, and the test efficiency of the production chip is effectively improved.
In one embodiment, as shown in fig. 4, an interface signal loopback test method is provided, which is described by taking the method as an example applied to the terminal in fig. 1, and includes the following steps:
And 406, determining that the signal channel corresponding to the chip to be tested is successfully connected under the condition that the return state parameter of the chip to be tested is received.
And step 408, determining that the connection of the signal channel corresponding to the chip to be tested fails under the condition that the return state parameter of the chip to be tested is not received.
The terminal can perform power-on operation on the chip to be tested after performing low-level setting operation on the pin corresponding to each clock signal channel of the chip to be tested. Wherein, the chip to be tested can be installed in the terminal equipment. And the terminal sends a query instruction to the electrified chip to be tested, and determines that the signal channel corresponding to the chip to be tested is successfully connected under the condition that the terminal receives the state parameter returned by the chip to be tested. And under the condition that the terminal does not receive the state parameter returned by the chip to be tested, determining that the connection of the signal channel corresponding to the chip to be tested fails. Therefore, after the low-level setting operation is carried out on the clock signal of the PCIE interface, the verification of the signal hardware access can be realized, the complex flow that the auxiliary equipment such as an oscilloscope is required for testing is avoided, and the testing efficiency of the production chip is effectively improved.
In one embodiment, as shown in fig. 5, the step of performing a low setting operation on a pin of each clock signal channel of the chip to be tested includes:
And step 504, performing a ground connection operation on the corresponding pin of each clock signal channel.
The terminal can perform power-on operation on the chip to be tested after performing low-level setting operation on the pin corresponding to each clock signal channel of the chip to be tested. Specifically, the terminal may externally connect a resistor with a preset value to each clock signal channel, and perform a ground connection operation on a pin corresponding to each clock signal channel. For example, a preset value of resistance may be set to 50 ohms, and the ground resistance is a protective measure to prevent lightning strikes on devices such as power and electronics. The grounding operation is an operation for setting a low level to the outside of a corresponding pin of each clock signal channel. For example, the terminal may verify hardware paths of CLK-like signals, which are clock signals on a jig such as a production line. For example, the PCIE _ CLK _ REQ, REF _ CLK _ P, and REF _ CLK _ M signals represent reference clock signals, respectively. The method can be used for externally connecting PCIE _ CLK _ REQ, REF _ CLK _ P and REF _ CLK _ M signals with resistors with preset values of 50 ohms on fixtures such as a production line, performing grounding connection operation on pins corresponding to each clock signal channel of the PCIE _ CLK _ REQ, the REF _ CLK _ P and the REF _ CLK _ M, and starting the chips or modules to be tested which are subjected to the grounding connection operation normally after power-on operation is performed on the chips or modules to be tested. Further, the terminal may detect a state parameter of the ground line corresponding to each clock signal of the PCIE _ CLK _ REQ, REF _ CLK _ P, and REF _ CLK _ M. Therefore, the PCIE network card equipment is completely simulated by using the register configuration and adjusting the resistance value of the hardware, all signals of the chip or the PCIE can be efficiently tested, the signals comprise data signals, clocks and reference clock signals, the hardware access verification of all the signals is realized, and the chip testing efficiency is effectively improved.
In one embodiment, after sending the query instruction to the chip to be tested, the method further includes a step of detecting a state parameter of the ground line corresponding to each clock signal, which specifically includes:
and detecting the state parameter of the grounding line corresponding to each clock signal.
And determining that the link corresponding to the clock signal is successfully connected under the condition that the state parameter of the grounding line is detected to be in a low level state.
And under the condition that the state parameter of the grounding line is detected to be in a high-impedance state, determining that the link connection corresponding to the clock signal fails.
After the terminal sends the query instruction to the powered chip to be tested, the terminal can detect the state parameters of the grounding line corresponding to each clock signal. Specifically, the terminal may detect a state parameter of the ground line corresponding to each clock signal. And determining that the link corresponding to the clock signal is successfully connected under the condition that the terminal detects that the state parameter of the grounding line is in a low level state. And determining that the link connection corresponding to the clock signal fails under the condition that the terminal detects that the state parameter of the grounding line is in a high-impedance state. Before the power-on operation is performed on the chip to be tested, the hardware can be adjusted correspondingly. For example, the PCIE _ CLK _ REQ, REF _ CLK _ P, and REF _ CLK _ M signals may be externally connected to 50-ohm resistors and grounded, respectively, on a fixture such as a production line. And after the adjusted chip or module to be tested is electrified, the chip or module to be tested is started normally. Further, the terminal may detect a state parameter of the ground line corresponding to each clock signal of the PCIE _ CLK _ REQ, REF _ CLK _ P, and REF _ CLK _ M. And determining that the link corresponding to the PCIE _ CLK _ REQ signal is successfully connected under the condition that the terminal detects that the state parameter of the grounding line corresponding to the PCIE _ CLK _ REQ signal is in a low level state. In the case where the terminal detects that the state parameter of the ground line corresponding to REF _ CLK _ M is in a high impedance state, it is determined that the link connection corresponding to the REF _ CLK _ M signal has failed. Therefore, the PCIE network card equipment is completely simulated by using the register configuration and adjusting the resistance value of the hardware, all signals of the chip or the PCIE can be completely tested, including data signals, clocks and reference clock signals, the verification of hardware paths of all signals is realized, and the test efficiency of the production chip is effectively improved.
It should be understood that although the various steps in the flow charts of fig. 1-5 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 1-5 may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, which are not necessarily performed in sequence, but may be performed in turn or alternately with other steps or at least some of the other steps.
In one embodiment, as shown in fig. 6, there is provided an interface signal loop test apparatus, including: a sending module 602 and a determining module 604, wherein:
the sending module 602 is configured to send an inquiry instruction to a powered chip to be tested, where the chip to be tested is in a low level state.
A determining module 604, configured to determine that a signal channel corresponding to a chip to be tested is successfully connected when receiving a status parameter returned by the chip to be tested; and under the condition that the return state parameters of the chip to be tested are not received, determining that the connection of the signal channel corresponding to the chip to be tested fails.
In one embodiment, the apparatus further comprises: and a detection module.
The detection module is used for detecting the state parameters of the grounding line corresponding to each clock signal; determining that the link corresponding to the clock signal is successfully connected under the condition that the state parameter of the grounding line is detected to be in a low level state; and under the condition that the state parameter of the grounding line is detected to be in a high-impedance state, determining that the link connection corresponding to the clock signal fails.
In one embodiment, as shown in fig. 7, there is provided an interface signal loop test apparatus, including: a setting module 702, a sending module 704, and a determining module 706, wherein:
the setting module 702 is configured to perform a low level setting operation on a pin corresponding to each clock signal channel of a chip to be tested, and then perform a power-on operation on the chip to be tested.
The sending module 704 is configured to send a query instruction to the chip to be tested.
A determining module 706, configured to determine that a signal channel corresponding to the chip to be tested is successfully connected when receiving the status parameter returned by the chip to be tested; and under the condition that the return state parameters of the chip to be tested are not received, determining that the connection of the signal channel corresponding to the chip to be tested fails.
In one embodiment, the apparatus further comprises: and connecting the modules.
The connecting module is used for externally connecting a resistor with a preset numerical value to each clock signal channel and performing grounding connection operation on a pin corresponding to each clock signal channel.
In one embodiment, the apparatus further comprises: and a detection module.
The detection module is used for detecting the state parameters of the grounding line corresponding to each clock signal; determining that the link corresponding to the clock signal is successfully connected under the condition that the state parameter of the grounding line is detected to be in a low level state; and under the condition that the state parameter of the grounding line is detected to be in a high-impedance state, determining that the link connection corresponding to the clock signal fails.
For specific definition of the interface signal loop test apparatus, reference may be made to the above definition of the interface signal loop test method, which is not described herein again. All or part of each module in the interface signal loopback testing device can be realized by software, hardware and a combination thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.
In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as shown in fig. 8. The computer device includes a processor, a memory, a communication interface, a display screen, and an input device connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The communication interface of the computer device is used for carrying out wired or wireless communication with an external terminal, and the wireless communication can be realized through WIFI, an operator network, NFC (near field communication) or other technologies. The computer program is executed by a processor to implement a method for testing a loop back of an interface signal. The display screen of the computer equipment can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment can be a touch layer covered on the display screen, a key, a track ball or a touch pad arranged on the shell of the computer equipment, an external keyboard, a touch pad or a mouse and the like.
Those skilled in the art will appreciate that the architecture shown in fig. 8 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
In one embodiment, a computer device is provided, comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the steps of the above-described method embodiments being implemented when the computer program is executed by the processor.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database or other medium used in the embodiments provided herein can include at least one of non-volatile and volatile memory. Non-volatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical storage, or the like. Volatile Memory can include Random Access Memory (RAM) or external cache Memory. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM), among others.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. An interface signal loopback test method, the method comprising:
sending a query instruction to a powered chip to be tested; the chip to be tested is in a low level state;
under the condition of receiving the state parameter returned by the chip to be tested, determining that the signal channel corresponding to the chip to be tested is successfully connected;
and determining that the connection of the signal channel corresponding to the chip to be tested fails under the condition that the return state parameter of the chip to be tested is not received.
2. The method of claim 1, wherein the signal channels corresponding to the chips under test comprise a data signal channel and a clock signal channel.
3. The method of claim 1, wherein after sending the query command to the powered-up chip under test, the method further comprises:
detecting the state parameter of the grounding line corresponding to each clock signal;
determining that the link corresponding to the clock signal is successfully connected under the condition that the state parameter of the grounding line is detected to be in a low level state;
and determining that the link connection corresponding to the clock signal fails under the condition that the state parameter of the grounding line is detected to be in a high-impedance state.
4. An interface signal loopback test method, the method comprising:
carrying out low level setting operation on a pin corresponding to each clock signal channel of a chip to be tested, and then carrying out power-on operation on the chip to be tested;
sending a query instruction to the chip to be tested;
under the condition of receiving the state parameter returned by the chip to be tested, determining that the signal channel corresponding to the chip to be tested is successfully connected;
and determining that the connection of the signal channel corresponding to the chip to be tested fails under the condition that the return state parameter of the chip to be tested is not received.
5. The method of claim 4, wherein the performing a low setting operation on the pin of each clock signal channel of the chip under test comprises:
each clock signal channel is externally connected with a resistor with a preset numerical value;
and carrying out grounding connection operation on the corresponding pin of each clock signal channel.
6. The method of claim 5, wherein after sending the query instruction to the chip under test, the method further comprises:
detecting the state parameter of the grounding line corresponding to each clock signal;
determining that the link corresponding to the clock signal is successfully connected under the condition that the state parameter of the grounding line is detected to be in a low level state;
and determining that the link connection corresponding to the clock signal fails under the condition that the state parameter of the grounding line is detected to be in a high-impedance state.
7. An interface signal loopback test device, the device comprising:
the sending module is used for sending a query instruction to the electrified chip to be tested; the chip to be tested is in a low level state;
the determining module is used for determining that the signal channel corresponding to the chip to be tested is successfully connected under the condition of receiving the state parameter returned by the chip to be tested; and determining that the connection of the signal channel corresponding to the chip to be tested fails under the condition that the return state parameter of the chip to be tested is not received.
8. An interface signal loopback test device, the device comprising:
the device comprises a setting module, a power-on module and a power-on module, wherein the setting module is used for carrying out low-level setting operation on pins corresponding to each clock signal channel of a chip to be tested and then carrying out power-on operation on the chip to be tested;
the sending module is used for sending a query instruction to the chip to be tested;
the determining module is used for determining that the signal channel corresponding to the chip to be tested is successfully connected under the condition of receiving the state parameter returned by the chip to be tested; and determining that the connection of the signal channel corresponding to the chip to be tested fails under the condition that the return state parameter of the chip to be tested is not received.
9. A computer device comprising a memory and a processor, the memory storing a computer program, wherein the processor implements the steps of the method of any one of claims 1 to 6 when executing the computer program.
10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 6.
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