CN101071394A

CN101071394A - Inter-board transparent transmission bus test device and method

Info

Publication number: CN101071394A
Application number: CN 200610078805
Authority: CN
Inventors: 朱红军; 周嵘; 郝磷; 牛堃; 张来喜
Original assignee: ZTE Corp
Current assignee: Guangdong Huabo Enterprise Management Consulting Co ltd; Electric Power Research Institute of State Grid Xinjiang Electric Power Co Ltd
Priority date: 2006-05-08
Filing date: 2006-05-08
Publication date: 2007-11-14
Anticipated expiration: 2026-05-08
Also published as: CN100511172C

Abstract

The invention discloses a test device and method for an inter-board transparent transmission bus, a test device for an inter-board transparent transmission bus, which includes: a main control unit, an inter-board connector unit and an environment The bus unit under test; the main control unit is used to initiate a transparent transmission bus test command, control the bus unit under test to write data to the storage unit of the environmental board, and the bus unit under test to read data from the storage unit of the environmental board , and judge the consistency of the write and read data, analyze the test results and locate the fault, and give the test conclusion; the inter-board connector unit is used to form the connection between the measured bus unit and the environment board storage unit The connecting channel between them; the environment board storage unit is used to provide a bus interface and a storage medium matching the bus unit under test. The test device and method of the invention have low cost, simple implementation and stable and reliable operation.

Description

The proving installation of transparent transmission bus and method between a kind of plate

Technical field

The present invention relates to the single-board testing device and method in a kind of electronics and the communication system, specifically, what relate to is a kind of plate level bus at transparent transmission between plate, such as the device for testing functions and the method for SPI, I2C, parallel bus etc.

Background technology

In the electronics and the communications field of prior art, the bus signals that often occurs on the veneer is transparent to situation on an other veneer or the subcard by each class interface, whether the functional chip that needs to detect this class transparent transmission bus signal correction on the veneer of batch process in Board Functional Test, Board Function Test normal, and signal the driving and the connector of process whether normal.

The device for testing functions of transparent transmission bus generally comprises the test of aspects such as short circuit, open circuit, interface sequence, and common implementation has following two kinds:

The one, every bus signal line is tested as independent I/O, but there is following shortcoming in this scheme: need the provide support hardware capability module of I/O read-write of test environment, and under a fairly large number of situation of bus signal line, required I/O quantity is a lot, cost is higher, complex operation; And can't realize the timing sequence test of bus.

The 2nd, interface corresponding of EPLD on test environment plate design with the bus of tested single board, during test by carrying out data transmit-receive between tested single board and the EPLD and the judgment data consistance is finished.China Patent No. is that CN99127441, applicant are the Chinese patents " the production test interface is connected to the method and apparatus of overall universal serial bus " of International Business Machine Corporation (IBM), be a kind of a production test interface to be connected to the method and apparatus of an overall universal serial bus such as interconnected integrated circuit (I2C) bus, its I/O cache logic sends to need and carries out buffer memory from the data of overall universal serial bus; What be connected with the I/O cache logic receives from the data of I/O cache logic and sends the data to the I/O cache logic from the control interface logic; With the I/O cache logic be connected from the control interface logic pair carry out pacing from the control controller with the exchanges data of I/O cache logic; The error detection occurs logic that is connected between I/O buffer and the overall universal serial bus is used for detecting error condition.

Basic and the above-mentioned scheme of this patent thinking two is identical, buffering and adjustment function have mainly been increased to the I/O data, but its shortcoming is the design relative complex, workload and difficulty that certain logic coding and debugging are arranged, need to increase logic chip in addition, cost compares higher, and in the application of reality, may also can cause the instability of test owing to logical design is improper.

Summary of the invention

The object of the present invention is to provide the proving installation and the method for transparent transmission bus between a kind of plate, the plate level bus of transparent transmission between plate is tested, to realize fast to interface testings under transparent transmission situation between plate such as SPI, I2C, parallel buss.

Technical scheme of the present invention is as follows:

The proving installation of transparent transmission bus between a kind of plate wherein, comprising: main control unit, mother daughter board connector unit and environment plate storage unit are connected with tested bus unit;

Described main control unit is used to initiate transparent transmission bus test command, the tested bus unit of control to be judged and test result is analyzed and localization of fault from described environment plate storage unit reading of data and to the consistance of writing read data to described environment plate storage unit write data, described tested bus unit, provides test result;

Described mother daughter board connector unit is used to constitute the interface channel between described tested bus unit and the described environment plate storage unit;

Described environment plate storage unit is used to provide bus interface and the storage medium that mates with described tested bus unit.

Described device, wherein, described environment plate storage unit is E2PROM chip or the RAM chip with described tested bus unit Interface Matching.

Described device, wherein, described main control unit is all kinds of CPU, MPU system or the logic function module with processing power.

Described device, wherein, described mother daughter board connector unit is a socket connector all kinds of between veneer.

Described device, wherein, described mother daughter board connector is the highly dense socket connector of 2mm.

The method of testing of transparent transmission bus between a kind of plate, it may further comprise the steps:

A, main control unit are initiated the write bus test command;

B, tested bus unit be to environment plate storage unit write data, and the control, address, data-signal of writing process is sent through the mother daughter board connector unit to environment plate storage unit from described tested bus unit, and finishes write operation;

C, behind delay predetermined time, after guaranteeing the write operation normal termination, described main control unit is initiated the read bus test command, tested bus unit is from described environment plate storage unit retaking of a year or grade test data, the control of read procedure, address, data signal channel and to write process identical, but that data-signal flows to is opposite;

After D, described main control unit are finished read operation, the data of reading and writing are compared, and judge whether tested bus unit is normal, and provide localization of fault and test result.

The proving installation and the method for transparent transmission bus between a kind of plate provided by the present invention, cost is low, realizes simple and easyly, and working stability is reliable; Its software and hardware is realized simple and easy, and hardware is equivalent to extend out the E2PROM chip or the RAM chip of a band SPI or I2C or parallel interface, and software is exactly the read-write operation to storer; Test speed is fast, and erasable the operating in the Millisecond time of E2PROM just can be finished, and the read or write speed of RAM is higher.

Description of drawings

Fig. 1 is of the present invention based on storer realization transparent transmission bus test block diagram;

Fig. 2 is the SPI transparent transmission bus interface testing example block diagram of apparatus of the present invention.

Embodiment

Below in conjunction with accompanying drawing, will be described in more detail each preferred embodiment of the present invention.

The proving installation of transparent transmission bus comprises following these parts between plate of the present invention, as shown in Figure 1, main control unit 101, mother daughter board connector unit 102 and environment plate storage unit 103, unit 201 is tested bus units.Wherein, the function that realizes of described main control unit 101 be initiate transparent transmission bus test command, control bus unit 201 to environment plate storage unit 103 write datas, control bus unit 201 from environment plate storage unit reading of data, the consistance of writing read data is judged and test result is analyzed and localization of fault, provided test result.

The function that described mother daughter board connector unit 102 is realized is to constitute interface channel between tested bus unit 201 and the environment plate storage unit 103; The function that described environment plate storage unit 103 realizes provides bus interface and the storage medium with tested bus unit coupling, can select and tested bus interface matching E 2PROM chip or RAM chip.

The connection of this device as shown in Figure 1, each unit connection relation is as follows: described main control unit 101 is initiated the write bus test command, control bus unit 201 is to environment plate storage unit 103 write datas, the control, address, data-signal of writing process is sent through mother daughter board connector unit 102 to environment plate storage unit 103 from bus unit 201, and finishes write operation; In the time-delay some time, after guaranteeing the write operation normal termination, main control unit 101 is initiated the read bus test command, and control bus unit 201 is from environment plate storage unit 103 retaking of a year or grade test datas, the control of read procedure, address, data signal channel and to write process identical, but that data-signal flows to is opposite.After main control unit 101 is finished read operation, the data of reading and writing are compared, thereby judge whether tested bus unit is normal, and provide localization of fault and test result.

The scope of application of apparatus of the present invention comprises: to the test of the bus interface that is transparent to mother daughter board connector, and this class bus can find the E2PROM chip or the RAM chip of interface with it.Bus can include but not limited to following several, 1. SPI; 2. I2C; 3. parallel bus.

Main control unit 101 of the present invention can be all kinds of CPU, MPU system or the logic function module with processing power, such as single-chip microcomputer, DSP, POWERPC mini system.Mother daughter board connector unit 102 can be a socket connector all kinds of between veneer, such as the highly dense socket connector of 2mm; Environment plate storage unit 103 is to satisfy the E2PROM chip or the RAM of transparent transmission bus interface, can select AT25040 for use such as the spi bus interface testing; The test of I2C bus interface can be selected 24C02 for use; The parallel bus interface test can select for use low speed RAM to realize that the selection of RAM is decided according to the figure place of parallel bus address and data line.

Apparatus of the present invention easy to use, simple, its test process is as follows: 1. main control unit 101 starts the transparent transmission bus test commands, and control transparent transmission bus unit 201 writes particular data to environment plate storage unit 103 certain space, such as 0x55; 2. postpone a bit of time, guarantee write operation normal termination (delay time is decided according to the memory device characteristic); 3. main control unit 101 control transparent transmission bus unit 201, from the 1. retaking of a year or grade data 103 unitary spaces write of step, and compare; 4. main control unit 101 is judged the consistance that reads and writes data; 5. by writing and read other specific data to the different address space of storage unit, repeat 1.～4. test process, make test can cover each signal wire of tested bus; 6. gather test result,, provide localization of fault information, at last test result is shown if make mistakes.

Be example with spi bus transparent transmission interface testing flow process below, as shown in Figure 2, the specific implementation of apparatus of the present invention be introduced.

In this embodiment, described main control unit 101 is MPC860 mini systems, mother daughter board connector unit 102 is one the 100 straight formula PCB paster of core 0.8 spacing plugs (chip pin), environment plate storage unit 103 is to adopt the E2RPOM chip AT25040 with SPI interface, measurand 201 comprise SPI controller, spi bus signal 100 core sockets between the buffering chip for driving of process and plate.

Its test process is as follows: MPC860 initiates SPI transparent transmission bus test command, and the SPI controller on the control MPC860 writes 0x55 in the 0x0 unit, address of AT25040 on the environment plate, time-delay 10ms, MPC860 control SPI controller is from the address 0x0 unit retaking of a year or grade data of AT25040, and judge whether it is 0x55, if consistent, think that then spi bus transparent transmission interface is normal, if inconsistent, then there is fault in the spi bus unit.

Apparatus of the present invention are because the realization of its software and hardware is simple and easy, and hardware is equivalent to extend out the E2PROM chip or the RAM chip of a band SPI or I2C or parallel interface, and software is exactly the read-write operation to storer; Because bus timing is by the memory chip hardware supported, so working stability is reliable, and the erasable number of times of E2PROM is generally more than hundreds thousand of times, and the read-write number of times of RAM chip is higher, is enough to satisfy test request; And E2PROM and low speed RAM low price, therefore with low cost; And test speed is fast, and erasable the operating in the Millisecond time of E2PROM just can be finished, and the read or write speed of RAM is higher.

Should be understood that above-mentioned description at specific embodiment is comparatively detailed, can not therefore be interpreted as the restriction to scope of patent protection of the present invention, scope of patent protection of the present invention should be as the criterion with claims.

Claims

1. A test device for inter-board transparent transmission bus, characterized in that it includes: a main control unit, an inter-board connector unit and an environment board storage unit, connected to the bus unit under test;

The main control unit is used to initiate a transparent transmission bus test command, control the bus unit under test to write data to the storage unit of the environmental board, and the bus unit under test to read data from the storage unit of the environmental board, and write data to the storage unit of the environmental board. Judging the consistency of the read data, analyzing the test results and locating the fault, and giving the test conclusion;

The inter-board connector unit is used to form a connection channel between the bus unit under test and the environment board storage unit;

The environmental board storage unit is used to provide a bus interface and a storage medium matching the bus unit under test.

2. The device according to claim 1, wherein the environmental board storage unit is an E2PROM chip or a RAM chip that matches the interface of the bus unit under test.

3. The device according to claim 1, wherein the main control unit is various types of CPUs, MPU systems or logical function modules with processing capabilities.

4. The device according to claim 1, wherein the inter-board connector unit is a socket connector of various types between boards.

5. The device according to claim 4, wherein the board-to-board connector is a 2mm high-density socket connector.

6. A test method for a transparent transmission bus between boards, comprising the following steps:

A. The main control unit initiates a write bus test command;

B. The bus unit under test writes data to the environment board storage unit, and the control, address, and data signals of the writing process are sent from the bus unit under test to the environment board storage unit through the inter-board connector unit, and the write operation is completed;

C. After delaying for a predetermined time and ensuring that the write operation ends normally, the main control unit initiates a bus read test command, and the bus unit under test reads back the test data from the storage unit of the environmental board, and the control, address, and The data signal channel is the same as the writing process, but the data signal flows in the opposite direction;

D. After the main control unit completes the read operation, it compares the data read and written, and judges whether the bus unit under test is normal, and gives fault location and test conclusions.