CN112259141B - Refreshing method of dynamic random access memory, memory controller and electronic device - Google Patents

Abstract

A refreshing method for a dynamic random access memory, a memory controller and an electronic device are provided. The dynamic random access memory comprises a plurality of storage queues, each storage queue comprises a plurality of block groups, and each block group comprises a plurality of blocks. The method comprises the following steps: determining states of a plurality of state machines corresponding to a plurality of storage queues, wherein the storage queues are in one-to-one correspondence with the state machines; determining a plurality of prediction addresses corresponding to a plurality of storage queues; based on the states of the plurality of state machines and the plurality of predicted addresses, a refresh request is generated and sent to an arbiter coupled to the dynamic random access memory such that the arbiter arbitrates the refresh request and, in response to the refresh request winning the arbitration, sends the refresh request to the dynamic random access memory for effecting a refresh of the dynamic random access memory. The method can ensure the continuity of read-write access as much as possible and improve the bandwidth utilization rate on the basis of ensuring timely completion of refreshing.

Description

Dynamic random access memory refresh method, memory controller, and electronic device

Technical field

Embodiments of the present disclosure relate to a refresh method for dynamic random access memory, a memory controller, and an electronic device.

Background technique

Computer systems usually use dynamic random access memory (Dynamic Random Access Memory, DRAM) as the main memory (or memory) of the system. DRAM has high density and low price, so it is widely used in computer systems. DRAM is a kind of semiconductor memory. The main working principle is to use capacitors to store data. The amount of charge stored in the capacitors represents the binary bit (bit) as "0" or "1".

Contents of the invention

At least one embodiment of the present disclosure provides a refreshing method for a dynamic random access memory, wherein the dynamic random access memory includes a plurality of storage queues, each storage queue includes a plurality of block groups, and each block The group includes multiple blocks, and the method includes: determining the states of multiple state machines corresponding to the multiple storage queues, wherein the multiple storage queues correspond to the multiple state machines one-to-one; determining the Multiple predicted addresses corresponding to multiple storage queues; based on the states of the multiple state machines and the multiple predicted addresses, generate a refresh request, and send the refresh request to the device connected to the dynamic random access memory an arbiter, such that the arbiter arbitrates the refresh request and wins the arbitration in response to the refresh request, sending the refresh request to the dynamic random access memory for implementing the dynamic random access memory Access memory refresh.

For example, in a method provided by an embodiment of the present disclosure, determining the status of multiple state machines corresponding to the multiple storage queues includes: for each state machine, based on the value of the delayed refresh counter, the self-refresh entry request and the self-refresh Exit the command to determine the state of the state machine.

For example, in the method provided by an embodiment of the present disclosure, the state machine includes four states: a first priority state, a second priority state, a flushing state and a self-refresh state. The priority of the first priority state is The priority level is higher than the second priority state.

For example, in the method provided by an embodiment of the present disclosure, for each state machine, the state of the state machine is determined based on the value of the delayed refresh counter, the self-refresh entry request, and the self-refresh exit command, The method includes: in response to the value of the delayed refresh counter being greater than or equal to a threshold, causing the state machine to enter the first priority state; in response to the value of the delayed refresh counter being less than the threshold, causing the state machine to enter The second priority state; in response to the self-refresh entry request, causing the state machine to enter the flush state immediately or delayed according to the current state of the state machine; in response to an operation corresponding to the flush state Completed, causing the state machine to enter the self-refresh state; in response to the self-refresh exit command, causing the state machine to enter the first priority state or the second priority state according to the value of the delayed refresh counter. Priority status.

For example, in a method provided by an embodiment of the present disclosure, in response to the self-refresh entry request, causing the state machine to enter the flush state immediately or delayed according to the current state of the state machine includes: responding to the The self-refresh entry request, when the state machine is in the first priority state, causes the state machine to maintain the first priority state until the value of the postponed refresh counter is less than the threshold before entering the state machine. The flush state; in response to the self-refresh entry request, when the state machine is in the second priority state and there is no recorded address in the refresh address recording unit, the state machine enters the flush state; in response In the case of the self-refresh entry request, when the state machine is in the second priority state and there is a recorded address in the refresh address recording unit, the state machine is maintained in the second priority state until the If there is no recorded address in the refresh address recording unit, the flushing state will be entered again.

For example, in a method provided by an embodiment of the present disclosure, determining the plurality of predicted addresses corresponding to the plurality of storage queues includes: for each storage queue, based on the block information and the state machine corresponding to the storage queue. status to determine the predicted address.

For example, in a method provided by an embodiment of the present disclosure, for each storage queue, determining the predicted address based on the block information and the state of the state machine corresponding to the storage queue includes: responding to the state When the machine is in the first priority state and there is no refresh task being executed in the corresponding storage queue, the address of the block that meets the requirements is determined as the predicted address in the order of priority from the first level to the Nth level; In response to the state machine being in the second priority state and there being no refresh task being executed in the corresponding storage queue, the address of the block that satisfies the requirements is determined in priority order from the first level to the Mth level. Determined to be the predicted address; in response to the state machine being in the first priority state and a refresh task being executed in the corresponding storage queue, determining that the predicted address is empty; in response to the state machine being in the The above second priority state, and there is no block that meets the requirements or there is a refresh task being executed in the corresponding storage queue, it is determined that the predicted address is empty; where, N>M>1 and N and M are both Integer, the priority order from the first level to the Nth level gradually decreases, and the priority order of each level is determined based on the block information. The block information at least includes: whether it is valid, whether it is refreshed, whether it is There is a memory access request, whether it is idle, and whether the timing is consistent.

For example, the method provided by an embodiment of the present disclosure further includes: generating a blocking address based on the states of the multiple state machines and the multiple predicted addresses, and sending the blocking address to the arbiter, so that the The arbiter blocks the non-refresh command corresponding to the blocking address.

For example, in a method provided by an embodiment of the present disclosure, the blocking address is generated based on the states of the multiple state machines and the multiple predicted addresses, and the blocking address is sent to the arbiter, including : In response to the state machine being in the first priority state and there being no refresh task being executed in the corresponding storage queue, determine the predicted address corresponding to the storage queue as the blocking address, and set the blocking address to sent to the arbiter.

For example, in the method provided by an embodiment of the present disclosure, the refresh request is generated based on the states of the multiple state machines and the multiple predicted addresses, and the refresh request is sent to the server associated with the dynamic random memory. Obtaining the arbiter of a memory connection includes: based on the status of the plurality of state machines, selecting a storage queue according to a priority selection rule and generating the refresh request, and sending the refresh request to the arbiter; wherein , the refresh request includes a request command, a request address and a flag bit. The request address is the predicted address corresponding to the selected storage queue. The flag bit indicates that the state machine corresponding to the selected storage queue is in the first priority. level status or the second priority status.

For example, in the method provided by an embodiment of the present disclosure, the first priority state includes a first sub-state and a second sub-state, and the priority of the first sub-state is higher than the priority of the second sub-state. stage, the first sub-state is when the value of the delayed refresh counter reaches the maximum value, the second sub-state is when the value of the delayed refresh counter is less than the maximum value and greater than or equal to the threshold; the priority The level selection rule is: select the corresponding storage queue according to the priority order of the first sub-state, the second sub-state, and the second priority state. If all state machines are in the second priority state , then select a storage queue whose predicted address is not empty. If there are multiple state machines with the same priority order, randomly select a storage queue corresponding to a state machine among the multiple state machines with the same priority order.

For example, the method provided by an embodiment of the present disclosure further includes: in response to generating the refresh request, the flag bit of the refresh request indicating the first priority status, and the block corresponding to the request address being not completely free, generating Precharge request and send the precharge request to the arbiter; wherein the precharge request corresponds to the block corresponding to the request address.

For example, in the method provided by an embodiment of the present disclosure, the arbiter is further configured to arbitrate read and write requests, row strobe requests, and the precharge request, and the priority of arbitration is reduced in the following order: The flag bit indicates the refresh request of the first priority state, the read-write request, the row strobe request, the precharge request, and the flag bit indicates the refresh request of the second priority state.

At least one embodiment of the present disclosure also provides a memory controller for a dynamic random access memory, wherein the memory controller is configured to be connected to the dynamic random access memory and configured to control the dynamic random access memory. The memory is refreshed, the dynamic random access memory includes multiple storage queues, each storage queue includes multiple block groups, and each block group includes multiple blocks; the memory controller includes a refresh control module, so The refresh control module includes multiple state machines, multiple address prediction units and request generation units; the multiple state machines correspond to the multiple storage queues one-to-one, and the state machine is configured to switch between multiple states. ; The plurality of address prediction units are in one-to-one correspondence with the plurality of storage queues, and the address prediction unit is configured to determine the predicted address of the corresponding storage queue; the request generation unit is configured to be based on the plurality of state machines status and the predicted address, generate a refresh request, and send the refresh request to an arbiter connected to the dynamic random access memory.

For example, the memory controller provided by an embodiment of the present disclosure further includes the arbiter, wherein the refresh control module is connected to the arbiter, the arbiter is connected to the dynamic random access memory, and the arbiter The processor is configured to arbitrate the refresh request, and in response to winning the arbitration for the refresh request, send the refresh request to the dynamic random access memory for implementing refresh of the dynamic random access memory.

For example, in the memory controller provided by an embodiment of the present disclosure, the refresh control module further includes a plurality of blocking address generation units; the plurality of blocking address generation units correspond to the plurality of storage queues one by one, and the The blocking address generation unit is configured to generate a blocking address based on the predicted address and the state of the state machine of the storage queue corresponding to the predicted address, and send the blocking address to the arbiter; the arbiter is further configured to Block the non-refresh command corresponding to the blocked address.

For example, in the memory controller provided by an embodiment of the present disclosure, the refresh control module further includes a refresh interval counter, a plurality of postponed refresh counters and a plurality of refresh address recording units; the refresh interval counter is configured to count in a loop, and When the count value reaches the count setting value, a pulse is generated and cleared, and the pulse is sent to the multiple delayed refresh counters; the multiple delayed refresh counters correspond to the multiple storage queues in a one-to-one manner, and the delayed refresh counters are in one-to-one correspondence with the multiple storage queues. The refresh counter is configured to count postponed refresh requests of the corresponding storage queue based on the received pulses, and the state machine determines the state based on the value of the corresponding postponed refresh counter; the plurality of refresh address recording units are related to the plurality of refresh address recording units. Each storage queue has a one-to-one correspondence, and the refresh address recording unit is configured to record the address of the refreshed block.

At least one embodiment of the present disclosure further provides an electronic device, including the memory controller according to any embodiment of the present disclosure.

For example, an electronic device provided by an embodiment of the present disclosure further includes the dynamic random access memory.

Description of drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure. .

Figure 1 is a schematic structural diagram of a memory controller for dynamic random access memory provided by some embodiments of the present disclosure;

Figure 2 is a schematic structural diagram of a refresh control module in a memory controller for dynamic random access memory provided by some embodiments of the present disclosure;

Figure 3 is a schematic flowchart of a refreshing method for dynamic random access memory provided by some embodiments of the present disclosure;

Figure 4 is a schematic diagram of a state machine used in a refresh method of a dynamic random access memory provided by some embodiments of the present disclosure;

Figure 5 is a schematic flowchart of another refresh method for dynamic random access memory provided by some embodiments of the present disclosure; and

FIG. 6 is a schematic block diagram of an electronic device provided by some embodiments of the present disclosure.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present disclosure.

Unless otherwise defined, technical terms or scientific terms used in this disclosure shall have the usual meaning understood by a person with ordinary skill in the art to which this disclosure belongs. "First", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Likewise, similar words such as "a", "an" or "the" do not indicate a quantitative limitation but rather indicate the presence of at least one. Words such as "include" or "comprising" mean that the elements or things appearing before the word include the elements or things listed after the word and their equivalents, without excluding other elements or things. Words such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", etc. are only used to express relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

DRAM is volatile memory and cannot hold data permanently. This is because DRAM uses capacitors to store data. Over time, the charge on the capacitors will gradually drain away, resulting in data loss. Therefore, in order to maintain data, DRAM needs to be refreshed periodically (Refresh), that is, the data in the capacitor is read out and rewritten to restore the charge on the capacitor to its original level, thereby maintaining the data. the goal of.

However, during the refresh process, DRAM cannot perform normal read and write access, nor can it receive any other commands, which has a negative impact on memory bandwidth. Before the fifth generation of Double Data Rate Dynamic Random Access Memory (DDR5 DRAM), refresh commands were performed in units of queues (Rank). This type of refresh command was called REFab (all bank refresh). In common refresh schemes, most refresh scheduling is implemented by grading refreshes. When the refresh accumulation is close to the upper limit time that can be postponed, the DRAM is urgently refreshed. When an emergency refresh occurs, the impact on DRAM performance is very obvious.

Starting from DDR5 DRAM, a more fine-grained refresh command can be used. This refresh command is performed in units of banks. This type of refresh command is called REFsb (same bank refresh). This refresh command will cause a storage All blocks with the same block address in the queue are refreshed.

However, in the current refresh scheme, it is difficult to take into account DRAM refresh and read and write access. Refresh has a greater impact on DRAM performance, resulting in lower bandwidth utilization of DRAM.

At least one embodiment of the present disclosure provides a refresh method for dynamic random access memory, a memory controller, and an electronic device. This method has multi-level priority and arbitration logic, which can take into account the refresh and read-write access of the dynamic random access memory. On the basis of ensuring the timely completion of the refresh, it ensures the continuity of the read-write access as much as possible and reduces the impact of the refresh on the dynamic random access memory. The impact of accessing memory performance, improving the bandwidth of memory access, and improving bandwidth utilization.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that the same reference numbers in different figures will be used to refer to the same elements that have been described.

At least one embodiment of the present disclosure provides a refreshing method for a dynamic random access memory. The dynamic random access memory includes a plurality of storage queues, each storage queue includes a plurality of block groups, and each block group includes a plurality of block groups. blocks. The method includes: determining the status of multiple state machines corresponding to multiple storage queues, and multiple storage queues corresponding to multiple state machines; determining multiple prediction addresses corresponding to the multiple storage queues; based on the status of multiple state machines and a plurality of predicted addresses, generate a refresh request, and send the refresh request to an arbiter connected to the dynamic random access memory, so that the arbiter arbitrates the refresh request, and in response to the refresh request winning the arbitration, sends the refresh request to Dynamic random access memory is used to realize the refresh of dynamic random access memory.

FIG. 1 is a schematic structural diagram of a memory controller for a dynamic random access memory provided by some embodiments of the present disclosure. For example, the memory controller 100 is suitable for controlling DDR5 DRAM. It should be noted that FIG. 1 only shows the functional modules related to the refresh operation in the memory controller 100. Other functional modules can be set according to requirements, and the embodiments of the present disclosure do not limit this.

For example, the DRAM that needs to be refreshed includes multiple storage queues (Ranks), each storage queue includes multiple block groups, and each block group includes multiple blocks (Banks). For example, in some examples, the DRAM includes 32 or 64 storage queues, each storage queue includes 4 or 8 block groups, and each block group includes 2 or 4 blocks. Regarding the specific structure of DRAM, please refer to conventional design and will not be described in detail here.

For example, as shown in Figure 1, the memory controller 100 is connected to the bus interface and the DDR5 physical layer respectively, and can receive memory access commands from the central processing unit (Central Processing Unit, CPU) core transmitted by the bus interface to access the DRAM. (such as reading and writing data), and can control DRAM to refresh. For example, the memory controller 100 is connected to the DDR5 physical layer through a DDR PHY Interface (DFI) interface, and may further be connected to the DDR5 physical layer through an Advanced Peripheral Bus (APB) interface to implement memory control. The connection between the processor 100 and the DRAM. Thus, the memory controller 100 can configure control registers, perform storage access to DRAM, and issue commands such as refresh and calibration. For example, in some examples, the memory controller 100 includes a 32-bit wide DRAM channel without error correction bits (ECC bits).

For example, the memory controller 100 includes an address decoder 101, a command queue 102, a data cache 103, a timing checker 104, a block status record table 105, an arbiter 106, a refresh control module 107, a start queue 108 and a pre-charge module. 109.

The address decoder 101 is configured to convert the physical address of the received memory access request into the standard address format of DDR5 DRAM according to the address mapping method specified by the configuration register. The command queue 102 is configured to store received memory access commands, and at the same time, update the stored memory access request information in real time according to the information provided by the arbiter 106 . For example, if a write request is received, the corresponding data will be stored in the data cache 103 . In addition to storing memory access information, the command queue 102 also provides some statistical results for use by other modules. For example, the command queue 102 needs to provide the following two kinds of statistical information to the refresh control module 107: (1) Statistics of memory access commands corresponding to the block address, to inform the refresh control module 107 whether there is a memory access request for the corresponding block in the command queue 102 ; (2) Whether there is a type of memory access command corresponding to the block address. This type of memory access command means that a row strobe command has been issued, but the read and write commands have not yet been issued, that is, the read and write have not yet been issued. Completed command.

The timing checker 104 records and detects various timing parameters used in memory access, and provides necessary timing information to the arbiter 106 and the refresh control module 107 to ensure the correctness of the DRAM memory access operation. The block status record table 105 records the address and status of each DRAM block, and is updated according to the arbitration result of the arbiter 106 . At the same time, whenever a memory access request arrives, the block status record table 105 will also provide the command queue 102 with the initial block status information of the memory access request.

The arbiter 106 is configured to receive various requests from other modules and filter the requests according to established rules. When a command wins arbitration, the arbiter 106 sends the winning command to the departure queue 108. At the same time, the arbiter 106 also provides feedback signals to each module to help these modules update information. For example, the arbiter 106 is further configured to block requests (eg, read and write requests, etc.) corresponding to the blocking address provided by the refresh control module 107 .

The refresh control module 107 is configured to defer or generate refresh requests according to the configuration of the configuration register and information provided by the command queue 102, the timing checker 104 and the block status record table 105, and provide relevant priority indications. Since executing REFsb requires the block of the corresponding address to be in an idle state, the refresh control module 107 is also configured to generate a same bank address pre-charge (PCHGsb) request as needed. The same bank address pre-charge request will All blocks with the same block address in a storage queue are precharged. In order to ensure that refresh and precharge can be performed normally and orderly, and to take into account read and write access, the refresh control module 107 also provides a blocking address and tells the arbiter 106 to block other commands corresponding to the blocking address according to the blocking address.

The departure queue 108 is configured to send the request from the arbiter 106 to the DFI interface according to the rules and eventually reach the DRAM, and receive the data read back from the DRAM and return the data to the bus interface so that the data reaches the CPU core. For example, when the request from the arbiter 106 is a write request, the departure queue 108 will also send the data obtained from the data cache 103 to the DFI interface according to the rules, and finally reaches the DRAM to implement data writing.

The pre-charging module 109 is configured to monitor the block access history. When a certain block has not been read or written within a certain period of time, the pre-charging module 109 will generate a pre-charging command to close the block.

FIG. 2 is a schematic structural diagram of a refresh control module in a memory controller for a dynamic random access memory provided by some embodiments of the present disclosure. For example, as shown in Figure 2, the refresh control module 107 includes a refresh interval counter 201, a plurality of postponed refresh counters 202, a plurality of state machines 203, a request generation unit 204, a plurality of address prediction units 205, and a plurality of blocking address generation units 206. and multiple refresh address recording units 207.

Multiple state machines 203 correspond to multiple storage queues in a one-to-one manner, that is, each storage queue is assigned a separate state machine 203. State machine 203 is configured to switch between multiple states. Multiple address prediction units 205 correspond to multiple storage queues in a one-to-one manner, that is, each storage queue is assigned one address prediction unit 205. The address prediction unit 205 is configured to determine the predicted address of the corresponding storage queue. The request generation unit 204 is configured to generate a refresh request based on the states of the plurality of state machines 203 and the predicted addresses, and send the refresh request to the arbiter 106 connected to the DRAM.

Multiple blocking address generating units 206 correspond to multiple storage queues in a one-to-one manner, that is, each storage queue is independently assigned a blocking address generating unit 206. The blocking address generation unit 206 is configured to generate a blocking address based on the predicted address and the state of the state machine 203 of the storage queue corresponding to the predicted address, and send the blocking address to the arbiter 106 .

The refresh interval counter 201 is configured to count cyclically, and when the count value reaches a count setting value, it generates a pulse and clears it, and sends pulses to multiple delayed refresh counters 202 . Multiple deferred refresh counters 202 correspond to multiple storage queues in a one-to-one manner, that is, each storage queue is independently assigned a deferred refresh counter 202. The deferred refresh counter 202 is configured to count deferred refresh requests of the corresponding storage queue based on the received pulses, and the state machine 203 determines the state based on the value of the corresponding deferred refresh counter 202 . Multiple refresh address recording units 207 correspond to multiple storage queues in a one-to-one manner, that is, each storage queue is independently assigned a refresh address recording unit 207. The refresh address recording unit 207 is configured to record the address of the refreshed block.

FIG. 3 is a schematic flowchart of a refreshing method for dynamic random access memory provided by some embodiments of the present disclosure. For example, in some examples, as shown in Figure 3, the method includes the following operations.

Step S10: Determine the states of multiple state machines corresponding to multiple storage queues, where multiple storage queues correspond to multiple state machines one-to-one;

Step S20: Determine multiple prediction addresses corresponding to multiple storage queues;

Step S30: Generate a refresh request based on the states of multiple state machines and multiple predicted addresses, and send the refresh request to the arbiter connected to the dynamic random access memory, so that the arbiter arbitrates the refresh request and responds to The refresh request wins arbitration, and the refresh request is sent to the dynamic random access memory to implement refresh of the dynamic random access memory.

Each of the above steps will be exemplarily explained below with reference to the refresh control module 107 shown in FIG. 2 .

For example, in step S10, multiple storage queues correspond to multiple state machines 203 one-to-one, that is, each storage queue is independently assigned a state machine 203, and the states of the multiple state machines 203 may be the same or different.

As shown in FIG. 4 , the state machine 203 includes four states: a first priority state 302 , a second priority state 303 , a flush state 304 and a self-refresh state 301 . For example, the priority of the first priority state 302 is higher than the priority of the second priority state 303. That is, the first priority state 302 is a high priority state and the second priority state 303 is a low priority state. . Self-refresh state 301 is a state of DRAM used in sleep mode or low-power mode. In self-refresh state 301, DRAM will refresh periodically according to the internal clock to maintain data. In this state, DRAM does not receive data from the outside. any command. The flush state 304 is used to prepare for entering the self-refresh state 301. In the flush state 304, the command queue 102 will be cleared (that is, all issued). In addition, high-priority refresh requests will also be cleared (also That is, all are issued), low-priority refresh requests will be cleared selectively according to needs (that is, whether to all be issued). For example, as shown in Figure 4, the state machine 203 can jump and switch between four states in the direction indicated by the arrowed lines in the figure to achieve state changes.

For example, determining the status of multiple state machines 203 corresponding to multiple storage queues may include: for each state machine 203, determining the status of the state machine 203 based on the value of the delayed refresh counter 202, the self-refresh entry request, and the self-refresh exit command. .

Further, for each state machine 203, determining the state of the state machine 203 according to the value of the delayed refresh counter 202, the self-refresh entry request and the self-refresh exit command may include the following operations: in response to the value of the delayed refresh counter 202 being greater than or is equal to the threshold, causing the state machine 203 to enter the first priority state 302; in response to the value of the delayed refresh counter 202 being less than the threshold, causing the state machine 203 to enter the second priority state 303; in response to the self-refresh entry request, according to the state machine 203 In the current state, the state machine 203 enters the flush state 304 immediately or delayed; in response to the completion of the operation corresponding to the flush state 304, the state machine 203 enters the self-refresh state 301; in response to the self-refresh exit command, the value of the delayed refresh counter 202 is , causing the state machine 203 to enter the first priority state 302 or the second priority state 303.

For example, the above thresholds can be set according to requirements and specified by configuration registers. Generally, DRAM needs to be refreshed periodically according to the average refresh time interval (Trefi), which can be postponed up to 4 times in normal refresh mode and up to 8 times in fine-grained refresh mode. Therefore, the above threshold can be set to a value less than 8, such as 5, 6, or 7, etc., which can be determined according to actual needs, and embodiments of the present disclosure do not limit this.

The main basis for the state machine 203 to perform state transition between the first priority state 302 and the second priority state 303 is the value of the delayed refresh counter 202 . When the value of the delayed refresh counter 202 is greater than or equal to the threshold, the state machine 203 enters the first priority state 302 (that is, enters the high priority state); when the value of the delayed refresh counter 202 is less than the threshold, the state machine 203 enters the second Priority state 303 (that is, entering a low priority state).

For example, according to the value of the delayed refresh counter 202, the first priority state 302 is divided into a first sub-state and a second sub-state, and the priority of the first sub-state is higher than the priority of the second sub-state. For example, the first substate is when the value of the delayed refresh counter 202 reaches the maximum value, and the second substate is when the value of the delayed refresh counter 202 is less than the maximum value and greater than or equal to the threshold. For example, the maximum value can be set according to actual requirements, for example, it can be set to 8 or other applicable values, and the embodiments of the present disclosure do not limit this.

For example, the refresh interval counter 201 starts working after the memory controller 100 and the DRAM complete initialization. The refresh interval counter 201 counts cyclically, and when the count value reaches a count setting value (the count setting value is Trefi, for example), a pulse is generated and cleared, and the generated pulse is sent to the postponed refresh counter 202 . Whenever the refresh interval counter 201 generates a pulse, all delayed refresh counters 202 are incremented by 1 and counted once. The value of the delayed refresh counter 202 represents the number of currently postponed refresh requests. When the value of the delayed refresh counter 202 is 0, it means that the DRAM does not need to be refreshed.

When the refresh control module 107 receives the self-refresh entry request, it causes the state machine 203 to enter the flush state 304 immediately or delayed according to the current state of the state machine 203 . For example, in response to the self-refresh entry request, when the state machine 203 is in the first priority state 302, the state machine 203 is maintained in the first priority state 302 until the value of the delayed refresh counter 202 is less than the threshold and then enters the flush state 304, also That is, entering flush state 304 is delayed. In response to the self-refresh entry request, when the state machine 203 is in the second priority state 303 and there is no recorded address (no address is recorded) in the refresh address recording unit 207, the state machine 203 is entered into the flush state 304, that is, Immediately enter flush state 304. In response to the self-refresh entry request, when the state machine 203 is in the second priority state 303 and there is a recorded address in the refresh address recording unit 207, the state machine 203 is maintained in the second priority state 303 until there is no record address in the refresh address recording unit 207. Record the address (that is, after completing the refresh of all block addresses) and then enter the flush state 304.

For example, in the flushing state 304, the command queue 102 will be cleared (that is, all issued), high-priority refresh commands will also be cleared (that is, all issued), and the refresh control module 107 will be based on the instructions of the configuration register. Select whether to issue all remaining accumulated low-priority refresh requests. After the operation corresponding to the flush state 304 is completed, that is, after all the above-mentioned requests that need to be issued have been issued, the state machine 203 enters the self-refresh state 301.

When receiving the self-refresh exit command, if the value of the delayed refresh counter 202 is greater than or equal to the threshold, the state machine 203 is made to enter the first priority state 302. If the value of the delayed refresh counter 202 is less than the threshold, the state machine 203 is made to enter the self-refresh exit command. Second priority status 303. By using the aforementioned state transition mechanism, it is ensured that all blocks have received the REFsb request before entering the self-refresh state 301 (that is, all blocks have been refreshed once). Therefore, after exiting the self-refresh state 301, the state machine 203 The process of sending the compensation refresh will be skipped and directly jump from the self-refresh state 301 to the first priority state 302 or the second priority state 303. Since the number of REFsb required for compensation refresh is always greater than or equal to the number of REFsb required to achieve the condition that all blocks receive REFsb before entering the self-refresh state 301, the overall process of entering and exiting the self-refresh state 301 can be reduced through the above method. of additional overhead. Of course, the embodiments of the present disclosure are not limited to this. In other examples, no restrictions are placed before entering the self-refresh state 301, and compensation refresh can be performed after exiting the self-refresh state 301.

For example, in step S20, the multiple address prediction units 205 respectively determine multiple predicted addresses corresponding to the multiple storage queues. That is, the multiple address prediction units 205 correspond to the multiple storage queues one-to-one. Each address prediction unit 205 determines multiple predicted addresses corresponding to the multiple storage queues. 205 Determine the predicted address corresponding to the corresponding storage queue. For example, the predicted address may be the address of a certain block, indicating the block address of the next REFsb request of the current storage queue predicted by the address prediction unit 205. The address prediction unit 205 supplies the determined predicted address to the request generation unit 204 and the blocking address generation unit 206 . It should be noted that each address prediction unit 205 determines a predicted address, which may be the address of a certain block, or may be empty.

For example, determining multiple predicted addresses corresponding to multiple storage queues includes: for each storage queue, determining the predicted address based on block information and the state of the state machine 203 corresponding to the storage queue.

Further, for each storage queue, determining the predicted address based on the block information and the state of the state machine 203 corresponding to the storage queue may include the following operations: in response to the state machine 203 being in the first priority state 302 and the corresponding storage queue There is no refresh task being executed, and the address of the block that meets the requirements is determined as the predicted address in priority order from the first level to the Nth level; in response to the state machine 203 being in the second priority state 303 and the corresponding storage There is no refresh task being executed in the queue, and the address of the block that meets the requirements is determined as the predicted address in priority order from the first level to the Mth level; in response to the state machine 203 being in the first priority state 302 and the corresponding There is a refresh task being executed in the storage queue, and it is determined that the predicted address is empty; in response to the state machine 203 being in the second priority state 303, and there is no block that meets the requirements or there is a refresh task being executed in the corresponding storage queue , confirm that the predicted address is empty. For example, if the block is divided into N levels, N>M>1 and N and M are both integers, the priority order from the first level to the Nth level gradually decreases. It should be noted that the specific values of N and M can be determined according to actual needs, and the embodiments of the present disclosure do not limit this.

For example, the priority order of each level is determined based on block information. The block information at least includes: whether it is valid, whether it is refreshed, whether there is a memory access request, whether it is idle, whether the timing is consistent, etc.

For example, in some examples, when the address prediction unit 205 performs address prediction, the following information may be referred to: (1) It has not been refreshed, that is, whether the block address is recorded in the refresh address recording unit 207; (2) There is no memory access request. , that is, whether there is a memory access request for the block in the command queue 102; (3) the block is idle, that is, whether the corresponding block is in an idle state; (4) the block reading and writing is completed, that is, the corresponding block has not been read or written yet. command; (5) The refresh timing is consistent, that is, whether the timing check required by the REFsb request is met; (6) The precharge timing is met, that is, whether the timing check required by the PCHGsb request is met; (7) Valid block, that is, the current block address Whether it is a valid address (the number of blocks contained in each block group may be 2 or 4).

It should be noted that the block information referenced by the address prediction unit 205 when performing address prediction is not limited to the information listed above, and may also include any other applicable information, which may be determined according to actual needs. The embodiments of the present disclosure are suitable for This is not a limitation.

For example, in some examples, the blocks are divided into 10 levels, that is, the aforementioned N is equal to 10. For example, M equals 2. The address prediction unit 205 selects blocks to determine predicted addresses based on the following rules:

(1) First level: valid block, not refreshed, no memory access request, block is idle, refresh timing is consistent;

(2) Second level: valid block, not refreshed, no memory access request, block idle, refresh timing does not meet;

(3) The third level: valid block, not refreshed, no memory access request, block is not idle, precharge timing is consistent;

(4) Level 4: Valid block, not refreshed, no memory access request, block not idle, precharge timing does not meet;

(5) Level 5: Valid block, not refreshed, there is a memory access request, block reading and writing is completed, the block is idle, and the refresh timing is consistent;

(6) Level 6: Valid block, not refreshed, memory access request, block read and write completed, block idle, refresh timing does not match;

(7) The seventh level, the valid block, has not been refreshed, there is a memory access request, the block read and write is completed, the block is not idle, and the precharge timing is consistent;

(8) Level 8: Valid block, not refreshed, memory access request, block read and write completed, block not idle, precharge timing does not meet;

(9) Level 9: Valid block, not refreshed, block reading and writing not completed, precharge timing consistent;

(10) Level 10: Valid block, not refreshed, block read and write not completed, precharge timing does not match.

For example, the priority order gradually decreases from the first level to the tenth level.

When the state machine 203 is in the first priority state 302 and there is no refresh task being executed in the corresponding storage queue, the address of the block that meets the requirements will be determined as a prediction in priority order from the first level to the tenth level. The address, that is, predictions from the first level to the tenth level are performed; when the state machine 203 is in the first priority state 302 and there is a refresh task being executed in the corresponding storage queue, it is determined that the prediction address is empty.

When the state machine 203 is in the second priority state 303 and there is no refresh task being executed in the corresponding storage queue, the address of the block that meets the requirements will be determined as a prediction in priority order from the first level to the second level. Address, that is, prediction from the first level to the second level is performed; when the state machine 203 is in the second priority state 303, and there is no block or corresponding storage queue that satisfies the first level to the second level. When there is a refresh task being executed, it is determined that the prediction address is empty.

Low-priority commands only have the first two levels of prediction. When no conditions are met, low-priority commands will accumulate. That is, the prediction address corresponding to the corresponding storage queue is empty and will not be selected by the request generation unit 204. . High priority commands have all level 10 predictions. In this way, simultaneous reading, writing and refreshing can be ensured, and meaningless row strobes can be avoided, thereby improving bandwidth utilization. Here, "meaningless row strobe" means that after row strobe, it is precharged without issuing a read or write command.

For example, in step S30, the request generation unit 204 generates a refresh request based on the states of the plurality of state machines 203 and the plurality of predicted addresses, and sends the refresh request to the arbiter 106 connected to the DRAM. This causes the arbiter 106 to arbitrate the refresh request, and in response to winning the arbitration for the refresh request, the arbiter 106 sends the refresh request to the DRAM for implementing refresh of the DRAM. For example, the request generation unit 204 selects a storage queue according to priority selection rules based on the states of the plurality of state machines 203 and generates a refresh request, and sends the refresh request to the arbiter 106 .

For example, the generated refresh request includes a request command, a request address and a flag bit. The request address is the predicted address corresponding to the selected storage queue. The flag bit indicates that the state machine 203 corresponding to the selected storage queue is in the first priority state 302 or the second priority state 303. For example, in some examples, a 1-bit binary number (such as “0” and “1”) may be used to indicate that the state machine 203 corresponding to the selected storage queue is in the first priority state 302 or the second priority state 303.

For example, in some examples, request generation unit 204 selects a storage queue according to the following priority selection rules. The priority selection rule is: select the corresponding storage queue according to the priority order of the first sub-state of the first priority state 302, the second sub-state of the first priority state 302, and the second priority state 303, that is, Yes, the priority relationship is: the first sub-state of the first priority state 302 > the second sub-state of the first priority state 302 > the second priority state 303; if all state machines 203 are in the second priority state 303, then select the storage queue whose predicted address is not empty; if there are multiple state machines 203 with the same priority order, randomly select the storage corresponding to one state machine 203 among the multiple state machines 203 with the same priority order. queue. Based on the above priority selection rules, the request generation unit 204 will preferentially select a high-priority storage queue to generate a corresponding refresh request and send it to the arbiter 106 .

By selecting the storage queue according to the first sub-state, the second sub-state, and the second priority state 303, it can be ensured that the storage queue whose value of the postponed refresh counter 202 reaches the critical point is selected first for refresh, ensuring that the refresh will not violation. If there are multiple state machines 203 with the same priority order, the storage queue corresponding to one state machine 203 is randomly selected among the multiple state machines 203 with the same priority order. Through random selection, it is possible to avoid causing certain problems in a fixed order. There are too many refreshes accumulated in the storage queue.

By selecting the storage queue according to the above priority selection rules and generating the corresponding refresh request, it is ensured that blocks without read and write memory access requests are refreshed, so that when the block is refreshed, other blocks with read and write memory access can be read. Write operations maximize the parallelization of refresh, read and write, thereby effectively improving bandwidth.

The arbiter 106 not only receives refresh requests from the request generation unit 204, but also receives read and write requests, row strobe requests, precharge requests, etc. from other units and modules. The arbiter 106 is configured to respond to refresh requests, read and write requests, row Various requests such as gating requests and precharge requests are arbitrated. For example, the priority of arbitration by the arbiter 106 decreases in the following order: a refresh request with a flag bit indicating the first priority state 302, a read-write request, a row strobe request, a precharge request, and a flag bit indicating the second priority state 303. refresh request. The arbiter 106 can enable the high-priority REFsb to reach the DRAM in time to maintain the data of the DRAM. It should be noted that the priority order of arbitration by the arbiter 106 is not limited to the above order, and any other applicable rules can also be used for arbitration. Moreover, the requests to participate in arbitration can also include power down requests and mode register requests. read) request, impedance calibration (zq calibration) request, and other various other requests, which may be determined according to actual needs, and embodiments of the present disclosure do not limit this.

When the arbiter 106 performs arbitration, if the refresh request from the request generation unit 204 wins the arbitration, the arbiter 106 will send the refresh request that wins the arbitration to the DRAM to implement refresh of the DRAM. Regarding the specific operation of refreshing the DRAM after receiving the refresh request, please refer to the conventional design and will not be detailed here.

For example, after the refresh request wins arbitration, the refresh address recording unit 207 will record the refreshed block address. When all block addresses are refreshed by REFsb, the refresh address recording unit 207 is cleared, and the delayed refresh counter 202 is decremented by 1 and counted once. If the refresh interval counter 201 generates a pulse while the refresh address recording unit 207 is cleared, the delayed refresh counter 202 does not count this time.

The refresh method provided by the embodiment of the present disclosure uses REFsb refresh request, and through the above method, it can combine a series of factors such as delayed refresh, refresh address prediction, command queue monitoring, etc. to form multi-level priority and arbitration logic, thereby taking into account the refresh of DRAM. And read and write access, on the basis of ensuring the timely completion of refresh, ensure the continuity of read and write access as much as possible, reduce the impact of refresh on DRAM performance, improve the bandwidth of memory access, and increase bandwidth utilization.

FIG. 5 is a schematic flowchart of another refreshing method for dynamic random access memory provided by some embodiments of the present disclosure. For example, in this embodiment, the method may include the following operations.

Step S10: Determine the states of multiple state machines corresponding to multiple storage queues, where multiple storage queues correspond to multiple state machines one-to-one;

Step S20: Determine multiple prediction addresses corresponding to multiple storage queues;

Step S40: Generate a blocking address based on the states of multiple state machines and multiple predicted addresses, and send the blocking address to the arbiter, so that the arbiter blocks the non-refresh command corresponding to the blocking address;

Step S30: Generate a refresh request based on the states of multiple state machines and multiple predicted addresses, and send the refresh request to the arbiter connected to the dynamic random access memory;

Step S50: In response to generating a refresh request, the flag bit of the refresh request indicating the first priority status, and the block corresponding to the request address being not completely free, generate a precharge request and send the precharge request to the arbiter.

In this embodiment, steps S10, S20 and S30 are basically the same as steps S10, S20 and S30 shown in Figure 3. For relevant descriptions, please refer to the foregoing content and will not be described again here.

Steps S40 and S50 will be exemplified below in conjunction with the refresh control module 107 shown in FIG. 2 .

For example, in step S40, the blocking address generation unit 206 generates a blocking address based on the states of the multiple state machines 203 and the multiple prediction addresses, and sends the blocking address to the arbiter 106, so that the arbiter 106 Non-refresh commands are blocked. For example, the address prediction unit 205 sends the predicted address to the blocking address generation unit 206 for use by the blocking address generation unit 206.

Further, in response to the state machine 203 being in the first priority state 302 and the corresponding storage queue having no refresh task being executed, the blocking address generation unit 206 determines the predicted address corresponding to the storage queue as the blocking address, and sets the blocking address Sent to arbiter 106.

It should be noted that although the refresh control module 107 includes multiple blocking address generation units 206 and each storage queue corresponds to one blocking address generation unit 206, only when the corresponding state machine 203 is in the first priority state 302 and corresponds to When there is no refresh task being executed in the storage queue, the corresponding blocking address generation unit 206 determines the corresponding predicted address as a blocking address and sends it to the arbiter 106 . The blocking address generation unit 206 corresponding to other storage queues that do not meet the requirements will not generate blocking addresses, that is, will not provide valid address information to avoid having at least two block addresses inaccessible in the same storage queue at the same time. situation arises. For example, if any block address is being refreshed in a certain storage queue, the corresponding blocking address generation unit 206 will not generate a blocking address, which can avoid having at least two block addresses in the same storage queue being unable to perform other operations at the same time. Memory access requests to avoid reducing bandwidth.

After receiving the blocking address, the arbiter 106 will block the non-refresh command (such as a memory access request) corresponding to the blocking address from participating in the arbitration of the arbiter 106, thereby providing timing and block status information for high-priority refresh requests to be sent as soon as possible. ensure. For example, in some examples, when the refresh control module 107 also generates a precharge request, the arbiter 106 blocks commands corresponding to the blocking address except for the precharge command and the refresh command. This can provide prerequisites for refresh and precharge, so that its block status and timing requirements can be achieved as soon as possible. When certain blocks are subject to a refresh request or are blocked target blocks, the arbiter 106 will temporarily remove these blocks from read-write switching, read-write statistics, command priority and other logic to avoid blocking other accesses. The operation of storage-related functional logic prevents blocks that cannot be read and written from interfering with other reading and writing.

In the refresh method provided by the embodiment of the present disclosure, by generating a blocking address to block the corresponding non-refresh command, high-priority refresh requests can win the arbitration of the arbiter 106 and reach the DRAM as soon as possible to ensure that the refresh is completed in time. .

For example, in some other examples, the blocking address can not be generated based on the predicted address, but the entire storage queue can be blocked, and then after the REFsb is sent out, memory access requests for other block addresses can be released. This can be determined according to actual needs. The embodiments of the present disclosure are not limited to this.

For example, in step S50, in response to generating a refresh request, the flag bit of the refresh request indicating the first priority state 302, and the block corresponding to the request address being not completely free, the request generation unit 204 generates a precharge request and sends the precharge request. To the arbiter 106, the precharge request corresponds to the block corresponding to the request address, and the address of the precharge request is the request address. For example, while generating a refresh request with a flag bit indicating the first priority state 302, if the corresponding block is in the open state, a precharge request (PCHGsb) needs to be issued, and PCHGsb will close the corresponding block in order to win the arbitration later. REFsb corresponding to this block can be executed.

In the refresh method provided by the embodiment of the present disclosure, by generating a precharge request, preparations can be made as soon as possible for the execution of a high-priority refresh request to ensure that the refresh is completed in time.

It should be noted that while generating a refresh request with a flag bit indicating the second priority state 303, if the corresponding block is in an open state, PCHGsb will not be generated. At this time, the flag bit indicates that the refresh request of the second priority state 303 will wait for the pre-charge module 109 to close the corresponding block, otherwise it will be accumulated until the first priority state 302 is reached. Low-priority refresh requests do not generate PCHGsb, which can prevent low-priority refreshes from interfering with future reading and writing processes. It can also achieve the effect of prioritizing reading and writing and increasing bandwidth.

At least one embodiment of the present disclosure also provides a memory controller for a dynamic random access memory. The memory controller has multi-level priority and arbitration logic and can take into account refresh and read and write access of the dynamic random access memory. On the basis of ensuring that the refresh is completed in time, the continuity of read and write access is ensured as much as possible, the impact of refresh on the performance of dynamic random access memory is reduced, the bandwidth of memory access is improved, and the bandwidth utilization rate is improved.

As shown in FIG. 1 and FIG. 2 , the memory controller 100 is configured to be connected to the DRAM and configured to control the DRAM to refresh. DRAM includes multiple storage queues, each storage queue includes multiple block groups, and each block group includes multiple blocks.

The memory controller 100 includes at least an arbiter 106 and a refresh control module 107 .

The refresh control module 107 includes a refresh interval counter 201, a plurality of delayed refresh counters 202, a plurality of state machines 203, a request generation unit 204, a plurality of address prediction units 205, a plurality of blocking address generation units 206 and a plurality of refresh address recording units 207 .

Multiple state machines 203 correspond to multiple storage queues one-to-one, and the state machines 203 are configured to switch between multiple states, such as the first priority state 302, the second priority state 303, the flush state 304, and the self-refresh state. Switch between 301. Multiple address prediction units 205 correspond to multiple storage queues on a one-to-one basis, and the address prediction units 205 are configured to determine predicted addresses of corresponding storage queues. The request generation unit 204 is configured to generate a refresh request based on the states of the plurality of state machines 203 and the predicted addresses, and send the refresh request to the arbiter 106 connected to the DRAM. Multiple blocking address generation units 206 correspond to multiple storage queues in a one-to-one manner. The blocking address generation unit 206 is configured to generate a blocking address based on the predicted address and the state of the state machine 203 of the storage queue corresponding to the predicted address, and send the blocking address to Arbiter 106.

The refresh interval counter 201 is configured to count cyclically, and when the count value reaches a count setting value, it generates a pulse and clears it, and sends pulses to multiple delayed refresh counters 202 . Multiple deferred refresh counters 202 correspond to multiple storage queues one-to-one, and the deferred refresh counters 202 are configured to count deferred refresh requests of the corresponding storage queue based on received pulses. The state machine 203 determines the state based on the value of the corresponding deferred refresh counter 202 . Multiple refresh address recording units 207 correspond to multiple storage queues one-to-one, and the refresh address recording units 207 are configured to record addresses of refreshed blocks.

The refresh control module 107 is connected to the arbiter 106, and the arbiter 106 is connected to the DRAM. The arbiter 106 is configured to arbitrate the refresh request, and in response to winning the arbitration for the refresh request, send the refresh request to the DRAM for implementing refresh of the DRAM. The arbiter 106 is also configured to block non-refresh commands corresponding to the blocked addresses.

It should be noted that in the embodiment of the present disclosure, the memory controller 100 may also include more modules and units, and the refresh control module 107 may also include more modules and units, which are not limited to those shown in Figures 1 and 2 modules and units, which can be determined according to actual needs, and the embodiments of the present disclosure do not limit this. For detailed description and technical effects of the memory controller 100, please refer to the above description of the refresh method, which will not be described again here.

At least one embodiment of the present disclosure further provides an electronic device, which includes the memory controller provided by any embodiment of the present disclosure. The memory controller in the electronic device has multi-level priority and arbitration logic, which can take into account the refresh and read and write access of the dynamic random access memory, and ensure the continuity of read and write access as much as possible on the basis of ensuring that the refresh is completed in time. , reduce the impact of refresh on the performance of dynamic random access memory, improve the bandwidth of memory access, and increase bandwidth utilization.

FIG. 6 is a schematic block diagram of an electronic device provided by some embodiments of the present disclosure. For example, as shown in FIG. 6 , the electronic device 200 includes a memory controller 100 . The memory controller 100 is a memory controller provided by any embodiment of the present disclosure, such as the memory controller 100 shown in FIG. 1 . For example, the electronic device 200 may further include a dynamic random access memory 210 . The memory controller 100 is configured to be connected to the dynamic random access memory 210 and configured to control the dynamic random access memory 210 to refresh. For example, the electronic device 200 can be implemented as a central processing unit (CPU) or any other device, and the embodiments of the present disclosure are not limited thereto.

It should be noted that in the embodiment of the present disclosure, the electronic device 200 may also include more modules and units, which are not limited to the modules and units shown in FIG. 6 . This may be determined according to actual needs. The embodiment of the present disclosure There are no restrictions on this. For detailed descriptions and technical effects of the electronic device 200, please refer to the above descriptions of the refresh method and the memory controller, and will not be described again here.

The following points need to be explained:

(1) The drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure, and other structures can refer to common designs.

(2) Without conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims (19)

1. A refresh method for a dynamic random access memory, wherein the dynamic random access memory comprises a plurality of storage queues, each storage queue comprising a plurality of block groups, each block group comprising a plurality of blocks, the method comprising:

Determining states of a plurality of state machines corresponding to the plurality of storage queues, wherein the plurality of storage queues are in one-to-one correspondence with the plurality of state machines;

determining a plurality of predicted addresses corresponding to the plurality of storage queues, wherein the predicted addresses are block addresses of a next block refresh request of a predicted current storage queue;

based on the states of the state machines and the predicted addresses, a refresh request is generated and sent to an arbiter coupled to the dynamic random access memory, such that the arbiter arbitrates the refresh request and, in response to the refresh request, wins the arbitration, sends the refresh request to the dynamic random access memory for implementing the refresh of the dynamic random access memory.

2. The method of claim 1, wherein determining states of a plurality of state machines corresponding to the plurality of store queues comprises:

for each state machine, determining the state of the state machine according to the value of the deferred refresh counter, the self-refresh entry request, and the self-refresh exit command.

3. The method of claim 2, wherein the state machine comprises 4 states: a first priority state, a second priority state, a flush state, and a self-refresh state,

The first priority state has a higher priority than the second priority state.

4. The method of claim 3, wherein for each state machine, determining the state of the state machine from the value of the deferred refresh counter, the self-refresh entry request, and the self-refresh exit command comprises:

responsive to the deferred refresh counter having a value greater than or equal to a threshold, causing the state machine to enter the first priority state;

responsive to the value of the deferred refresh counter being less than the threshold, causing the state machine to enter the second priority state;

responsive to the self-refresh entry request, causing the state machine to enter the flush state immediately or with a delay in accordance with a current state of the state machine;

responsive to completion of an operation corresponding to the flush state, causing the state machine to enter the self-refresh state;

and in response to the self-refresh exit command, enabling the state machine to enter the first priority state or the second priority state according to the value of the deferred refresh counter.

5. The method of claim 4, wherein responsive to the self-refresh entry request, causing the state machine to enter the flush state immediately or with a delay in accordance with a current state of the state machine comprises:

In response to the self-refresh entry request, in a case where the state machine is in the first priority state, causing the state machine to maintain the first priority state until the deferred refresh counter value is less than the threshold value to reenter the flush state;

in response to the self-refresh entry request, causing the state machine to enter the flush state in a case where the state machine is in the second priority state and no address is recorded in a refresh address recording unit;

in response to the self-refresh entry request, in a case where the state machine is in the second priority state and there is a recorded address in the refresh address recording unit, causing the state machine to maintain the second priority state until no recorded address in the refresh address recording unit reenters the flush state.

6. The method of any of claims 3-5, wherein determining the plurality of predicted addresses corresponding to the plurality of store queues comprises:

for each storage queue, determining the prediction address based on block information and the state of a state machine corresponding to the storage queue.

7. The method of claim 6, wherein for each store queue, determining the predicted address based on the block information and a state of a state machine to which the store queue corresponds comprises:

Determining the addresses of the blocks meeting the requirements as the predicted addresses according to the priority sequence from the first level to the N level in response to the state machine being in the first priority state and no refresh task being executed in the corresponding storage queue;

determining the addresses of the blocks meeting the requirements as the predicted addresses according to the priority sequence from the first level to the Mth level in response to the state machine being in the second priority state and no refresh task being executed in the corresponding storage queue;

determining that the predicted address is empty in response to the state machine being in the first priority state and there being an executing refresh task in a corresponding storage queue;

determining that the predicted address is empty in response to the state machine being in the second priority state and there being no block meeting a requirement or a refresh task being performed in a corresponding store queue;

wherein N > M >1 and N and M are integers, the priority order from the first level to the N level is gradually reduced,

the priority order of each level is determined based on the block information, and the block information at least comprises: whether valid, whether refreshed, whether there is a memory access request, whether idle, and whether timing is in compliance.

8. The method of any of claims 3-5, further comprising:

and generating a blocking address based on the states of the state machines and the predicted addresses, and sending the blocking address to the arbiter so that the arbiter blocks a non-refresh command corresponding to the blocking address.

9. The method of claim 8, wherein generating the blocking address and sending the blocking address to the arbiter based on the states of the plurality of state machines and the plurality of predicted addresses comprises:

and in response to the state machine being in the first priority state and no executing refreshing task in the corresponding storage queue, determining a predicted address corresponding to the storage queue as the blocking address, and sending the blocking address to the arbiter.

10. The method of claim 4 or 5, wherein generating the refresh request based on the states of the plurality of state machines and the plurality of predicted addresses and sending the refresh request to the arbiter coupled to the dynamic random access memory comprises:

selecting a storage queue and generating the refresh request according to a priority selection rule based on states of the plurality of state machines, and transmitting the refresh request to the arbiter;

The refresh request comprises a request command, a request address and a flag bit, wherein the request address is a predicted address corresponding to the selected storage queue, and the flag bit indicates that a state machine corresponding to the selected storage queue is in the first priority state or the second priority state.

11. The method of claim 10, wherein the first priority state comprises a first sub-state and a second sub-state, the first sub-state having a higher priority than the second sub-state, the first sub-state being that the deferred refresh counter reaches a maximum value, the second sub-state being that the deferred refresh counter is less than the maximum value and greater than or equal to the threshold value;

the priority selection rule is:

selecting a corresponding storage queue according to the priority order of the first sub-state, the second sub-state and the second priority state,

if all state machines are in the second priority state, selecting a store queue whose predicted address is not empty,

if a plurality of state machines with the same priority order exist, randomly selecting a storage queue corresponding to one state machine from the plurality of state machines with the same priority order.

12. The method of claim 10, further comprising:

generating a precharge request and sending the precharge request to the arbiter in response to the generation of the refresh request, the flag bit of the refresh request indicating that the first priority state and the block corresponding to the request address are not fully idle;

wherein the precharge request corresponds to a block corresponding to the request address.

13. The method of claim 12, wherein the arbiter is further configured to arbitrate read and write requests, row strobe requests, the precharge requests,

the priority of arbitration is reduced in the following order: the flag bit indicates a refresh request of the first priority state, the read-write request, the row strobe request, the precharge request, and the flag bit indicates a refresh request of the second priority state.

14. A memory controller for a dynamic random access memory, wherein the memory controller is configured to be coupled to the dynamic random access memory and configured to control refresh of the dynamic random access memory, the dynamic random access memory comprising a plurality of memory queues, each memory queue comprising a plurality of block groups, each block group comprising a plurality of blocks;

The memory controller comprises a refresh control module, wherein the refresh control module comprises a plurality of state machines, a plurality of address prediction units and a request generation unit;

the plurality of state machines are in one-to-one correspondence with the plurality of storage queues, and the state machines are configured to switch among a plurality of states;

the plurality of address prediction units are in one-to-one correspondence with the plurality of storage queues, and the address prediction units are configured to determine the predicted addresses of the corresponding storage queues, wherein the predicted addresses are block addresses of a next block refresh request of the current storage queue to be predicted;

the request generation unit is configured to generate a refresh request based on states of the plurality of state machines and the predicted address, and to send the refresh request to an arbiter connected to the dynamic random access memory.

15. The memory controller of claim 14, further comprising the arbiter,

wherein the refresh control module is coupled to the arbiter, the arbiter is coupled to the dynamic random access memory,

the arbiter is configured to arbitrate the refresh request and to win arbitration in response to the refresh request, send the refresh request to the dynamic random access memory for effecting refresh of the dynamic random access memory.

16. The memory controller of claim 14 or 15, wherein the refresh control module further comprises a plurality of barrier address generation units;

the plurality of blocking address generating units are in one-to-one correspondence with the plurality of storage queues, and are configured to generate blocking addresses based on the predicted addresses and states of state machines of the storage queues corresponding to the predicted addresses, and send the blocking addresses to the arbiter;

the arbiter is further configured to block non-refresh commands corresponding to the blocking address.

17. The memory controller of claim 14 or 15, wherein the refresh control module further comprises a refresh interval counter, a plurality of deferred refresh counters, and a plurality of refresh address logging units;

the refresh interval counter is configured to cycle count and generate and empty a pulse when the count value reaches a count set value and send the pulse to the plurality of deferred refresh counters;

the plurality of deferred refresh counters are in one-to-one correspondence with the plurality of storage queues, the deferred refresh counters are configured to count deferred refresh requests of the storage queues corresponding to the received pulses, and the state machine determines a state based on the values of the corresponding deferred refresh counters;

The refresh address recording units are in one-to-one correspondence with the storage queues and are configured to record addresses of the refreshed blocks.

18. An electronic device comprising a memory controller as claimed in any one of claims 14 to 17.

19. The electronic device of claim 18, further comprising the dynamic random access memory.