CN105489240A - DRAM or eDRAM refreshing apparatus and method - Google Patents

Abstract

The invention discloses a DRAM or eDRAM refreshing apparatus and method. The method comprises the steps that step 1, a storage control apparatus receives a reading-writing request and determines to send the reading-writing request or a refreshing request to a storage apparatus according to an output of a refreshing control apparatus; and step 2, the refreshing control apparatus generates a refreshing signal by control and records whether the refreshing is delayed or not according to an output of the storage control apparatus. According to the DRAM or eDRAM refreshing apparatus and method, the conflicts between the reading-writing and the refreshing can be reduced and the effect of improving the DRAM or eDRAM performance can be achieved.

Description

A device and method for refreshing DRAM or eDRAM

technical field

The invention relates to refreshing technology, in particular to a device and method for refreshing DRAM or eDRAM.

Background technique

In the traditional centralized refresh method, there will be a period of time for refreshing in each refresh cycle. As shown in Figure 1, in each refresh cycle, the time axis is divided into two parts, and part of the time is used for reading and writing. , and the other part of the time is spent refreshing.

In the existing refresh method, when DRAM is being refreshed, read and write operations cannot be performed, which is called dead time, which reduces the throughput of DRAM, and the delay of reading and writing will become very high.

Contents of the invention

The object of the present invention is to provide a device and method for refreshing DRAM or eDRAM, which are used to reduce conflicts between refreshing and reading and writing, and achieve the effect of increasing the performance of DRAM or eDRAM.

In order to achieve the above object, the present invention provides a device for refreshing DRAM or eDRAM. DRAM or eDRAM is provided with a storage unit, and the device includes: a storage control device and a refresh control device;

The storage control device is configured to receive a read-write request, and decide to send a read-write request or a refresh request to the storage unit according to the output of the refresh control device;

The refresh control device is used to control the generation of a refresh signal, and record whether the refresh is delayed according to the output of the storage control device.

The device for refreshing DRAM or eDRAM, wherein the storage control device includes:

Read cache, for caching data read from the storage unit;

Write cache, for caching data to be written to the storage unit;

a control logic unit, configured to receive read and write requests;

The storage control signal generator is used for receiving the command sent by the control logic unit, and decoding the command into a command recognizable by the storage unit.

The device for refreshing DRAM or eDRAM, wherein the refresh control device includes:

The refresh cycle register is used to store the refresh cycle;

The refresh delay counter is used to store the time when the current refresh is delayed;

Refresh cycle timer for timing each refresh cycle;

Refresh the number of rows counter, used to record the number of rows currently refreshed;

Refresh logic unit, for judging the current reading and writing state of the register, and sending the refresh state to the control logic unit;

The total number of rows register is used to store the total number of rows;

The refresh delay register is used to store the total refresh delay time.

The device for refreshing DRAM or eDRAM, wherein, when the refresh logic unit receives a read/write request, it stops refreshing, controls the refresh delay counter to start counting, and sends a signal indicating whether the current refresh can be interrupted to the control logic unit.

The device for refreshing DRAM or eDRAM, wherein the refresh logic unit is not completed in the current refresh, and when the time in the refresh delay counter is equal to the time in the refresh delay register, return a current refresh A signal that cannot be interrupted is sent to the control logic unit to control the control logic unit to continue refreshing; or when the current refresh is completed or the time difference between the refresh delay register and the refresh delay counter is greater than the total number of rows When the difference between the number of rows in the register and the refresh row counter is multiplied by the refresh time of each row, a signal that can be read and written is returned to the control logic unit.

The device for refreshing DRAM or eDRAM, wherein, when the time in the refresh cycle timer is equal to the time in the refresh cycle register, the refresh cycle timer, the refresh row number counter, the The refresh delay counter described above is reset to zero.

In the device for refreshing DRAM or eDRAM, the sum of the refresh period of the refresh period register and the delayed time of the refresh delay counter is less than the data retention time.

In the device for refreshing DRAM or eDRAM, there are one or more refresh control devices, and the refresh between the refresh control devices is independent of each other.

In order to achieve the above object, the present invention provides a method for refreshing a DRAM or eDRAM, where the DRAM or eDRAM is provided with a storage unit, the method comprising:

Step 1, the storage control device receives the read-write request, and decides to send a read-write request or a refresh request to the storage unit according to the output of the refresh control device;

In step 2, the refresh control device controls the generation of a refresh signal, and records whether the refresh is delayed according to the output of the storage control device.

The method for refreshing DRAM or eDRAM, wherein the refresh control device includes:

The refresh cycle register is used to store the refresh cycle;

The refresh delay counter is used to store the time when the current refresh is delayed;

Refresh cycle timer for timing each refresh cycle;

Refresh the number of rows counter, used to record the number of rows currently refreshed;

Refresh logic unit, for judging the current reading and writing state of the register, and sending the refresh state to the control logic unit;

The total number of rows register is used to store the total number of rows;

The refresh delay register is used to store the total refresh delay time.

The method for refreshing DRAM or eDRAM, wherein, in the second step, comprising:

When receiving a read/write request, the refresh logic unit stops refreshing, controls the refresh delay counter to start counting, and sends a signal whether the current refresh can be interrupted to the control logic unit of the storage control device.

The method for refreshing DRAM or eDRAM, wherein, in the second step, comprising:

The refresh logic unit is not completed in the current refresh, and when the time in the refresh delay counter is equal to the time in the refresh delay register, return a signal that the current refresh cannot be interrupted to the control logic unit, and control The control logic unit continues to refresh; or when the current refresh is completed or the time difference between the refresh delay register and the refresh delay counter is greater than the row number difference between the total row number register and the refresh row number counter When the product is multiplied by the refresh time of each row, a signal that can be read and written is returned to the control logic unit.

The method for refreshing DRAM or eDRAM, wherein, in the second step, comprising:

When the time in the refresh cycle timer is equal to the time in the refresh cycle register, the refresh cycle timer, the refresh row number counter, and the refresh delay counter are reset to zero.

In the method for refreshing DRAM or eDRAM, the sum of the refresh period of the refresh period register and the delayed time of the refresh delay counter is less than the data retention time.

The method for refreshing a DRAM or eDRAM, wherein there are one or more refresh control devices, and the refresh between the refresh control devices is independent of each other.

Compared with the prior art, the beneficial technical effect of the present invention is:

The invention provides a method for refreshing DRAM or eDRAM. This refreshing method improves the way of centralized refreshing, makes refreshing more flexible, and coordinates refreshing and reading and writing conflicts, thereby improving the throughput of DRAM and realizing DRAM Performance improvements. Specifically reflected in the following aspects:

1. Through the interruptible centralized refreshing method, the conflict between refreshing and reading and writing is reduced, and the effect of increasing the performance of DRAM or eDRAM is achieved.

2. During centralized refreshing, it can be interrupted by reading and writing, which reduces the delay of reading and writing.

3. The sum of the refresh period and the refresh delay time must be set to be less than the data retention time.

4. It can be interrupted by reading and writing during centralized refresh.

5. There can be a set of refreshing devices, or multiple block banks can share a set of refreshing devices, or each block bank can have a set of refreshing devices exclusively.

Description of drawings

Figure 1 is a schematic diagram of a traditional centralized refresh method;

Fig. 2 is a schematic diagram of the refresh mode of the present invention;

Fig. 3 is a structural diagram of the refreshing device of the present invention;

Fig. 4 is a flowchart of the refreshing method of the present invention;

Fig. 5 is the first embodiment of the refresh mode of the present invention;

FIG. 6 is a second embodiment of the refresh mode of the present invention.

detailed description

The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the present invention.

As shown in FIG. 2 , it is a schematic diagram of the refreshing method of the present invention. FIG. 2 shows the refresh sequence, the DRAM refresh circuit sets the refresh cycle to be shorter than the data retention time. In each refresh cycle, the time domain is divided into three parts. The first part is called the centralized refresh time, and the centralized refresh is performed in the first part, but when there are read and write operations, the centralized refresh can be interrupted, and the read and write operations are prioritized; the second Part is called the delayed refresh time. At the beginning of the second part, reading and writing are also given priority, but when the rest of the second part is just able to complete the refresh operation, the forced refresh operation will be performed, and the read and write requests will not be responded at this time. The third part is called read and write time, and only read and write operations are performed in this part. The refresh method can be used in a DRAM or eDRAM controller, and the technical solution will be described below taking the DRAM controller as an example, which is also applicable to the eDRAM controller.

DRAM is manufactured by MOS technology and uses capacitors as storage units (for eDRAM controllers, capacitors are also used as storage units). DRAM has low power consumption and is slow. On the other hand, SRAM is fast and does not need to be refreshed, however, the area of SRAM is too large and more expensive, so DRAM is more widely used than SRAM.

Unlike SRAM, which uses flip-flops to store information, DRAM uses capacitors to store information. But the capacitor will gradually leak and lose data. Therefore, the storage unit of the DRAM needs to be periodically refreshed, and the refresh cycle is shorter than the data retention time. If the storage unit is not refreshed within the data retention time, the stored information will be lost.

As shown in FIG. 3 , it is a structural diagram of the refreshing device of the present invention, and FIG. 4 is a flow chart of the refreshing method of the present invention.

Referring to FIGS. 3 and 4 , the refreshing device 300 is a device for refreshing DRAM or eDRAM, and includes a storage control device 31 and a refresh control device 32 . DRAM or eDRAM includes storage unit 33 .

The refresh control device 32 is used to control the generation of refresh signals, and the storage control device 31 is used to receive read and write requests and send refresh requests or read and write requests to the storage unit 33. The unit 33 sends a read/write request or a refresh request, and the refresh control device 32 records whether the refresh is delayed according to the output of the storage control device 31 .

Further, the storage control device 31 includes:

The read cache 1 is used to cache data read from the storage unit 33 .

The write buffer 2 is used for buffering data to be written into the storage unit 33 .

The control logic unit 3 is configured to receive read and write requests and send commands to the storage unit control signal generator 4 .

The storage control signal generator 4 is used to decode the command sent by the control logic unit 3 into a command that the storage unit 33 can recognize.

Further, the refresh control device 32 is used as a block bank, and the device 300 may include multiple block banks.

Further, the refresh control device 32 includes:

Refresh period register 5, used to store the refresh period.

Refresh delay counter 6 is used to store the time when the current centralized refresh has been delayed.

The refresh cycle timer 7 is used for recording the time of the current refresh cycle and timing each refresh cycle.

Refresh row count counter 8 is used to record the current refresh progress, such as the current refresh row number.

The refresh logic unit 9 sends the refresh status to the control logic unit 3 by judging several registers related to refresh (that is, judging whether they can be read or written currently).

The total number of rows register 10 is used to store the total number of rows in a bank.

Refresh delay register 11 is used to store the total refresh delay time.

Further, the refresh period stored in the refresh period register 5 is less than the data retention time.

Further, the refresh delay register 11 stores the time that the refresh can be delayed, and the following condition must be met: the sum of the refresh cycle and the time that the refresh can be delayed is less than or equal to the data retention time.

In the present invention, there is only one group of refreshing devices in total, and the refreshing operations of all blocks are the same. The refresh logic unit 9 sends to the control logic unit 3 by judging the status of each refresh register. Refresh row number counter 8 counts the number of rows refreshed by the block bank, and refresh delay counter 11 counts the delay time during refresh. During centralized refresh, if there is a read and write request, the refresh is interrupted, and refresh delay counter 6 starts count. The refresh logic unit 9 sends a signal to the control logic unit 3 whether the current refresh can be interrupted, if the current refresh is not completed, and the refresh delay counter 6 is equal to the refresh delay register 11, then the refresh logic unit 9 returns a signal that the refresh cannot be interrupted , and the control logic unit 3 continues to refresh the remaining rows. If the refresh is completed, or the time in the refresh delay counter 6 is less than the time in the refresh delay register 11, then the refresh logic unit 9 returns a signal that can be read and written. The refresh period register 5 stores the time of the refresh period, and the refresh period timer 7 starts counting all the time. When the refresh period timer 7 is equal to the refresh period, it means that the next refresh period is reached, the refresh period timer 7, the refresh line counter 8, and the refresh period The delay counter 6 is reset to zero.

Please refer to Figures 3 and 4. The working process of the DRAM refresh circuit is introduced in detail in conjunction with Figure 3 below:

The initialization register, the refresh period register 5 stores the refresh period of the DRAM, the total number of rows register 10 stores the number of rows of a block bank of the DRAM, and the refresh delay register 11 stores the time that the refresh can be delayed during centralized refresh. Wherein, refresh delay time+refresh cycle<=data retention time of the storage unit 33, the above-mentioned registers need to be configured in advance before normal operation.

The control logic unit 3 is used to receive and execute external commands. Before accessing the storage unit 33, the control logic unit 3 checks the signal returned by the refresh logic unit 9. If it is in the refresh state, it does not execute it, otherwise it executes.

When entering the centralized refresh time, if the control logic unit 3 needs to access the storage unit 33, the refresh logic unit 9 needs to judge whether the current refresh can be interrupted, if the time difference between the refresh delay register 11 and the refresh delay counter 6 is greater than the total number of rows When the product of the row number difference in the register 10 and the refresh row number counter 8 and the refresh time of each row, the current refresh can be interrupted, and the control logic unit 3 starts to access the storage unit 33, and the refresh delay counter 6 starts counting and the refresh is interrupted simultaneously. Delay time.

The refresh cycle timer 7 is always counting. If the refresh cycle timer 7 is equal to the refresh cycle register 5, it means that the next refresh cycle is reached, and the refresh cycle timer 5, the refresh row number counter 8, and the refresh delay counter 6 are reset to zero. As shown in FIG. 5 , it is the first embodiment of the refresh mode of the present invention.

In this embodiment, each block bank has its own independent refreshing device, and the refreshing between each block bank is independent of each other. Each block bank has its own refresh device. When a block bank is interrupted during the centralized refresh time, it will not affect the refresh of other block banks.

As shown in FIG. 6, it is the second embodiment of the refreshing method of the present invention.

In this embodiment, all block banks are divided into M groups, each group has N block banks, and each group has an independent refreshing device, and the refreshing between each group is independent of each other. As shown in the figure above, each group has its own refresh device. When a group is interrupted during the centralized refresh time, it will not affect the refresh of other groups.

Further, there is only one refresh device in a DRAM or eDRAM controller.

Further, all the blocks Bank share a refresh device, and the refresh status of all the block banks is exactly the same.

Further, each block bank has its own refreshing device, and the refreshing of each block bank is independent of each other.

Further, several block banks can be divided into one group, and each group of block banks has a refreshing device.

Furthermore, each group of block banks has its own refresh device, the refresh status of the block banks in each group is exactly the same, and the refresh between groups is independent of each other.

The invention improves the mode of centralized refreshing to make the refreshing more flexible, can effectively coordinate the conflict between reading and writing and refreshing, improves the throughput of the DRAM, and thus improves the performance of the DRAM.

Of course, the present invention can also have other various embodiments, and those skilled in the art can make various corresponding changes and deformations according to the present invention without departing from the spirit and essence of the present invention. All changes and deformations should belong to the protection scope of the appended claims of the present invention.

Claims (15)

1., for the device that DRAM or eDRAM refreshes, DRAM or eDRAM is provided with storage unit, it is characterized in that, this device comprises: memory control device, refresh control device;

Described memory control device, for receiving read-write requests, and determines to send read-write requests or refresh requests to storage unit according to the output of described refresh control device;

Whether described refresh control device, generate refresh signal for controlling, and record refreshing according to the output of described memory control device and be delayed by.

2. the device refreshed for DRAM or eDRAM according to claim 1, it is characterized in that, described memory control device comprises:

Read buffer memory, for the data that buffer memory reads from storage unit;

Write buffer memory, the data of storage unit will be written to for buffer memory;

Steering logic unit, for receiving read-write requests;

Storage control signal generator, for receiving the order that described steering logic unit sends, and becomes the discernible order of storage unit by this command decoder.

3. the device refreshed for DRAM or eDRAM according to claim 2, it is characterized in that, described refresh control device comprises:

Refresh cycle register, for storing the refresh cycle;

Refresh delay counter, for storing the time that current refreshing is delayed by;

Refresh cycle timer, for the timing of each refresh cycle;

Refreshed rows counter, for recording the line number of current refreshing;

Flush logic unit, for judge register current by read-write state, and send the state refreshed to described steering logic unit;

Head office's number register, for storing total line number;

Refresh delay register, refreshes total time be delayed by for storing.

4. the device refreshed for DRAM or eDRAM according to claim 3, it is characterized in that, described flush logic unit is when receiving read-write requests, stop refreshing, control described refresh delay counter and start counting, and send current refreshing whether can by the signal extremely described steering logic unit interrupted.

5. the device refreshed for DRAM or eDRAM according to claim 4, it is characterized in that, described flush logic unit does not complete in current refreshing, and when the time in described refresh delay counter equals the time in described refresh delay register, return a current refreshing by the signal extremely described steering logic unit interrupted, described steering logic unit to be controlled and continue to refresh; Or when current refreshing has completed or time difference in described refresh delay register and described refresh delay counter is greater than product with every row refresh time of line number difference in described head office number register and described refreshed rows counter, returning one can by the signal read and write to described steering logic unit.

6. the device refreshed for DRAM or eDRAM according to claim 3, it is characterized in that, when the time in described refresh cycle timer equals the time in described refresh cycle register, described refresh cycle timer, described refreshed rows counter, described refresh delay counter clear.

7. the device refreshed for DRAM or eDRAM according to claim 3, it is characterized in that, the refresh cycle of described refresh cycle register and the time sum be delayed by of described refresh delay counter are less than data hold time.

8., according to the described device refreshed for DRAM or eDRAM arbitrary in claim 1-7, it is characterized in that, described refresh control device is one or more, and the refreshing between each described refresh control device is separate.

9., for the method that DRAM or eDRAM refreshes, DRAM or eDRAM is provided with storage unit, it is characterized in that, the method comprises:

Step one, memory control device receives read-write requests, and determines to send read-write requests or refresh requests to storage unit according to the output of refresh control device;

Step 2, whether refresh control device controls to generate refresh signal, and record refreshing according to the output of described memory control device and be delayed by.

10. the method refreshed for DRAM or eDRAM according to claim 9, it is characterized in that, described refresh control device comprises:

Refresh cycle register, for storing the refresh cycle;

Refresh delay counter, for storing the time that current refreshing is delayed by;

Refresh cycle timer, for the timing of each refresh cycle;

Refreshed rows counter, for recording the line number of current refreshing;

Flush logic unit, for judge register current by read-write state, and send the state refreshed to described steering logic unit;

Head office's number register, for storing total line number;

Refresh delay register, refreshes total time be delayed by for storing.

11. methods refreshed for DRAM or eDRAM according to claim 10, is characterized in that, in described step 2, comprising:

Described flush logic unit, when receiving read-write requests, stops refreshing, and controls described refresh delay counter and starts counting, and send current refreshing whether can by the signal that interrupts to the steering logic unit of described memory control device.

12. methods refreshed for DRAM or eDRAM according to claim 11, is characterized in that, in described step 2, comprising:

Described flush logic unit does not complete in current refreshing, and when the time in described refresh delay counter equals the time in described refresh delay register, return a current refreshing by the signal extremely described steering logic unit interrupted, described steering logic unit to be controlled and continue to refresh; Or when current refreshing has completed or time difference in described refresh delay register and described refresh delay counter is greater than product with every row refresh time of line number difference in described head office number register and described refreshed rows counter, returning one can by the signal read and write to described steering logic unit.

13. methods refreshed for DRAM or eDRAM according to claim 10, is characterized in that, in described step 2, comprising:

When the time in described refresh cycle timer equals the time in described refresh cycle register, described refresh cycle timer, described refreshed rows counter, described refresh delay counter clear.

14. methods refreshed for DRAM or eDRAM according to claim 10, it is characterized in that, the refresh cycle of described refresh cycle register and the time sum be delayed by of described refresh delay counter are less than data hold time.

15. according to the described method refreshed for DRAM or eDRAM arbitrary in claim 9-14, and it is characterized in that, described refresh control device is one or more, and the refreshing between each described refresh control device is separate.