CN112257384A - Standard cell detection method - Google Patents
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- CN112257384A CN112257384A CN202011191795.0A CN202011191795A CN112257384A CN 112257384 A CN112257384 A CN 112257384A CN 202011191795 A CN202011191795 A CN 202011191795A CN 112257384 A CN112257384 A CN 112257384A
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- 238000012360 testing method Methods 0.000 claims abstract description 38
- 238000003860 storage Methods 0.000 claims description 9
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- 238000010998 test method Methods 0.000 claims 1
- 238000011156 evaluation Methods 0.000 description 38
- 239000011295 pitch Substances 0.000 description 14
- 238000004804 winding Methods 0.000 description 11
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- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
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Abstract
一种标准单元的检测方法，适用于检测标准单元。该标准单元的检测方法包括获取第一标准单元、第二标准单元以及第三标准单元；将第一标准单元、第二标准单元以及第三标准单元组合为测试单元；对测试单元进行布线；判断第一标准单元是否会导致违反设计规则；当第一标准单元会导致违反所述设计规则时，调整第一标准单元与第二标准单元以及第三标准单元之间的间距；以及当第一标准单元不会导致违反所述设计规则时，直接使用第一标准单元所属的第一类标准单元。
A detection method for standard units, which is suitable for detecting standard units. The detection method of the standard unit includes acquiring a first standard unit, a second standard unit and a third standard unit; combining the first standard unit, the second standard unit and the third standard unit into a test unit; wiring the test unit; Whether the first standard cell would lead to a violation of the design rule; when the first standard cell would lead to a violation of the design rule, adjust the spacing between the first standard cell and the second standard cell and the third standard cell; and when the first standard cell When the cell does not cause violation of the design rule, the first type of standard cell to which the first standard cell belongs is directly used.
Description
Technical Field
The present invention relates to a method for detecting a standard cell, and more particularly, to a method for detecting a winding capability of a standard cell.
Background
The main steps of automatic layout and routing of digital integrated circuit back-end design usually include floor placement (floor plan), placement (placement), Clock Tree Synthesis (Clock Tree Synthesis), routing (routing) and optimization. After a circuit Design is subjected to the routing step, the Design Rule (DR) of the Design is checked, and after the Design Rule is found to be easily violated by some units through artificial analysis, the units are forbidden to be redesigned from the beginning. A circuit design often needs to go through such a process of iterative operations to troubleshoot the problematic cells.
Because the design is increasingly complex, the time required for completing automatic layout and wiring is often over 300 hours, the time required for one iteration is at least over 600 hours, and manual analysis is not necessarily accurate and very time-consuming, so that the winding capacity of the standard cells needs to be evaluated before the standard cells are put into use, and the standard cells with insufficient winding capacity are corrected or directly disabled.
Disclosure of Invention
In view of the above, the present invention provides a method for detecting a standard cell, which is suitable for detecting the standard cell. The standard cell detection method comprises the steps of obtaining a first standard cell, a second standard cell and a third standard cell; combining the first standard cell, the second standard cell and the third standard cell into a test cell; wiring the test unit; judging whether the first standard cell can cause the violation of the design rule or not; adjusting the spacing between the first standard cell and the second standard cell and the third standard cell when the first standard cell would cause a violation of the design rule; and directly using the first standard cell belonging to the first standard cell when the first standard cell does not cause violation of the design rule.
The detection method provided by the invention is beneficial to evaluating the winding capacity of the standard cell and correcting or forbidding the winding capacity before automatic layout and wiring, so that the standard cell can be correctly used and the standard cell which is easy to violate the design rule can be avoided when the placing step of automatic layout and wiring is carried out, the iteration times of automatic layout and wiring are reduced, and the time required by design is greatly shortened.
In addition, the detection method provided by the invention has foresight on the winding capacity of the standard unit, and the use suggestion can be made for the standard unit before the standard unit is put into use. In addition, all standard cells with winding problems are not forbidden, and new use suggestions are provided, so that the selectivity of the standard cells is stronger. The invention further provides an electronic computing device, which includes a storage medium and a processor. The storage medium is used for storing a computer program. The processor calls the computer program to execute a standard cell detection method. The standard cell detection method comprises the steps of obtaining a first standard cell, a second standard cell and a third standard cell; combining the first standard cell, the second standard cell and the third standard cell into a test cell; wiring the test unit; judging whether the first standard cell can cause the violation of the design rule or not; adjusting the spacing between the first standard cell and the second standard cell and the third standard cell when the first standard cell would cause the design rule to be violated; and when the first standard cell does not cause violation of the design rule, directly using the first standard cell belonging to the first class standard cell.
Drawings
FIG. 1 is a flow chart of a detection method 100 according to an embodiment of the invention;
FIGS. 2A-2B are schematic diagrams of a test unit 200 according to an embodiment of the invention;
FIGS. 3A-3B are schematic diagrams of a test unit 300 according to another embodiment of the invention; and
fig. 4 is a block diagram of an electronic computing device 400 according to an embodiment of the invention.
Detailed Description
The following description is an example of the present invention. The general principles of the present invention are intended to be illustrative, but not limiting, of the scope of the invention, which is defined by the claims.
It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms, and these terms are only used to distinguish one element, component, region, layer and/or section from another element, component, region, layer and/or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of some embodiments of the present disclosure.
It is noted that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. The particular examples and arrangements of components set forth below are presented for illustrative purposes only and are not intended to limit the scope of the present invention. Moreover, the following description may repeat reference numerals and/or letters in the various examples. However, this repetition is for the purpose of providing a simplified and clear illustration only and is not intended to limit the scope of the various embodiments and/or configurations discussed below. Moreover, the description below of one feature connected to, coupled to, and/or formed on another feature, and the like, may actually encompass a variety of different embodiments that include the feature in direct contact, or that include other additional features formed between the features, and the like, such that the features are not in direct contact.
Fig. 1 is a flowchart of a detection method 300 according to an embodiment of the invention. As shown in FIG. 1, the detection method 100 is suitable for evaluating a standard cell within a library of standard cells. According to an embodiment of the present invention, the standard cell library is used to store a plurality of types of digital standard cells, and the detection method 100 is used to evaluate whether the digital standard cells in the standard cell library violate the design rule, so as to be modified or disabled.
As shown in fig. 1, step S101 is first executed to obtain a first type standard cell from the standard cell library, that is, the first type standard cell is used as a target cell for evaluation, which is hereinafter referred to as a target evaluation cell. Next, step S102 is executed to obtain at least one second-type standard cell from the standard cell library, and combine the target evaluation unit and the at least one second-type standard cell into a test unit.
Fig. 2A-2B are schematic diagrams of a test unit 200 according to an embodiment of the invention. As shown in FIG. 2A, the test unit 200 comprises a target evaluation unit 211, a second type standard cell 212 and another second type standard cell 213, and the target evaluation unit 211, the second type standard cell 212 and the second type standard cell 213 are arranged along a first direction as shown by F in FIG. 2A. As shown in fig. 2A, the target evaluation unit 211 is disposed between the second type standard cell 212 and the second type standard cell 213, and the second type standard cell 212 and the second type standard cell 213 are respectively disposed at two sides of the target evaluation unit 211.
As shown in FIG. 2B at F, the target evaluation unit 211 is placed in a first direction, and the second-type standard cells 212 and 213 are placed in a second direction, for example, the first direction mirror-rotated by 180 degrees. In other words, the first-type standard cell 211 as the target evaluation unit is located in the middle without any rotation, the directions (or angles) of the second-type standard cells 212 and the second-type standard cells 213 with respect to the first-type standard cells 211 are changed, and the second-type standard cells 212 and the second-type standard cells 213 are still disposed on both sides of the first-type standard cells 211. According to an embodiment of the present invention, the detection method 100 is performed by the test units 200 shown in fig. 2A and 2B individually or sequentially.
Fig. 3A-3B are schematic diagrams of a test unit 500 according to another embodiment of the invention. According to other embodiments of the present invention, in step S102, one first-type standard cell as the target evaluation unit and at least one other first-type standard cell in the standard cell library may be combined into a test cell.
As shown in fig. 3A, the test unit 500 includes a target evaluation unit 311, a first type standard cell 312, and a first type standard cell 313. As shown in FIG. 3A by F, the target evaluation unit 311, a first-type standard cell 312, and another first-type standard cell 313 are placed in a first direction. As shown in fig. 3A, the target evaluation unit 311 is disposed between the first-type standard cell 312 and the first-type standard cell 313, and the first-type standard cell 312 and the first-type standard cell 313 are disposed on both sides of the target evaluation unit 311, respectively.
As shown in fig. 3B at F, the target evaluation unit 311 is still placed in the first direction, and the first-type standard cell 312 and the first-type standard cell 313 are placed in the second direction, for example, the first direction mirror-rotated by 180 degrees. In other words, the first-type standard cell 311 as the target evaluation unit is still placed in the middle without any rotation, the directions (or angles) of the first-type standard cell 312 and the first-type standard cell 313 with respect to the target evaluation unit 311 are changed, and the first-type standard cell 312 and the first-type standard cell 313 are still placed on both sides of the target evaluation unit 311. According to an embodiment of the present invention, the detection method 100 is performed by the test units 200 shown in fig. 3A and 3B individually or sequentially.
According to an embodiment of the present invention, the at least one test unit 200 may be combined with the at least one test unit 300 to perform the evaluation method 100. According to another embodiment of the present invention, in step S102, any standard cell in the standard cell library may be used as a target evaluation unit, and then combined with a plurality of types of standard cells to generate the test cell 200 and/or the test cell 300, and then the evaluation method 100 is executed. According to another embodiment of the present invention, in step S102, a plurality of standard cells in the standard cell library may be simultaneously used as the target evaluation unit and constitute a test unit with the plurality of standard cells, and the evaluation method 100 may be simultaneously performed. According to another embodiment of the present invention, the first type of standard cell as the target evaluation unit can be combined with at least one type of standard cell in the standard cell library into the test unit 200 or the test unit 300, but not limited to one type. According to another embodiment of the present invention, the first type of standard cells as the target evaluation unit may be combined with at least one type of standard cells in the standard cell library to form a test unit, and the at least one type of standard cells are not necessarily disposed at two sides of the first type of standard cells.
Returning to fig. 1, when the test cell assembly is completed, step S103 is performed, the test cell is wired, and in step S104, it is determined whether the target evaluation cell would cause a violation of the design rule. Design rules are usually provided by the manufacturer, including, for example, the spacing between two wires needs to be greater than 1 micron, the width of a metal line in a certain layer needs to be greater than 0.032 micron, etc. When it is determined that the target evaluation unit does not cause violation of the design rule, step S105 is performed to directly use the target evaluation unit. When it is determined that the target evaluation unit would violate the design rule, step S106 is executed to adjust the distance between the target evaluation unit and the other standard cells. Taking the situation shown in fig. 2A-2B as an example, step S106 includes adjusting the distance between the target evaluation unit 211 and the second type standard cells 212 and 213. Taking the situation shown in fig. 3A-3B as an example, step S106 includes adjusting the distance between the target evaluation unit 311 and the first- type standard cells 312 and 313. According to an embodiment of the present invention, the adjustment of the inter-standard cell pitch is performed in units of unit adjustment intervals (sites). Step S106 further includes generating a pitch instruction file according to the adjusted pitch, so as to use the first type standard cell to which the target evaluation unit belongs according to the pitch instruction file during subsequent layout and routing, for example, setting the pitch between the first type standard cell and other standard cells to be greater than the adjusted pitch.
According to an embodiment of the present invention, when the pitches of the target evaluation unit and the other standard cells are adjusted in step S106, step S107 is performed to add 1 to the number of times of pitch adjustment of the test cell. After step S107, step S108 is executed to determine whether the number of pitch adjustments to the test cell exceeds a threshold value. When the adjustment number exceeds the threshold value, step S109 is executed to disable the target evaluation unit. When the adjustment times do not exceed the threshold value, step S110 is performed to route the test units after the pitch adjustment. After step S110, step S111 is executed to continuously determine whether the target evaluation unit after adjusting the pitch would cause a design rule violation. When the target evaluation unit after adjusting the pitch does not violate the design rule any more, step S312 is executed, and the first type standard unit to which the target evaluation unit belongs is used in combination with the pitch guidance file. When the adjusted target evaluator still causes a design rule violation, the process returns to step S106.
According to many embodiments of the present invention, each standard cell in the standard cell library may be combined with other standard cells to form at least one test cell, and the at least one test cell may be evaluated simultaneously using the detection method 100, and only the pitch of the test cells that would cause a design rule violation is adjusted.
According to an embodiment of the present invention, when the detection method 100 determines for the first time whether a standard cell will violate a design rule, and determines that the standard cell will not violate the design rule, the standard cell can be used normally (directly) when designing an integrated circuit. According to an embodiment of the present invention, when the detection method 100 disables a standard cell, the standard cell is not used in designing the integrated circuit. According to another embodiment of the present invention, after the detection method 100 adjusts the spacing between a standard cell and other standard cells, it is determined again whether the standard cell will violate the design rule, and if it is determined that the standard cell will not violate the design rule, the standard cell is used in combination with the spacing rule file generated by the detection method 100 when designing the integrated circuit.
Fig. 4 is a block diagram of an electronic computing device 400 according to an embodiment of the invention. As shown in fig. 4, electronic computing device 400 includes storage medium 410 and processor 420. The storage medium 410 is used for storing a computer program, and the processor 420 is used for storing the computer program of the storage medium 410 and executing the detection method 100 shown in fig. 1, wherein the operation steps of the detailed detection method 100 are as described above, and are not repeated herein.
According to many embodiments of the invention, the storage medium may include, but is not limited to, a non-transitory tangible configuration of an article made or formed by a machine or device, including, for example, a hard disk, any other type of disk including floppy disks, optical disks, compact disk read-only memories (CD-ROMs), compact disk readable (CD-RWs), and magneto-optical disks, storage media such as read-only memories (ROMs), Random Access Memories (RAMs) such as Dynamic Random Access Memories (DRAMs) and Static Random Access Memories (SRAMs), erasable programmable read-only memories (EPROMs), flash memories, electrically erasable programmable read-only memories (EEPROMs), Phase Change Memories (PCMs), magnetic or optical cards, or any other type of storage medium suitable for storing electronic instructions.
The detection methods of the present invention may also be embodied in the form of program code that is transmitted over some transmission medium, such as over electrical wiring or cabling, through fiber optics, or via any other form of transmission, wherein, when the program code is received and loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the invention. When implemented on a general-purpose processor, the program code combines with the processor to provide a unique apparatus that operates analogously to specific logic circuits.
The detection method provided by the invention is beneficial to evaluating the winding capacity of the standard cell and correcting or forbidding the winding capacity before automatic layout and wiring, so that the standard cell can be correctly used and the standard cell which is easy to violate the design rule can be avoided when the placing step of automatic layout and wiring is carried out, the iteration times of automatic layout and wiring are reduced, and the time required by design is greatly shortened.
In addition, the detection method provided by the invention has foresight on the winding capacity of the standard cell, and can provide use suggestions for the standard cell in the early design stage. In addition, all standard cells with winding problems are not forbidden, and new use suggestions are provided, so that the selectivity of the standard cells is stronger.
Although the embodiments of the present disclosure and their advantages have been disclosed above, it should be understood that various changes, substitutions and alterations can be made herein by those skilled in the art without departing from the spirit and scope of the disclosure. Moreover, the scope of the present disclosure is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein. Accordingly, the scope of the present disclosure includes the processes, machines, manufacture, compositions of matter, means, methods, and steps described above. In addition, each claim constitutes a separate embodiment, and the scope of protection of the present disclosure also includes combinations of the respective claims and embodiments.
Claims (10)
1. A method of testing a standard cell, comprising:
acquiring a first standard cell, a second standard cell and a third standard cell;
combining the first standard cell, the second standard cell, and the third standard cell into a test cell;
wiring the test unit;
determining whether the first standard cell results in a design rule violation;
adjusting the spacing of the first standard cell from the second standard cell and the third standard cell when the first standard cell results in a violation of the design rule; and
when the first standard cell does not cause violation of the design rule, the first standard cell belonging to the first standard cell is directly used.
2. The detection method of claim 1, wherein the second standard cell and the third standard cell are the first type standard cell or the second type standard cell.
3. The detection method of claim 1, further comprising:
respectively placing the second standard unit and the third standard unit on two sides of the first standard unit; and
the first standard cell is placed in a first direction or a second direction, and the second standard cell and the third standard cell are placed in the first direction.
4. The detection method of claim 1, further comprising:
adding one to the number of adjustments while performing the step of adjusting the spacing between the first standard cell and the second standard cell and the third standard cell;
judging whether the plus one adjustment times exceeds a threshold value;
disabling the first class of standard cells when the number of adjustments added by one exceeds the threshold;
when the added adjusting times do not exceed the threshold value, wiring the test unit after the distance is adjusted; and
determining whether the first standard cell after adjusting the spacing causes violation of the design rule.
5. The detection method of claim 1, further comprising:
using the first type standard cell in combination with the adjusted pitch when the first standard cell after adjusting the pitch does not cause violation of the design rule; and
when the first standard cell after adjusting the spacing causes a violation of the design rule, the spacing of the first standard cell and the second standard cell and the third standard cell is continuously adjusted.
6. An electronic computing device, comprising:
a storage medium to store a computer program; and
a processor calling the computer program to execute a detection method, wherein the detection method comprises:
acquiring a first standard cell, a second standard cell and a third standard cell;
combining the first standard cell, the second standard cell, and the third standard cell into a test cell;
wiring the test unit;
determining whether the first standard cell results in a design rule violation;
adjusting the spacing of the first standard cell from the second standard cell and the third standard cell when the first standard cell results in a violation of the design rule; and
when the first standard cell does not cause violation of the design rule, the first standard cell belonging to the first standard cell is directly used.
7. The electronic computing device of claim 6, wherein the second standard cell and the third standard cell are the first type of standard cell or a second type of standard cell.
8. The electronic computing device of claim 6, wherein the detection method further comprises:
respectively placing the second standard unit and the third standard unit on two sides of the first standard unit; and
placing the first standard cell in a first direction or a second direction,
placing the second standard cell and the third standard cell along the first direction.
9. The electronic computing device of claim 6, wherein the detection method further comprises:
adding one to the number of adjustments while performing the step of adjusting the spacing of the first standard cell, the second standard cell, and the third standard cell;
judging whether the plus one adjustment times exceeds a threshold value;
disabling the first class of standard cells when the number of adjustments added by one exceeds the threshold;
when the added adjusting times do not exceed the threshold value, wiring the test unit after the distance is adjusted; and
determining whether the first standard cell after adjusting the spacing causes violation of the design rule.
10. The electronic computing device of claim 6, wherein the detection method further comprises:
using the first type standard cell in combination with the adjusted pitch when the first standard cell after adjusting the pitch does not cause violation of the design rule; and
when the first standard cell after adjusting the spacing causes a violation of the design rule, the spacing of the first standard cell and the second standard cell and the third standard cell is continuously adjusted.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112257383A (en) * | 2020-10-30 | 2021-01-22 | 上海兆芯集成电路有限公司 | Standard unit detection method |
| CN114358174A (en) * | 2021-12-31 | 2022-04-15 | 海光信息技术股份有限公司 | Standard unit discharge rate test classification method, apparatus, equipment, procedure and medium |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140130003A1 (en) * | 2012-11-08 | 2014-05-08 | Advanced Micro Devices Inc. | Standard cell placement method to exercise placement permutations of standard cell libraries |
| US20150302135A1 (en) * | 2014-04-17 | 2015-10-22 | Chul-Hong Park | Method for designing and manufacturing an integrated circuit, system for carrying out the method, and system for verifying an integrated circuit |
| CN107919354A (en) * | 2016-10-05 | 2018-04-17 | 三星电子株式会社 | The design method of integrated circuit and the integrated circuit including modified unit |
| CN108520128A (en) * | 2018-03-29 | 2018-09-11 | 北京集创北方科技股份有限公司 | Method of designing integrated circuit and computer readable storage medium |
| CN108830008A (en) * | 2018-06-28 | 2018-11-16 | 中国科学院微电子研究所 | Test method and test system for full model of standard cell library |
| CN109684707A (en) * | 2018-12-19 | 2019-04-26 | 上海华力微电子有限公司 | A kind of standard cell lib layout design rules verification method |
| CN109817614A (en) * | 2017-11-21 | 2019-05-28 | 台湾积体电路制造股份有限公司 | Standard cell structures and methods of placing and routing standard cell structures |
| CN110390122A (en) * | 2018-04-19 | 2019-10-29 | 三星电子株式会社 | Integrated circuits including standard cells and methods and systems for designing and manufacturing the same |
| US20200134126A1 (en) * | 2018-10-31 | 2020-04-30 | Taiwan Semiconductor Manufacturing Company Ltd. | Reduced area standard cell abutment configurations |
-
2020
- 2020-10-30 CN CN202011191795.0A patent/CN112257384B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140130003A1 (en) * | 2012-11-08 | 2014-05-08 | Advanced Micro Devices Inc. | Standard cell placement method to exercise placement permutations of standard cell libraries |
| US20150302135A1 (en) * | 2014-04-17 | 2015-10-22 | Chul-Hong Park | Method for designing and manufacturing an integrated circuit, system for carrying out the method, and system for verifying an integrated circuit |
| CN107919354A (en) * | 2016-10-05 | 2018-04-17 | 三星电子株式会社 | The design method of integrated circuit and the integrated circuit including modified unit |
| CN109817614A (en) * | 2017-11-21 | 2019-05-28 | 台湾积体电路制造股份有限公司 | Standard cell structures and methods of placing and routing standard cell structures |
| CN108520128A (en) * | 2018-03-29 | 2018-09-11 | 北京集创北方科技股份有限公司 | Method of designing integrated circuit and computer readable storage medium |
| CN110390122A (en) * | 2018-04-19 | 2019-10-29 | 三星电子株式会社 | Integrated circuits including standard cells and methods and systems for designing and manufacturing the same |
| CN108830008A (en) * | 2018-06-28 | 2018-11-16 | 中国科学院微电子研究所 | Test method and test system for full model of standard cell library |
| US20200134126A1 (en) * | 2018-10-31 | 2020-04-30 | Taiwan Semiconductor Manufacturing Company Ltd. | Reduced area standard cell abutment configurations |
| CN109684707A (en) * | 2018-12-19 | 2019-04-26 | 上海华力微电子有限公司 | A kind of standard cell lib layout design rules verification method |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112257383A (en) * | 2020-10-30 | 2021-01-22 | 上海兆芯集成电路有限公司 | Standard unit detection method |
| CN112257383B (en) * | 2020-10-30 | 2022-11-01 | 上海兆芯集成电路有限公司 | Method for detecting standard cell |
| CN114358174A (en) * | 2021-12-31 | 2022-04-15 | 海光信息技术股份有限公司 | Standard unit discharge rate test classification method, apparatus, equipment, procedure and medium |
| CN114358174B (en) * | 2021-12-31 | 2025-06-13 | 海光信息技术股份有限公司 | Classification methods, devices, equipment, procedures and media for standard unit release rate testing |
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| CN112257384B (en) | 2022-11-01 |
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