CN112230703A - A High Precision Bandgap Reference Current Source Based on Clamping Technology - Google Patents
A High Precision Bandgap Reference Current Source Based on Clamping Technology Download PDFInfo
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- CN112230703A CN112230703A CN202011195233.3A CN202011195233A CN112230703A CN 112230703 A CN112230703 A CN 112230703A CN 202011195233 A CN202011195233 A CN 202011195233A CN 112230703 A CN112230703 A CN 112230703A
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- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
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- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is DC
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
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Abstract
A high-precision band-gap reference current source based on clamping technology is disclosed, which uses Q as reference current source2As node X1With its source passing through R1Then grounding; q1As node X2The source of the transistor is grounded; the grid of the first NMOS tube is connected with Q1The source of the collector is connected with R2And as node X3，R2The other end of the first and second electrodes is grounded; node X1Node X2And node X3The interconnection ensures that the voltages of the three nodes are not influenced by the channel length modulation effect and MOS mismatch and always keep an accurate equal relation, thereby ensuring that R is not influenced by the channel length modulation effect and MOS mismatch1The voltage across is kept at Q1And Q2Difference of base-collector differential pressure, R2The voltage across is kept at Q1So that a flow through R is caused1The current of (2) is a positive temperature coefficient current flowing through R2Is a negative temperature coefficient current, and the superposition generates a zero temperature coefficient current. The invention effectively reducesThe chip area reduces the influence of MOS tube mismatch on the circuit, thereby ensuring the precision and stability of the reference source.
Description
Technical Field
The invention belongs to the technical field of band gap reference sources, and relates to a high-precision band gap reference current source circuit based on a clamping technology.
Background
The key of the band-gap reference current source is that positive temperature coefficient current I is respectively generatedPTATWith negative temperature coefficient current ICTATAnd proportionally integrating the current sources into a current source I with zero temperature coefficientREFI.e. the reference source.
A conventional bandgap reference current source structure is shown in FIG. 1, which is implemented by a MOS transistor (MP)1、MP2、MP6、MP7、MN1、MN2、MN4、MN5) Constituent cascode current mirror enable node X1、X2Is approximately equal, through a MOS transistor (MN)5、MN6) The gate voltages are equal and the source voltages are approximately equal to make the node X2、X3Are approximately equal to each other, thereby reaching node X1、X2、X3The voltages are approximately equal to each other, and then the voltage flowing through the first resistor R is obtained1Positive temperature coefficient current IR1Through a second resistor R2Negative temperature coefficient current IR2And integrated as a zero temperature coefficient current IREF。
But the node X is influenced by the channel length modulation effect and the mismatch of the MOS tube2、X3The voltages at the positions cannot be exactly equal, and the deviation of dozens of mV is generated; due to the flow through the MOS transistor MN5、MN6Are not equal, so that the node X1、X2The voltages at the positions cannot be exactly equal, and the deviation of dozens of mV is generated; eventually resulting in node X1、X2、X3The voltage at the point will have a deviation of several tens mV, thereby affecting the current flowing through the first resistor R1And a second resistor R2Of the current influencing the positive temperature coefficient current IPTATAnd negative temperature coefficient current ICTATUltimately affecting the accuracy of the reference source.
Disclosure of Invention
Aiming at the problem that the traditional band-gap reference current source cannot ensure the node X1、X2、X3The voltages are approximately equalThe invention provides a high-precision band-gap reference current source based on a clamping technology, which can ensure that a node X is connected1、X2、X3The voltages at the reference point keep accurate and equal relation, so that the deviation caused by the influence of the channel length modulation effect and the MOS tube mismatch is solved, and the precision and the stability of the reference current source are improved.
The technical scheme adopted by the invention is as follows:
a high-precision band-gap reference current source based on a clamping technology comprises a first bipolar transistor, a second bipolar transistor, a first resistor, a second resistor, a first NMOS (N-channel metal oxide semiconductor) tube, a first current mirror, a second current mirror and a third current mirror, wherein the base of the second bipolar transistor is used as a node X1The source electrode of the transistor is grounded after passing through the first resistor; the base of the first bipolar transistor is used as a node X2The source of the transistor is grounded; the grid of the first NMOS transistor is connected with the collector of the first bipolar transistor, and the source of the first NMOS transistor is connected with one end of the second resistor and is used as a node X3The other end of the second resistor is grounded; node X1Node X2And node X3An interconnect;
the first current mirror is used for mirroring the current of the branch where the second bipolar transistor is located to the branch where the first bipolar transistor is located, so that the collector current of the first bipolar transistor is equal to the collector current of the second bipolar transistor, and the voltage at two ends of the first resistor is the base-collector voltage of the first bipolar transistor minus the base-collector voltage of the second bipolar transistor, so that the voltage at two ends of the first resistor is the voltage with a positive temperature coefficient, and the currents flowing through the first resistor, the first bipolar transistor and the second bipolar transistor are all currents with the positive temperature coefficient; the base-collector voltage of the first bipolar transistor being a negative temperature coefficient voltage, node X2Is a negative temperature coefficient voltage corresponding to node X3The voltage of the second resistor is also the voltage of the negative temperature coefficient, and the current flowing through the second resistor is the current of the negative temperature coefficient;
the second current mirror is used for mirroring the positive temperature coefficient current of the branch where the first resistor and the second bipolar transistor are located to the first output branch, the third current mirror is used for mirroring the negative temperature coefficient current of the branch where the second resistor and the first NMOS transistor are located to the second output branch, and the zero temperature coefficient reference current obtained by superposing the current of the first output branch and the current of the second output branch is output from the output end of the high-precision band-gap reference current source by adjusting the resistance values of the first resistor and the second resistor.
Specifically, the first current mirror comprises a first PMOS tube, a second PMOS tube, a third PMOS tube and a fourth PMOS tube,
the grid electrode of the first PMOS tube is connected with the grid electrode of the second PMOS tube, the drain electrode of the third PMOS tube and the drain electrode branch of the second bipolar transistor, the drain electrode of the first PMOS tube is connected with the source electrode of the third PMOS tube, and the source electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube and is connected with a power supply voltage;
the grid electrode of the fourth PMOS tube is connected with the grid electrode of the third PMOS tube, the drain electrode of the fourth PMOS tube is connected with the drain electrode branch of the first bipolar transistor, and the source electrode of the fourth PMOS tube is connected with the drain electrode of the second PMOS tube.
Specifically, the second current mirror comprises a first PMOS tube, a third PMOS tube, a fifth PMOS tube and a sixth PMOS tube,
the grid electrode of the fifth PMOS tube is connected with the grid electrode of the first PMOS tube, the drain electrode of the fifth PMOS tube is connected with the source electrode of the sixth PMOS tube, and the source electrode of the fifth PMOS tube is connected with power supply voltage;
and the grid electrode of the sixth PMOS tube is connected with the grid electrode of the third PMOS tube, and the drain electrode of the sixth PMOS tube is connected with the output end of the high-precision band-gap reference current source.
Specifically, the third current mirror comprises a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, and a tenth PMOS transistor,
the grid electrode of the seventh PMOS tube is connected with the grid electrode of the eighth PMOS tube, the drain electrode of the ninth PMOS tube and the drain electrode of the first NMOS tube, the drain electrode of the seventh PMOS tube is connected with the source electrode of the ninth PMOS tube, and the source electrode of the seventh PMOS tube is connected with the source electrode of the eighth PMOS tube and the power supply voltage;
the grid electrode of the tenth PMOS tube is connected with the grid electrode of the ninth PMOS tube, the drain electrode of the tenth PMOS tube is connected with the output end of the high-precision band-gap reference current source, and the source electrode of the tenth PMOS tube is connected with the drain electrode of the eighth PMOS tube.
Specifically, the high-precision band-gap reference current source further comprises a second NMOS tube and a third NMOS tube,
the grid drain of the third NMOS tube is in short circuit connection with the grid of the second NMOS tube and the drain of the fourth PMOS tube, and the source electrode of the third NMOS tube is connected with the collector electrode of the first bipolar transistor;
the drain electrode of the second NMOS tube is connected with the drain electrode of the third PMOS tube, and the source electrode of the second NMOS tube is connected with the collector electrode of the second bipolar transistor.
The invention has the beneficial effects that: the invention is realized by connecting a node X1、X2、X3The direct connection ensures that the voltages of the three nodes are not influenced by the channel length modulation effect and MOS mismatch and always keep an accurate equal relation, thereby ensuring that the first resistor R1The voltage at both ends is maintained as a first bipolar transistor Q1And a second bipolar transistor Q2Difference between base and collector voltage differences, second resistance R2The voltage at both ends is maintained as a first bipolar transistor Q1The base and collector are at a voltage difference such that the current flows through the first resistor R1Current of (I)R1A current with positive temperature coefficient flows through the second resistor R2Current of (I)R2For negative temperature coefficient currents, the superposition produces zero temperature coefficient current IREF(ii) a The invention solves the problem of deviation of the traditional band-gap reference current source caused by the influence of channel length modulation effect and MOS tube mismatch without increasing circuit complexity, reduces chip area and improves the precision and stability of the reference source.
Drawings
The following description of various embodiments of the invention may be better understood with reference to the following drawings, which schematically illustrate major features of some embodiments of the invention. These figures and examples provide some embodiments of the invention in a non-limiting, non-exhaustive manner. For purposes of clarity, the same reference numbers will be used in different drawings to identify the same or similar elements or structures having the same function.
Fig. 1 is a circuit configuration diagram of a conventional bandgap reference current source.
Fig. 2 is a circuit diagram of a specific implementation of a high-precision bandgap reference current source based on a clamping technique according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in detail with reference to the accompanying drawings. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It is to be noted that, in the present invention, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The invention provides a high-precision band-gap reference current source based on a clamping technology, which comprises a first bipolar transistor Q1A second bipolar transistor Q2A first resistor R1A second resistor R2A first NMOS transistor M13A first current mirror, a second current mirror, a third current mirror, and a second bipolar transistor Q2As node X1With its source passing through a first resistor R1Then grounding; first bipolar transistor Q1As node X2The source of the transistor is grounded; first NMOS transistor M13Is connected to the first bipolar transistor Q1The source of the collector is connected with a second resistor R2And as node X3A second resistance R2The other end of the first and second electrodes is grounded; the invention connects node X1Node X2And node X3The interconnection ensures that the voltages of the three nodes are always kept in an accurate equal relation, is not influenced by the channel length modulation effect and the mismatch between the MOS transistors, and has higher precision and stability compared with the traditional structure. First NMOS transistor M13For forming a negative feedback loop.
The first current mirror is used for connecting the second bipolar transistorQ2The current of the branch is mirrored to the first bipolar transistor Q1In a branch, so that the first bipolar transistor Q1And a second bipolar transistor Q2Are equal. Fig. 2 shows an implementation structure of the first current mirror, which includes a first PMOS transistor M in this embodiment1A second PMOS transistor M2And the third PMOS transistor M6And a fourth PMOS transistor M7The first PMOS transistor M1The grid electrode of the transistor is connected with a second PMOS transistor M2Grid electrode of the PMOS transistor M and a third PMOS transistor M6And a second bipolar transistor Q2The drain electrode of the drain electrode branch is connected with a third PMOS tube M6A source electrode of the second PMOS transistor M is connected with the source electrode2And connected to the supply voltage VDD; fourth PMOS transistor M7The grid electrode of the transistor is connected with a third PMOS transistor M6A drain of which is connected to the first bipolar transistor Q1The source of the drain branch is connected with a second PMOS tube M2Of the substrate.
The first PMOS transistor M in this embodiment1A second PMOS transistor M2And the third PMOS transistor M6And a fourth PMOS transistor M7Form a cascode current mirror and couple the first PMOS transistor M1And a third PMOS transistor M6Branch circuit (i.e. bipolar transistor Q)2Drain branch of) to the second PMOS transistor M2And a fourth PMOS transistor M7Branch (i.e. first bipolar transistor Q)1Drain branch) of the first bipolar transistor Q such that the first bipolar transistor Q is connected to the first bipolar transistor Q1A second bipolar transistor Q2Have equal currents as follows:
IC1＝IC2
IS1＝n·IS2
wherein IC1And IC2Respectively, a first bipolar transistor Q1And a second bipolar transistor Q2The collector current of (1); beta represents the current amplification factor of the bipolar transistor; i iss1And Is2Respectively, a first bipolar transistor Q1And a second bipolar transistor Q2The PN junction reverse-phase saturation current of (1); n represents a first bipolar transistor Q1And a second bipolar transistor Q2And n is a positive integer; vBE1And VBE2Respectively, a first bipolar transistor Q1And a second bipolar transistor Q2The voltage difference between the base electrode and the collector electrode; vTIs a thermal voltage.
The following can be derived from the above equation:
VBE1-VBE2＝VT·lnn
a first resistor R1Voltage V acrossR1Is a first bipolar transistor Q1A second bipolar transistor Q2The difference of the pressure difference between the base electrode and the collector electrode is as follows:
VR1＝VBE1-VBE2＝VT·lnn
flows through the first resistor R1Current of (I)R1Can be expressed as:
can see thatR1Is a current of positive temperature coefficient, IR1Flows through the second bipolar transistor Q2And a second bipolar transistor Q2Is equal to the first bipolar transistor Q1Thus, the first bipolar transistor Q1Is also a positive temperature coefficient of current. This causes the first bipolar transistor Q to be1Pressure drop V overBE1Is a voltage of negative temperature coefficient, i.e. X2The voltage at the node is a negative temperature coefficient voltage. And due to node X1Node X2And node X3Interconnection, corresponding node X3Is also a negative temperature coefficient voltage, then flows through the second resistor R2Current of (I)R2Can be expressed as:
can see thatR2Is a negative temperature coefficient current.
Thus at the first resistance R1And a second resistor R2The current with positive temperature coefficient and the current with negative temperature coefficient are respectively generated, the two currents are respectively mirrored to the output branch circuit by utilizing the second current mirror and the third current mirror for superposition, and the first resistor R is adjusted1And a second resistor R2The resistance value of the resistor adjusts the proportion of superposition, so that the reference current I with zero temperature coefficient is finally obtained by superpositionREF。
In particular, the second current mirror is used to couple the first resistor R1And a second bipolar transistor Q2The current mirror with positive temperature coefficient of the branch is mirrored to the first output branch, and an implementation structure of the second current mirror is shown in fig. 2, where the second current mirror includes a first PMOS transistor M in this embodiment1And the third PMOS transistor M6The fifth PMOS transistor M5And a sixth PMOS transistor M10Fifth PMOS transistor M5The grid electrode of the transistor is connected with a first PMOS transistor M1The drain electrode of the grid electrode is connected with a sixth PMOS tube M10A source electrode of (1), the source electrode of (2) being connected to a power supply voltage; sixth PMOS transistor M10The grid electrode of the transistor is connected with a third PMOS transistor M6The drain of the grid of the high-precision band-gap reference current source is connected with the output end of the high-precision band-gap reference current source.
The third current mirror is used for connecting the second resistor R2And a first NMOS transistor M13The negative temperature coefficient current of the branch is mirrored to the second output branch, and as shown in fig. 2, an implementation structure of the third current mirror is provided, in this embodiment, the third current mirror includes a seventh PMOS transistor M3Eighth PMOS transistor M4Ninth PMOS transistor M8Tenth PMOS transistor M9Seventh PMOS transistor M3The grid electrode of the transistor is connected with an eighth PMOS tube M4OfPole and ninth PMOS transistor M8Drain electrode of (1) and first NMOS transistor M13The drain electrode of the second PMOS tube M is connected with the second PMOS tube M8A source electrode of the transistor is connected with the eighth PMOS tube M4Is connected to a supply voltage; tenth PMOS tube M9The grid electrode of the first PMOS tube is connected with a ninth PMOS tube M8The drain electrode of the grid electrode is connected with the output end of the high-precision band-gap reference current source, and the source electrode of the grid electrode is connected with the eighth PMOS tube M4Of the substrate.
First PMOS transistor M in second current mirror of this embodiment1And the third PMOS transistor M6The fifth PMOS transistor M5And a sixth PMOS transistor M10Form a cascode current mirror and pass through a first resistor R1Current of (I)R1Is copied to a fifth PMOS transistor M5And a sixth PMOS transistor M10On the first output branch, is marked as IPTAT。
Seventh PMOS transistor M in third current mirror of this embodiment3Eighth PMOS transistor M4Ninth PMOS transistor M8Tenth PMOS transistor M9Form a cascode current mirror, and pass through a second resistor R2Current of (I)R2Is copied to the eighth PMOS transistor M4Tenth PMOS transistor M9On the second output branch and is marked as ICTAT。
By adjusting the first resistance R1And a second resistor R2The resistance value of the resistor can obtain the current I with zero temperature coefficientREFExpressed as:
IREF＝IPTAT+ICTAT
further, in order to make the first bipolar transistor Q1And a second bipolar transistor Q2The NMOS transistor has the same collector voltage, and a second NMOS transistor M can be arranged in the embodiment11And a third NMOS transistor M12Third NMOS transistor M12Is in short circuit with the gate and the drain and is connected with a second NMOS tube M11Grid and fourth PMOS tube M7A source electrode of which is connected with a first bipolar transistor Q1A collector electrode of (a); second NMOS transistor M11The drain electrode of the transistor is connected with a third PMOS tube M6And a source connected to the second bipolar transistor Q2The collector electrode of (1).
In summary, the bandgap reference current source provided by the invention is formed by connecting the node X1、X2、X3Directly connected to ensure the voltage of three nodes (i.e. the first bipolar transistor Q)1Base voltage V ofB_Q1A second bipolar transistor Q2Base voltage V ofB_Q2A second resistor R2Voltage V onR2) The exact equality relation is always strictly maintained, and even if the channel length modulation effect and the mismatch of the MOS transistor are considered, the V cannot be influencedB_Q1、VB_Q2、VR2And the equality relationship between them. In the traditional structure, three nodes are difficult to clamp simultaneously, the clamping cost is high, for example, an additional operational amplifier is needed, the reference current source provided by the invention realizes clamping without an amplifier, and the problem of depending on the node X is effectively solved by adopting a novel structure1、X2、X3But the accuracy and the stability are improved under the condition of not increasing the complexity of the circuit.
A first resistor R1The voltage drop across is exactly equal to the first bipolar transistor Q1A second bipolar transistor Q2The difference of the voltage difference between the base electrode and the collector electrode enables the current to flow through the first resistor R1Current of (I)R1Exactly aligned with the first bipolar transistor Q1A second bipolar transistor Q2The difference value of the voltage difference between the base electrode and the collector electrode is in direct proportion to obtain the current I with positive temperature coefficientR1(ii) a A second resistor R2The voltage drop across is exactly equal to the first bipolar transistor Q1The voltage difference between the base electrode and the collector electrode is enabled to flow through the second resistor R2Current of (I)R2Exactly aligned with the first bipolar transistor Q1The voltage difference between the base electrode and the collector electrode is in direct proportion to obtain the current I with negative temperature coefficientR2Copying I by means of a current mirrorR1To the first output branch to obtain IPTATCopying I by means of a current mirrorR2To a second output branch to obtain ICTATAnd after superposition, generating a reference current output with zero temperature coefficient.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (5)
1. A high-precision band-gap reference current source based on a clamping technology is characterized by comprising a first bipolar transistor, a second bipolar transistor, a first resistor, a second resistor, a first NMOS (N-channel metal oxide semiconductor) tube, a first current mirror, a second current mirror and a third current mirror, wherein the base electrode of the second bipolar transistor is used as a node X1The source electrode of the transistor is grounded after passing through the first resistor; the base of the first bipolar transistor is used as a node X2The source of the transistor is grounded; the grid of the first NMOS transistor is connected with the collector of the first bipolar transistor, and the source of the first NMOS transistor is connected with one end of the second resistor and is used as a node X3The other end of the second resistor is grounded; node X1Node X2And node X3An interconnect;
the first current mirror is used for mirroring the current of the branch where the second bipolar transistor is located to the branch where the first bipolar transistor is located, so that the collector current of the first bipolar transistor is equal to the collector current of the second bipolar transistor, and the voltage at two ends of the first resistor is the base-collector voltage of the first bipolar transistor minus the base-collector voltage of the second bipolar transistor, so that the voltage at two ends of the first resistor is the voltage with a positive temperature coefficient, and the currents flowing through the first resistor, the first bipolar transistor and the second bipolar transistor are all currents with the positive temperature coefficient; the base-collector voltage of the first bipolar transistor being a negative temperature coefficient voltage, node X2Is a negative temperature coefficient voltage corresponding to node X3The voltage of the second resistor is also the voltage of the negative temperature coefficient, and the current flowing through the second resistor is the current of the negative temperature coefficient;
the second current mirror is used for mirroring the positive temperature coefficient current of the branch where the first resistor and the second bipolar transistor are located to the first output branch, the third current mirror is used for mirroring the negative temperature coefficient current of the branch where the second resistor and the first NMOS transistor are located to the second output branch, and the zero temperature coefficient reference current obtained by superposing the current of the first output branch and the current of the second output branch is output from the output end of the high-precision band-gap reference current source by adjusting the resistance values of the first resistor and the second resistor.
2. The high-precision bandgap reference current source based on clamping technology as claimed in claim 1, wherein the first current mirror comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor and a fourth PMOS transistor,
the grid electrode of the first PMOS tube is connected with the grid electrode of the second PMOS tube, the drain electrode of the third PMOS tube and the drain electrode branch of the second bipolar transistor, the drain electrode of the first PMOS tube is connected with the source electrode of the third PMOS tube, and the source electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube and is connected with a power supply voltage;
the grid electrode of the fourth PMOS tube is connected with the grid electrode of the third PMOS tube, the drain electrode of the fourth PMOS tube is connected with the drain electrode branch of the first bipolar transistor, and the source electrode of the fourth PMOS tube is connected with the drain electrode of the second PMOS tube.
3. The high-precision bandgap reference current source based on the clamping technique as claimed in claim 2, wherein the second current mirror comprises a first PMOS transistor, a third PMOS transistor, a fifth PMOS transistor and a sixth PMOS transistor,
the grid electrode of the fifth PMOS tube is connected with the grid electrode of the first PMOS tube, the drain electrode of the fifth PMOS tube is connected with the source electrode of the sixth PMOS tube, and the source electrode of the fifth PMOS tube is connected with power supply voltage;
and the grid electrode of the sixth PMOS tube is connected with the grid electrode of the third PMOS tube, and the drain electrode of the sixth PMOS tube is connected with the output end of the high-precision band-gap reference current source.
4. The high-precision bandgap reference current source based on the clamping technique as claimed in claim 2 or 3, wherein the third current mirror comprises a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor and a tenth PMOS transistor,
the grid electrode of the seventh PMOS tube is connected with the grid electrode of the eighth PMOS tube, the drain electrode of the ninth PMOS tube and the drain electrode of the first NMOS tube, the drain electrode of the seventh PMOS tube is connected with the source electrode of the ninth PMOS tube, and the source electrode of the seventh PMOS tube is connected with the source electrode of the eighth PMOS tube and the power supply voltage;
the grid electrode of the tenth PMOS tube is connected with the grid electrode of the ninth PMOS tube, the drain electrode of the tenth PMOS tube is connected with the output end of the high-precision band-gap reference current source, and the source electrode of the tenth PMOS tube is connected with the drain electrode of the eighth PMOS tube.
5. The high-precision bandgap reference current source based on clamping technology as claimed in claim 4, wherein the high-precision bandgap reference current source further comprises a second NMOS transistor and a third NMOS transistor,
the grid drain of the third NMOS tube is in short circuit connection with the grid of the second NMOS tube and the drain of the fourth PMOS tube, and the source electrode of the third NMOS tube is connected with the collector electrode of the first bipolar transistor;
the drain electrode of the second NMOS tube is connected with the drain electrode of the third PMOS tube, and the source electrode of the second NMOS tube is connected with the collector electrode of the second bipolar transistor.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113467567A (en) * | 2021-07-28 | 2021-10-01 | 深圳市中科蓝讯科技股份有限公司 | Reference source circuit and chip |
| CN114020085A (en) * | 2021-10-18 | 2022-02-08 | 杭州中科微电子有限公司 | Multi-output reference voltage generating circuit |
| CN115113676A (en) * | 2021-03-18 | 2022-09-27 | 纮康科技股份有限公司 | Reference circuit with temperature compensation |
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| CN102880220A (en) * | 2011-07-12 | 2013-01-16 | 联咏科技股份有限公司 | Temperature coefficient current triggering generator and temperature coefficient current triggering generating module |
| US20140077789A1 (en) * | 2012-09-20 | 2014-03-20 | Novatek Microelectronics Corp. | Bandgap Reference Circuit and Self-Referenced Regulator |
| CN105425891A (en) * | 2015-11-19 | 2016-03-23 | 苏州市职业大学 | Zero-temperature coefficient adjustable voltage reference source |
| CN105786075A (en) * | 2016-04-20 | 2016-07-20 | 广东工业大学 | Pre-regulator circuit capable of increasing band-gap reference power supply rejection ratio |
| CN110888485A (en) * | 2019-10-09 | 2020-03-17 | 芯创智（北京）微电子有限公司 | Self-biased band gap reference circuit |
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| CN115113676A (en) * | 2021-03-18 | 2022-09-27 | 纮康科技股份有限公司 | Reference circuit with temperature compensation |
| CN115113676B (en) * | 2021-03-18 | 2024-03-01 | 纮康科技股份有限公司 | Reference circuit with temperature compensation function |
| CN113467567A (en) * | 2021-07-28 | 2021-10-01 | 深圳市中科蓝讯科技股份有限公司 | Reference source circuit and chip |
| CN114020085A (en) * | 2021-10-18 | 2022-02-08 | 杭州中科微电子有限公司 | Multi-output reference voltage generating circuit |
| CN114020085B (en) * | 2021-10-18 | 2023-10-27 | 杭州中科微电子有限公司 | Reference voltage generating circuit with multiple outputs |
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