CN112201693A - Gallium nitride semiconductor device and manufacturing method - Google Patents
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- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 134
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 86
- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 86
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- 229910052796 boron Inorganic materials 0.000 claims description 8
- 229910052698 phosphorus Inorganic materials 0.000 claims description 8
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
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- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
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- H—ELECTRICITY
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
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- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/109—Reduced surface field [RESURF] PN junction structures
- H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
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Abstract
The invention provides a gallium nitride semiconductor device and a manufacturing method thereof, wherein the gallium nitride semiconductor device comprises a gallium nitride layer, a silicon substrate layer and a heavily doped high-conductivity region, the heavily doped high-conductivity region is a doped region formed in the upper surface layer of the silicon substrate layer, the heavily doped high-conductivity region comprises an N-type doped region and a P-type doped region which are alternately arranged at intervals, and the gallium nitride layer grows on the heavily doped high-conductivity region. According to the invention, the heavily doped high-conductivity region is formed on the upper surface of the silicon substrate layer, and then the gallium nitride layer grows on the heavily doped high-conductivity region, so that the heavily doped high-conductivity region isolates an electric field between a drain electrode and a source electrode on the gallium nitride layer, thereby effectively avoiding electric field coupling between the gallium nitride layer and the silicon substrate layer, reducing loss generated on the silicon substrate layer due to electric field coupling, and improving various electrical properties of the gallium nitride semiconductor device including PAE and the like.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a gallium nitride semiconductor device and a manufacturing method thereof.
Background
The research and application of gallium nitride (GaN) materials are leading edge and hot spot of the current global semiconductor research, and are novel semiconductor materials for developing microelectronic devices and optoelectronic devices. In 5G key technology Massive MIMO application, a large number of array antennas are used on a base station transceiver to realize larger wireless data flow and connection reliability, the structure needs corresponding radio frequency transceiver unit array matching, the number of radio frequency devices is greatly increased, therefore, the size of the devices becomes a key factor, and the utilization of gallium nitride can help radio frequency front-end devices to realize high integration.
However, the gallium nitride devices grown on the silicon substrate have a great application prospect compared with gallium nitride devices grown on other substrates, such as silicon carbide and the like, due to good compatibility with a silicon-based process and low price. However, this type of gan device is prone to electric field loss with the low-resistance silicon substrate, so that the electrical performance, such as efficiency, of the rf gan device is affected. That is, in a conventional radio frequency gallium nitride device, electric field coupling is easily generated between a gallium nitride layer and a silicon substrate layer, which leads to a decrease in the conductivity of the gallium nitride device, thereby decreasing the efficiency of the gallium nitride device.
Disclosure of Invention
The invention aims to provide a gallium nitride semiconductor device and a manufacturing method thereof, and aims to solve the technical problem that the loss of the gallium nitride semiconductor device is high in the prior art.
In order to achieve the purpose, the invention adopts the technical scheme that:
a gallium nitride semiconductor device, comprising:
a silicon substrate layer;
the heavily doped high-conductivity region is a doped region formed in the upper surface layer of the silicon substrate layer and comprises an N-type doped region and a P-type doped region which are alternately arranged at intervals;
a gallium nitride layer disposed over the heavily doped high conductivity region.
Further, a depletion layer is formed between the N-type doped region and the adjacent P-type doped region.
Further, the impurity forming the N-type doped region comprises phosphorus, and the impurity forming the P-type doped region comprises boron.
Further, the impurity concentration range is 1018ion/cm3-1020ion/cm3。
Furthermore, the gallium nitride layer comprises an i-GaN layer, an ALGaN layer and an n-GaN layer, a grid electrode is arranged on the upper surface of the n-GaN layer, drain electrodes and source electrodes are respectively arranged on the upper surfaces of the two ends of the AlLGaN layer, and the drain electrodes and the source electrodes penetrate through the n-GaN layer.
A method of manufacturing a gallium nitride semiconductor device, comprising:
forming a heavily doped high-conductivity region in the upper surface layer of the silicon substrate layer, wherein the heavily doped high-conductivity region comprises a plurality of N-type doped regions and P-type doped regions which are alternately arranged at intervals;
and growing a gallium nitride layer on the heavily doped high-conductivity region.
Further, the forming a heavily doped high-conductivity region in an upper surface layer of the silicon substrate layer includes:
forming a first sacrificial layer on the upper surface of the silicon substrate layer, and performing first ion implantation on the upper surface of the silicon substrate layer based on the first sacrificial layer to form the N-type doped region;
and removing the first sacrificial layer, forming a second sacrificial layer on the upper surface of the silicon substrate layer, and performing second ion implantation on the upper surface of the silicon substrate layer based on the second sacrificial layer to form the P-type doped region.
Further, before growing the upper surface layer of the heavily doped high-conductivity region to obtain the gallium nitride layer, the method further comprises:
and carrying out high-temperature annealing treatment on the heavily doped high-conductivity region for a first preset time at a preset temperature.
Further, the growing a gallium nitride layer on the heavily doped high-conductivity region includes:
growing an i-GaN layer on the upper surface layer of the heavily doped high-conductivity region;
growing an ALGaN layer on the i-GaN layer;
and growing an n-GaN layer on the ALGaN layer.
Further, after growing the n-GaN layer on the ALGaN layer, the method further includes:
arranging a grid on the upper surface of the n-GaN layer;
and respectively arranging a drain electrode and a source electrode on the upper surfaces of two ends of the ALGaN layer, wherein the drain electrode and the source electrode penetrate through the n-GaN layer.
The gallium nitride semiconductor device and the manufacturing method provided by the invention have the beneficial effects that:
according to the invention, the gallium nitride semiconductor device comprises a gallium nitride layer, a silicon substrate layer and a heavily doped high-conductivity region, the heavily doped high-conductivity region including N-type doped regions and P-type doped regions which are alternately arranged at intervals is formed in the upper surface layer of the silicon substrate layer, and the gallium nitride layer is arranged on the heavily doped high-conductivity region, so that the heavily doped high-conductivity region isolates an electric field between a drain electrode and a source electrode on the gallium nitride layer, thereby effectively avoiding electric field coupling between the gallium nitride layer and the silicon substrate layer, reducing loss on the silicon substrate layer caused by electric field coupling, and enabling the gallium nitride semiconductor device to have better conductivity.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic overall view of a gan semiconductor device according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a silicon substrate layer according to a first embodiment of the present invention;
fig. 3 is a schematic structural diagram of a gallium nitride layer according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a first sacrificial layer and a P-type doped region according to a second embodiment of the present invention;
fig. 5 is a schematic structural diagram of the second sacrificial layer and the N-type doped region according to the second embodiment of the invention.
Wherein, in the figures, the respective reference numerals:
1-a gallium nitride layer; an 11-i-GaN layer; 12-ALGaN layer; a 13-n-GaN layer; 14-a source electrode; 15-a drain electrode; 16-a gate;
2-heavily doped high conductivity regions; a 21-N type doped region; 22-P type doped region; 23-depletion layer;
3-a silicon substrate layer; 41-a second sacrificial layer; 42-first sacrificial layer.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
It will be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, as used herein, refer to an orientation or positional relationship indicated in the drawings that is solely for the purpose of facilitating the description and simplifying the description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and is therefore not to be construed as limiting the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
Example one
Referring to fig. 1 to 3 together, the present embodiment provides a gan semiconductor device, which includes a gan layer 1, a silicon substrate layer 3 and a heavily doped high-conductivity region 2. The heavily doped high-conductivity region 2 is a doped region formed by injecting impurities in the form of ions into the upper surface layer of the silicon substrate layer 3, and the heavily doped high-conductivity region 2 comprises a plurality of N-type doped regions and P-type doped regions which are alternately arranged at intervals; a gallium nitride layer 1 is disposed over the heavily doped highly conductive region 2.
In the gallium nitride semiconductor device in the embodiment, impurities are implanted into the upper surface layer of the silicon (Si) substrate layer 3 in the form of ions, so that the heavily doped high-conductivity region 2 is formed between the silicon substrate layer 3 and the gallium nitride (GaN) layer 1, and the heavily doped high-conductivity region 2 isolates an electric field between a drain electrode and a source electrode in the gallium nitride layer 1, thereby effectively avoiding electric field coupling between the gallium nitride layer 1 and the silicon substrate layer 3, and reducing loss generated on the silicon substrate layer 3 due to electric field coupling.
In addition, as shown in fig. 1, N in fig. 1 is an N-type doped region, P in fig. 1 is a P-type doped region, and the heavily doped high-conductivity region 2 includes a plurality of N-type doped regions and P-type doped regions alternately arranged to form a plurality of PN junctions. Because the N-type doped regions and the P-type doped regions are alternately arranged at intervals, a depletion layer 23 can be automatically formed when the two adjacent N-type doped regions and the P-type doped regions are close to each other, the depletion layer 23 is a high-resistance region with a very small number of current carriers under the double effects of drift motion and diffusion of a PN junction, and the isolation of the heavily doped high-conductivity region 2 from an electric field can be effectively improved.
In one embodiment, as shown in fig. 3, the gallium nitride layer 1 includes an i-GaN layer 11, an ALGaN layer 12, and an n-GaN layer 13 grown from bottom to top, the upper surface of the n-GaN layer 13 is provided with a gate 16, the upper surfaces of two ends of the ALGaN layer 12 are respectively provided with a drain electrode 15 and a source electrode 14, and the drain electrode 15 and the source electrode 14 penetrate through the n-GaN layer.
In one embodiment, the impurities implanted into the surface layer ions on the silicon substrate layer mainly comprise boron and phosphorus, wherein the impurities forming the N-type doped region comprise phosphorus, and the impurities forming the P-type doped region comprise boron.
In one embodiment, the concentration of impurities in surface ions implanted into the silicon substrate layer is in a range of 1018ion/cm3-1020ion/cm3. The doping concentrations of the impurities implanted into the N-type doped region and the P-type doped region in this example may be the same or different as long as the concentrations are such that the heavily doped high-conductivity region 2 can be formed.
It should be noted that in the present embodiment, the electric field loss generated on the silicon substrate layer 3 is mainly generated by capacitive coupling and inductive coupling, but the amount of loss generated by inductive coupling is very small and can be almost ignored compared with capacitive coupling. In the implementation, impurities are injected into the upper surface layer of the silicon substrate layer 3 in an ion mode to form the heavily doped high-conductivity region 2, and the heavily doped high-conductivity region 2 isolates the silicon substrate layer 3 from the gallium nitride layer 1, so that the capacitive coupling loss generated on the silicon substrate layer 3 is reduced, and the loss generated by the silicon substrate layer 3 due to electric field coupling is further reduced.
Example two
The embodiment provides a method for manufacturing a gallium nitride semiconductor device, which specifically comprises the following steps:
s10: and forming a heavily doped high-conductivity region in the upper surface layer of the silicon substrate layer, wherein the heavily doped high-conductivity region comprises a plurality of N-type doped regions and P-type doped regions which are alternately arranged at intervals.
Before manufacturing the gallium nitride semiconductor device, a silicon substrate layer needs to be obtained in advance, so that a heavily doped high-conductivity region is formed on the upper surface layer of the silicon substrate layer in the following process, and then a gallium nitride layer is formed on the heavily doped high-conductivity region.
Implanting impurities into the upper surface of the silicon substrate layer in the form of ions to diffuse and penetrate the impurity ions into the silicon substrate layer to form heavy dopingA highly conductive region. The formed heavily doped high-conductivity region is a doped region formed by alternately arranging a plurality of N-type doped regions and a plurality of P-type doped regions. Wherein, the concentration range of the impurity implanted into the surface layer ions on the silicon substrate layer can be 1018ion/cm3-1020ion/cm3The implanted impurities mainly comprise boron and phosphorus, wherein the impurities for forming the N-type doped region comprise phosphorus, and the impurities for forming the P-type doped region comprise boron. The doping concentration of the impurities injected into the N-type doping region and the P-type doping region can be the same or different, as long as the concentration can meet the requirement of forming a heavily doped high-conductivity region. In addition, in the process of implanting impurities into the upper surface layer of the silicon substrate layer to form the N-type doped region and the P-type doped region, the energy of the impurities implanted into the formed N-type doped region and the formed P-type doped region needs to be more than 180kev (preferably 180kev), and the dose of the implanted impurities is 1015(/cm2)-1016(/cm2) (preferably 10)16(/cm2))。
S20: and growing a gallium nitride layer on the heavily doped high-conductivity region.
After a heavily doped high-conductivity region is formed on the upper surface of the silicon substrate layer, gallium nitride grows on the upper surface of the heavily doped high-conductivity region to form a gallium nitride layer so as to obtain a gallium nitride semiconductor device, so that the gallium nitride layer and the silicon substrate layer are isolated by the heavily doped high-conductivity region in the gallium nitride semiconductor device, the electric field of the subsequent gallium nitride layer is reduced from diffusing to the silicon substrate layer, and the electric field loss is reduced.
According to the gallium nitride semiconductor device manufactured by the manufacturing method in the embodiment, the heavily doped high-conductivity region is formed on the upper surface of the silicon substrate layer, and the electric field on the gallium nitride layer is isolated, so that the electric field coupling between the gallium nitride layer and the silicon substrate layer is avoided, the loss generated by the electric field coupling on the silicon substrate layer is reduced, and the gallium nitride semiconductor device has better conductivity.
In an embodiment, in step S10, forming a heavily doped high conductivity region in the upper surface layer of the silicon substrate layer, the method specifically includes the following steps:
s11: and forming a first sacrificial layer on the upper surface of the silicon substrate layer, and performing first ion implantation on the upper surface of the silicon substrate layer based on the first sacrificial layer to form an N-type doped region.
Specifically, as shown in fig. 4, the oxide layer on the upper surface layer of the silicon substrate layer 3 is removed by etching; then, baking the silicon substrate layer 3 at a high temperature to remove water vapor on the upper surface of the silicon substrate layer 3, optimizing the state of the upper surface of the silicon substrate layer and improving the adhesive force of the photoresist; then, photoresist coating is carried out on the upper surface layer of the silicon substrate layer, and a required pattern is formed through exposure and development; finally, the oxide layer is selectively protected and wet-etched using the photoresist as a mask to form the first sacrificial layer 42.
Further, after the first sacrificial layer 42 is formed, ion implantation is selectively performed using the photoresist that has been formed previously as a mask, that is, first ion implantation is performed on the upper surface layer of the silicon substrate layer that is not covered with the first sacrificial layer, and an impurity containing phosphorus is implanted to form the N-type doped region 22.
S12: and removing the first sacrificial layer, forming a second sacrificial layer on the upper surface of the silicon substrate layer, and performing second ion implantation on the upper surface of the silicon substrate layer based on the second sacrificial layer to form a P-type doped region.
Specifically, as shown in fig. 5, after the N-type doped region 22 is formed, the first sacrificial layer 42 is removed, i.e., the photoresist adhered to the surface of the silicon wafer is stripped off by chemical or physical means; then, the second sacrificial layer 41 is formed on the upper surface of the silicon substrate layer 3 by the same method and steps as those of step S11.
Further, after the second sacrificial layer 41 is formed, ion implantation is selectively performed using the photoresist that has been formed previously as a mask, that is, second ion implantation is performed on the upper surface layer of the silicon substrate layer that does not cover the second sacrificial layer 41, and an impurity containing boron is implanted to form the P-type doped region 21.
After the N-type doped region and the P-type doped region are formed, the second sacrificial layer 41 on the second type region is removed, and heavily doped high-conductivity regions including the N-type doped region and the P-type doped region which are alternately arranged at intervals on the upper surface layer of the silicon substrate layer are obtained. After the N-type doped region and the P-type doped region are formed, depletion layers are automatically formed when the two adjacent N-type doped regions and the two adjacent P-type doped regions are close to each other.
In another embodiment, after the first sacrificial layer is formed on the upper surface of the silicon substrate layer, a second ion implantation may be performed on the upper surface of the silicon substrate layer based on the first sacrificial layer, an impurity containing boron is implanted to form a P-type doped region, then the first sacrificial layer is removed, a second sacrificial layer is formed on the upper surface of the silicon substrate layer, a first ion implantation is performed on the upper surface of the silicon substrate layer based on the second sacrificial layer, and an impurity containing phosphorus is implanted to form an N-type doped region.
In this embodiment, form first sacrificial layer at the upper surface layer of silicon substrate layer, carry out first ion implantation based on first sacrificial layer to the upper surface layer of silicon substrate layer, form N type doped region, then get rid of first sacrificial layer, form second sacrificial layer at the upper surface layer of silicon substrate layer, carry out second ion implantation based on second sacrificial layer to the upper surface layer of silicon substrate layer, form P type doped region, the process of forming heavily doped high-conductivity region in the upper surface layer of silicon substrate layer has been clarified, carry out impurity ion implantation twice, can simplify the technology, and before carrying out impurity ion implantation, each regional mutual interval independence can be guaranteed to the sacrificial layer that forms, mix when avoiding impurity ion implantation, thereby avoid the infiltration of impurity.
In an embodiment, before step S20, that is, before growing the gallium nitride layer on the heavily doped high-conductivity region, the method further includes the following steps:
s01: and carrying out high-temperature annealing treatment on the heavily doped high-conductivity region for a first preset time at a preset temperature.
After impurity ions are injected into the ions on the upper surface of the silicon substrate layer to form the heavily doped high-conductivity region, high-temperature annealing treatment needs to be carried out on the heavily doped high-conductivity region on the silicon substrate layer in an environment with a preset temperature so as to ensure the stability of the heavily doped high-conductivity region. The duration of the high-temperature annealing treatment is a first preset duration.
For example, the preset temperature is 900 ℃, the first preset time is 5 hours, after impurity ions are implanted into ions on the upper surface of the silicon substrate layer to form a heavily doped high-conductivity region, high-temperature annealing treatment is performed on the heavily doped high-conductivity region on the silicon substrate layer for 5 hours at the environment of 900 ℃, so as to ensure the stability of the heavily doped high-conductivity region.
In this embodiment, the preset temperature is 900 ℃ and the first preset time period is 5 hours, which are only exemplary illustrations, in other embodiments, the preset temperature may be other temperatures, and the first preset time period may be other time periods, and details thereof are not repeated herein.
In this embodiment, after the heavily doped high-conductivity region is formed on the upper surface of the silicon substrate layer, and before the gallium nitride layer is grown on the heavily doped high-conductivity region, the stability of the heavily doped high-conductivity region is ensured by performing high-temperature annealing on the heavily doped high-conductivity region for a first preset duration at a preset temperature.
In an embodiment, in step S20, growing a gallium nitride layer on the heavily doped high-conductivity region, the method specifically includes the following steps: an upper surface layer of the heavily doped high-conductivity region;
s21: and growing the i-GaN on the upper surface layer of the heavily doped high-conductivity region.
S22: and growing an ALGaN layer on the i-GaN layer.
S23: and growing an n-GaN layer on the ALGaN layer.
After the heavily doped high-conductivity region is subjected to high-temperature annealing treatment for a first preset time, growing gallium nitride on the upper surface layer of the heavily doped high-conductivity region to obtain a gallium nitride layer. The gallium nitride layer comprises an i-GaN layer, an ALGaN layer and an n-GaN layer which grow from bottom to top. i-GaN grows on the upper surface layer of the heavily doped high-conductivity region, an ALGaN layer grows on the i-GaN layer, and finally an n-GaN layer grows on the ALGaN layer. And the total growth time of the gallium nitride layer is a second preset time.
For example, the second preset time is 1 hour, and then after the heavily doped high conductive region is subjected to high temperature annealing treatment, the i-GaN layer, the ALGaN layer and the n-GaN layer are sequentially grown on the heavily doped high conductive region for 1 hour to form the gallium nitride layer.
In this embodiment, the second preset time period of 1 hour is only an exemplary illustration, and in other embodiments, the second preset time period may also be other time periods, which are not described herein again.
In the embodiment, the specific process of growing the gallium nitride layer on the heavily doped high-conductivity region is determined by growing the i-GaN layer on the upper surface layer of the heavily doped high-conductivity region, then growing the ALGaN layer on the i-GaN layer, and finally growing the n-GaN layer on the ALGaN layer, so that a foundation is provided for obtaining a complete gallium nitride semiconductor device subsequently.
In an embodiment, in step S22, after growing the n-GaN layer on the ALGaN layer, the method further includes the following steps:
s31: and arranging a grid on the upper surface of the n-GaN layer.
After the gallium nitride layer is grown on the upper surface of the heavily doped high-conductivity region, different electrodes need to be arranged in the gallium nitride layer to obtain the gallium nitride semiconductor device. Wherein a Gate electrode (Gate) is disposed on the upper surface of the n-GaN layer.
S32: and respectively arranging a Drain electrode (Drain) and a Source electrode (Source) on the upper surfaces of two ends of the ALGaN layer, wherein the Drain electrode and the Source electrode penetrate through the n-GaN layer.
After the gallium nitride layer is obtained by growing the upper surface layer of the heavily doped high-conductivity region, a Drain electrode (Drain) and a Source electrode (Source) are respectively arranged on the upper surfaces of two ends of the ALGaN layer, and the Drain electrode and the Source electrode penetrate through the n-GaN layer.
The positions of the grid electrode, the drain electrode and the source electrode on the gallium nitride layer are shown in figure 3, the gallium nitride layer 1 comprises an i-GaN layer 11, an ALGaN layer 12 and an n-GaN layer 13 which grow from bottom to top, the grid electrode 16 is arranged on the upper surface of the n-GaN layer 13, the drain electrode 15 and the source electrode 14 are respectively arranged on the upper surfaces of two ends of the ALGaN layer 12, and the drain electrode 15 and the source electrode 14 penetrate through the n-GaN layer.
In this embodiment, the specific process of arranging different electrodes in the gallium nitride layer is refined by arranging the gate on the upper surface of the n-GaN layer, arranging the drain and the source on the upper surfaces of the two ends of the ALGaN layer respectively, and the drain and the source penetrate through the n-GaN layer, so that the specific positions of the gate, the drain and the source are determined.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.
The present invention is not limited to the above preferred embodiments, and any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
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