CN112187397A - Universal multichannel data synchronization method and device - Google Patents
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Abstract
The invention discloses a universal multichannel data synchronization method and a device, relating to the technical field of optical communication.A control circuit is arranged beside a receiving end, the positions of all frame headers of input data which possibly appear are compared with a frame header characteristic code pattern through the control circuit to obtain a code pattern comparison identifier, and according to the code pattern comparison identifier and a channel mask corresponding to the channel data, logical operation is carried out to obtain a frame header position indication and update a frame header sliding rule; and performing data selection on the integrated data at the receiving end according to the updated frame header sliding rule. The control circuit and the receiving end are separately processed in parallel, so that the time delay is reduced. Meanwhile, the same set of data channel and control circuit are time division multiplexed, so that multi-channel serial processing is realized, and chip resources are effectively saved.
Description
Technical Field
The invention relates to the technical field of optical communication, in particular to a universal multichannel data synchronization method and a universal multichannel data synchronization device.
Background
Telecommunication operators have strong requirements for realizing 5G business in 2020, and in order to meet the 5G requirements, communication standards such as Flexe (Flexible Ethernet) and Flexo (Flexible Optical Transport Network) are defined in sequence by international communication standards organizations such as the International Telecommunications Union and the like. In these communication protocols, a specific frame structure is defined, and a specific code pattern is adopted to realize data frame boundary positioning and data synchronization.
Meanwhile, with the increase of communication services, the 5G bearer network chip has strict requirements on bandwidth, power consumption, capacity and the like, the number of channels (clients) is multiplied, and in the conventional technology, a parallel processing mode is adopted at a receiving end to synchronize data from different channels. However, under the condition that the number of channels of the 5G bearing network chip is large, the method can greatly consume logic resources, increase chip power consumption, increase chip cost and reduce system competitiveness. In addition, the existing data synchronization systems such as FlexE, FlexO, PCS (Physical Coding Sublayer) layer 01 header synchronization and the like adopt different synchronization methods, which increases the risk of slice casting.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a universal multichannel data synchronization method and a universal multichannel data synchronization device, which can reduce the consumption of logic resources, the power consumption of a chip and the cost of the chip.
In order to achieve the above purposes, the technical scheme adopted by the invention is as follows: a general multi-channel data synchronization method comprises the following steps:
a control circuit is arranged beside a receiving end, and a frame header sliding rule, a mask rule and a data frame length suitable for each channel data are set;
the control circuit compares the possible positions of all frame headers of the input data with the characteristic code patterns of the frame headers to obtain code pattern comparison identifiers; caching the current code pattern comparison identifier, and integrating the current code pattern comparison identifier and the code pattern comparison identifier of the previous beat of data from the same channel according to the channel identifier; taking a channel mask corresponding to the channel data as a template, performing logic operation on the integrated code pattern comparison identifier according to bit sliding to obtain a frame header position indication, and updating a frame header sliding rule of the channel data;
integrating front and rear beat data from the same channel at a receiving end, and performing data selection on the integrated data according to a frame header sliding rule of the channel data to enable a frame header position to be positioned at the lowest position of a data frame;
and the control circuit rechecks the frame header feature code at the next expected position of the data after data selection.
On the basis of the technical scheme, the control circuit takes the channel mask corresponding to the channel data as a template, and performs logic operation on the integrated code pattern comparison identifier according to bit sliding to obtain a frame header position indication, and the method specifically comprises the following steps:
and taking a channel mask corresponding to the channel data as a template, matching the integrated code pattern identifier according to bit sliding, comparing the channel mask with the code pattern of a certain position, and determining that the position is the frame header position when all bit results are 1.
On the basis of the technical scheme, the control circuit integrates the current code pattern comparison identifier and the code pattern comparison identifier of the previous beat of data from the same channel according to the channel identifier, and the method specifically comprises the following steps:
and merging the current code pattern comparison identifier with the code pattern comparison identifier of the previous beat of data from the same channel, wherein the code pattern comparison identifier of the previous beat of data is in a high order.
On the basis of the technical scheme, the method integrates front and back two-beat data from the same channel at a receiving end, and performs data selection on the integrated data according to a frame header sliding rule of the channel data to enable a frame header position to be located at the lowest position of a data frame, and specifically comprises the following steps:
integrating front and back beat data from the same channel at a receiving end;
setting the data bit width of one clock cycle as N66 b, creating N data selection units;
inputting 66b blocks from 0 th to N-1 th bits to a first data selection unit, inputting 66b blocks from 1 st to N th bits to a second data selection unit, inputting 66b blocks from 2 nd to N +1 th bits to a third data selection unit, and so on, and inputting 66b blocks from N-1 th to 2N-2 th bits to a last data selection unit;
and obtaining the 66b block with the frame head position at the X bit according to the frame head sliding rule of the channel data, outputting the 66b block at the X bit of each data selection unit, and combining the output 66b blocks into a new data frame according to the sequencing arrangement of the data selection units.
On the basis of the technical scheme, the method further comprises the following steps: and performing data selection on the integrated data at a receiving end according to a frame header sliding rule of the channel data, so that bubbles are added to the frame header or the frame tail after the frame header is positioned at the lowest position of the data frame.
The invention also provides a general multichannel data synchronization device, comprising: the control circuit is arranged beside the receiving end;
the control circuit comprises a setting module, a characteristic code type comparison module, an identifier operation module and a frame header rechecking module:
the setting module is used for: setting frame header sliding rules, mask rules and data frame lengths suitable for each channel data;
the characteristic code pattern comparison module is used for: comparing the possible positions of all frame headers of the input data with the characteristic code patterns of the frame headers to obtain code pattern comparison identifiers; caching the current code pattern comparison identifier, and integrating the current code pattern comparison identifier and the code pattern comparison identifier of the previous beat of data from the same channel according to the channel identifier;
the identifier operation module is used for: taking a channel mask corresponding to the channel data as a template, performing logic operation on the integrated code pattern comparison identifier according to bit sliding to obtain a frame header position indication, and updating a frame header sliding rule of the channel data;
the frame header reinspection module is used for: performing data selection on the integrated data at a receiving end according to a frame header sliding rule of the channel data, and after the frame header position is located at the lowest position of the data frame, re-detecting a frame header feature code at a next data expected position after data selection;
the receiving end comprises a data integration module and a data selection module:
the data integration module is used for: integrating the front and back beat data from the same channel;
the data selection module is configured to: and performing data selection on the integrated data according to the frame header sliding rule of the channel data to enable the position of the frame header to be positioned at the lowest position of the data frame.
On the basis of the above technical solution, the identifier operation module is specifically configured to:
and taking a channel mask corresponding to the channel data as a template, matching the integrated code pattern identifier according to bit sliding, comparing the channel mask with the code pattern of a certain position, and determining that the position is the frame header position when all bit results are 1.
On the basis of the above technical solution, the feature code pattern comparison module is specifically configured to:
and merging the current code pattern comparison identifier with the code pattern comparison identifier of the previous beat of data from the same channel, wherein the code pattern comparison identifier of the previous beat of data is in a high order.
On the basis of the above technical solution, the data selection module is specifically configured to:
integrating the front and back beat data from the same channel;
setting the data bit width of one clock cycle as N66 b, creating N data selection units;
inputting 66b blocks from 0 th to N-1 th bits to a first data selection unit, inputting 66b blocks from 1 st to N th bits to a second data selection unit, inputting 66b blocks from 2 nd to N +1 th bits to a third data selection unit, and so on, and inputting 66b blocks from N-1 th to 2N-2 th bits to a last data selection unit;
and obtaining the 66b block with the frame head position at the X bit according to the frame head sliding rule of the channel data, outputting the 66b block at the X bit of each data selection unit, and combining the output 66b blocks into a new data frame according to the sequencing arrangement of the data selection units.
On the basis of the above technical solution, the receiving end further includes a bubble adding module, which is configured to: and performing data selection on the integrated data by the data selection module according to a frame header sliding rule of the channel data to enable the position of the frame header to be positioned at the lowest position of the data frame, and adding bubbles to the frame header or the frame tail.
Compared with the prior art, the invention has the advantages that:
the invention sets a control circuit beside the receiving end, compares the possible positions of all frame headers of the input data with the characteristic code pattern of the frame headers through the control circuit to obtain a code pattern comparison identifier, and performs logic operation according to the code pattern comparison identifier and a channel mask corresponding to the channel data to obtain frame header position indication and update the frame header sliding rule; and performing data selection on the integrated data at the receiving end according to the updated frame header sliding rule. The control circuit and the receiving end are separately processed in parallel, so that the time delay is reduced. Meanwhile, data synchronization of serial data from multiple channels is realized by arranging a control circuit beside the receiving end, and the serial data from the multiple channels share one set of receiving end and control circuit, so that chip resources are effectively saved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.
Fig. 1 is a schematic flowchart of a multichannel data synchronization method according to embodiment 1 of the present invention;
FIG. 2 is a schematic flow chart illustrating data selection for integrated data according to an embodiment of the present invention;
FIG. 3 is a flow chart of a multi-channel data synchronization method according to embodiment 2 of the present invention;
fig. 4 is a schematic structural diagram of a general multi-channel data synchronization apparatus according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some embodiments, but not all embodiments, of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.
The embodiment of the invention provides a universal multichannel data synchronization method, which comprises the following steps:
a control circuit is arranged beside a receiving end, and a frame header sliding rule, a mask rule and a data frame length suitable for each channel data are set;
the control circuit compares the possible positions of all frame headers of the input data with the characteristic code patterns of the frame headers to obtain code pattern comparison identifiers; caching the current code pattern comparison identifier, and integrating the current code pattern comparison identifier and the code pattern comparison identifier of the previous beat of data from the same channel according to the channel identifier; taking a channel mask corresponding to the channel data as a template, performing logic operation on the integrated code pattern comparison identifier according to bit sliding to obtain a frame header position indication, and updating a frame header sliding rule of the channel data;
integrating front and rear beat data from the same channel at a receiving end, and performing data selection on the integrated data according to a frame header sliding rule of the channel data to enable a frame header position to be positioned at the lowest position of a data frame;
and the control circuit rechecks the frame header feature code at the next expected position of the data after data selection.
The embodiment of the invention is provided with a control circuit beside a receiving end, compares the possible positions of all frame headers of input data with the characteristic code patterns of the frame headers through the control circuit to obtain code pattern comparison identifiers, and performs logic operation according to the code pattern comparison identifiers and the set channel masks to obtain frame header position indication and update the frame header sliding rules; and performing data selection on the integrated data in the receiving end according to the updated frame header sliding rule. The control circuit and the receiving end are separately processed in parallel, so that the time delay is reduced. Meanwhile, the generalized multi-channel serial data synchronization is realized according to the channel identification, and multiple channels share one set of receiving end and control circuit, so that the chip resources are effectively saved.
Further, in the conventional technology, a method for framing data of different channel data includes: presetting a certain position as the position of the frame header, starting a data frame period from the position, rechecking the frame header feature code at the next position, if the verification is passed, the position is the position of the frame header, if the verification is not passed, shifting a bit as the position of the frame header, and rechecking for one data frame period until the position of the frame header is found, so that the frame period is fixed. The embodiment of the invention calculates the code type comparison identifiers corresponding to the positions of all the frame headers which are possibly generated in parallel, and performs logical operation through the code type comparison identifiers to obtain the frame header position indication, and then performs frame header characteristic code rechecking, thereby shortening the time consumption of data framing and effectively accelerating multi-channel data synchronization.
Preferably, the initial sliding rule is a position of the frame header in the current data, and the initialization value is 0.
As a preferred embodiment, the control circuit performs a logical operation on the integrated code pattern comparison identifier according to bit sliding by using a channel mask corresponding to the channel data as a template to obtain a frame header position indication, and specifically includes the following steps:
and taking a channel mask corresponding to the channel data as a template, matching the integrated code pattern identifier according to bit sliding, comparing the channel mask with the code pattern of a certain position, and determining that the position is the frame header position when all bit results are 1.
As a preferred embodiment, the control circuit integrates the current pattern comparison identifier and the pattern comparison identifier of the previous beat of data from the same channel according to the channel identifier, and specifically includes the following steps:
and merging the current code pattern comparison identifier with the code pattern comparison identifier of the previous beat of data from the same channel, wherein the code pattern comparison identifier of the previous beat of data is in a high order.
As a preferred embodiment, integrating two previous and next beat data from the same channel at a receiving end, and performing data selection on the integrated data according to a frame header sliding rule of the channel data to make a frame header position located at a lowest position of a data frame specifically includes the following steps:
integrating front and back beat data from the same channel at a receiving end;
setting the data bit width of one clock cycle as N66 b, creating N data selection units;
inputting 66b blocks from 0 th to N-1 th bits to a first data selection unit, inputting 66b blocks from 1 st to N th bits to a second data selection unit, inputting 66b blocks from 2 nd to N +1 th bits to a third data selection unit, and so on, and inputting 66b blocks from N-1 th to 2N-2 th bits to a last data selection unit;
and obtaining the 66b block with the frame head position at the X bit according to the frame head sliding rule of the channel data, outputting the 66b block at the X bit of each data selection unit, and combining the output 66b blocks into a new data frame according to the sequencing arrangement of the data selection units.
Preferably, the method further comprises the steps of: and performing data selection on the integrated data at a receiving end according to a frame header sliding rule of the channel data, so that bubbles are added to the frame header or the frame tail after the frame header is positioned at the lowest position of the data frame.
Referring to fig. 1, embodiment 1 of the present invention is described by taking the FlexE aware mode serial framing as an example. The Flexe Group in this example 1 has two Flexe instances, and each instance has no unavailable slot. It should be noted that the embodiment of the present invention is simultaneously applicable to data synchronization systems such as a FlexE Unaware mode, a FlexE terminal mode, a FlexO, and 01 header synchronization.
The specific transmission steps are as follows:
step 100: the chip is powered on, information such as a frame header sliding rule and a mask rule applicable to data of each client channel, a FlexeAware frame length of each channel and the like is initialized by software or hardware, wherein the frame header sliding rule configured in the channel where the embodiment is located is 0, the mask rule is configured into 2 Flexe instances, and the FlexeAware frame length is configured into 327680 66bits code blocks. Since the mask rule is set to 2 FlexE instances, the data bit width of one clock cycle is 8 66bits blocks, and the channel mask applicable to the channel data is configured to 0011_1111, wherein the irrelevant fields are masked by 1.
Step 101: the control circuit compares the data of the possible positions of all the frame headers with the characteristic code patterns of the frame headers at the receiving end to obtain code pattern comparison identifiers, and caches the code pattern comparison identifiers of the currently input data according to the client channel identification. Meanwhile, integrating the current code pattern comparison identifier with the previous code pattern comparison identifier of the data from the same channel; for example, after the input code pattern is compared with the feature code in a certain clock cycle, the 66bits code blocks of 1 st, 4 th and 5 th are matched with the frame header feature code pattern, and the comparison identifier is: 1000_1100, where 1 denotes a matching code block and 0 denotes a non-matching code block. Assuming that the alignment identifier of the next beat of data is all 0, the alignment identifiers of the two previous and next beats of data are integrated to be 1000_1100_0000_ 0000.
Step 102: the control circuit takes the channel mask configured in the step 100 as a template, matches the integrated code pattern identifier according to bit sliding, determines a certain position as a frame header position when the mask is successfully matched with the code pattern comparison identifier of the position, and updates a frame header sliding rule according to the position. If the mask matches successfully with the plurality of positions of the current pattern comparison identifier, the first position is identified as the frame header position. After finding the frame head position, the search for the frame head is not continued.
The channel mask configured in step 100 is used to perform a bitwise or operation on the integrated alignment indicator according to bit sliding from left to right. The bit-wise OR operation of the 8bits at the leftmost end (position 0) with the mask is as follows:
position No. 0: 1000_1100|0011_1111 → 1011_1111
Position No. 1: 0001_1000|0011_1111 → 0011_1111
Position No. 2: 0011_0000|0011_1111 → 0011_1111
Position No. 3: 0110_0000|0011_1111 → 0111_1111
Position No. 4: 1100_0000|0011_1111 → 1111_1111
Position No. 5: 1000_0000|0011_1111 → 1011_1111
…
Obviously, the result after the position 0 operation is not all bits are 1, and the comparison is continued by sliding 1bit to the right. After several comparisons, only 8bits data extracted from the four positions are operated with the channel mask, and all bit results are 1. Therefore, the 4 th position is identified as the frame header position.
Step 103: integrating front and back two-beat data from the same channel in a receiving end, and then performing data selection on the integrated data according to a frame header sliding rule corresponding to the client channel to enable the frame header position to be located at the lowest position of a data frame, as shown in fig. 2, specifically comprising the following steps:
integrating front and back beat data from the same channel at a receiving end;
if the data bit width of one clock cycle is 8 and 66b, 8 data selection units are created;
inputting a 0 th to 7 th bit 66b block to a first data selection unit, inputting a1 th to 8 th bit 66b block to a second data selection unit, inputting a2 th to 9 th bit 66b block to a third data selection unit, and so on, and inputting a 7 th to 14 th bit 66b block to a last data selection unit;
and obtaining a 66b block with the frame head position at the 4 th bit according to the frame head sliding rule of the channel data, outputting the 66b block at the 4 th bit of each data selection unit, and combining the output 66b blocks into a new data frame according to the sequencing arrangement of the data selection units.
Step 104: and adding bubbles at proper positions such as a frame head or a frame tail in a receiving end, so that overhead is at the top position of the data of the current beat, wherein the step is an optional step.
Step 105: the control circuit rechecks the frame header feature code at the expected position (i.e. the frame header position) of the data after data selection. When the frame header feature codes of a plurality of continuous expected positions are matched with the mask, the frame header is considered to be found. When the signature code of the desired location does not match the mask, the circuit state returns to step 101 to be searched again.
It should be noted that steps 101 and 102 are parallel to steps 103 and 104. Step 103 and step 104 are reception-side data stream processing steps. Step 101, step 102, and step 105 are control circuit steps, and the implementation steps of the control circuit are put in a receiving end bypass, which does not affect data delay.
The embodiment of the invention is not only suitable for the data synchronization of Flexe, but also suitable for the data synchronization of multi-channel OTUC (optical channel transmission unit). Referring to fig. 3, OTUC data synchronization is exemplified in embodiment 2.
Step 200: and powering on the chip, and initializing information such as a frame header sliding rule applicable to data of each channel, a mask rule of each channel, a frame length of each channel OTUC and the like by software or hardware, wherein the frame header sliding rule configured for the channel where the embodiment is located is 3. The masking rule is configured for a six byte full detection mode of OA1OA 2. The OTUC frame length is configured to 15296 bytes;
the framing of the OTUC is searched by taking bytes as a unit, the frame header feature code of the OTUC is 6 bytes, and the value of the frame header feature code is F6F6F 6-282828; specifically, if a 6 byte full search is performed then the mask is configured to 000000; if only the third and fourth bytes need to be retrieved, the mask is configured to 110011; the setting is specifically carried out according to the requirements of users.
Step 201: the control circuit compares the data of the possible positions of all the frame headers with the characteristic code patterns of the frame headers at the receiving end to obtain code pattern comparison identifiers, and caches the code pattern comparison identifiers of the currently input data according to the channel identifiers. Meanwhile, integrating the current code pattern comparison identifier with the previous code pattern comparison identifier of the data from the same channel;
step 202: the control circuit takes the channel mask as a template, matches the integrated code pattern identifier according to bit sliding, and determines a certain position as a frame header position when the mask is successfully matched with the code pattern comparison identifier of the position, and updates a frame header sliding rule. If the mask matches successfully with the plurality of positions of the current pattern comparison identifier, the first position is identified as the frame header position. After finding the frame head position, the search for the frame head is not continued.
Step 203: integrating front and rear beat data from the same channel in a receiving end, and then selecting the integrated data according to a frame header sliding rule corresponding to the channel data to enable the position of a frame header to be positioned at the lowest position of a data frame;
step 204: and adding bubbles at proper positions such as a frame head or a frame tail in a receiving end, so that overhead is at the top position of the data of the current beat, wherein the step is an optional step.
Step 205: and the control circuit rechecks the frame header feature codes at the expected data positions after data selection. When the signatures of several consecutive desired locations match the mask, the frame header is considered to be found. When the signature code for the desired location does not match the mask, then the circuit state returns to step 201 to re-search.
It should be noted that step 201, step 202, step 203, and step 204 are parallel steps. Step 203 and step 204 are reception-side data stream processing steps. Step 201, step 202 and step 205 are control circuit steps, and the implementation steps of the control circuit are put on a receiving end for bypass, so that data delay is not influenced.
In the traditional technology, different channel data are synchronized by adopting a parallel processing mode. However, under the condition that the number of channels of the 5G bearing network chip is large, the method can greatly consume logic resources, increase chip power consumption, increase chip cost and reduce system competitiveness. In addition, the existing data synchronization systems such as FlexE, FlexO, PCS layer 01 header synchronization and the like adopt different synchronization methods, which increases the risk of slice casting.
The embodiment of the invention can realize synchronization of serial data streams from multiple channels in systems such as FlexE, FlexO, OTN, PCS layer 01 header synchronization and the like, thereby reducing the consumption of logic resources, reducing the power consumption of chips, reducing the cost and the risk of chip throwing and enhancing the competitiveness of system equipment.
Referring to fig. 4, an embodiment of the present invention further provides a general multi-channel data synchronization apparatus, including: the control circuit is arranged beside the receiving end;
the control circuit comprises a setting module, a characteristic code type comparison module, an identifier operation module and a frame header rechecking module:
the setting module is used for: setting frame header sliding rules, mask rules and data frame lengths suitable for each channel data;
the characteristic code pattern comparison module is used for: comparing the possible positions of all frame headers of the input data with the characteristic code patterns of the frame headers to obtain code pattern comparison identifiers; caching the current code pattern comparison identifier, and integrating the current code pattern comparison identifier and the code pattern comparison identifier of the previous beat of data from the same channel according to the channel identifier;
the identifier operation module is used for: taking a channel mask corresponding to the channel data as a template, performing logic operation on the integrated code pattern comparison identifier according to bit sliding to obtain a frame header position indication, and updating a frame header sliding rule of the channel data;
the frame header reinspection module is used for: performing data selection on the integrated data at a receiving end according to a frame header sliding rule of the channel data, and after the frame header position is located at the lowest position of the data frame, re-detecting a frame header feature code at a next data expected position after data selection;
the receiving end comprises a data integration module and a data selection module:
the data integration module is used for: integrating the front and back beat data from the same channel;
the data selection module is configured to: and performing data selection on the integrated data according to the frame header sliding rule of the channel data to enable the position of the frame header to be positioned at the lowest position of the data frame.
Preferably, the signature pattern comparison module is specifically configured to:
and merging the current code pattern comparison identifier with the code pattern comparison identifier of the previous beat of data from the same channel, wherein the code pattern comparison identifier of the previous beat of data is in a high order.
As a preferred embodiment, the identifier operation module performs a logical operation on the integrated code pattern comparison identifier according to bit sliding by using a channel mask corresponding to the channel data as a template to obtain a frame header position indication, and specifically includes the following steps:
and taking a channel mask corresponding to the channel data as a template, matching the integrated code pattern identifier according to bit sliding, comparing the channel mask with the code pattern of a certain position, and determining that the position is the frame header position when all bit results are 1.
As a preferred embodiment, the data selection module is specifically configured to:
integrating the front and back beat data from the same channel;
setting the data bit width of one clock cycle as N66 b, creating N data selection units;
inputting 66b blocks from 0 th to N-1 th bits to a first data selection unit, inputting 66b blocks from 1 st to N th bits to a second data selection unit, inputting 66b blocks from 2 nd to N +1 th bits to a third data selection unit, and so on, and inputting 66b blocks from N-1 th to 2N-2 th bits to a last data selection unit;
and obtaining the 66b block with the frame head position at the X bit according to the frame head sliding rule of the channel data, outputting the 66b block at the X bit of each data selection unit, and combining the output 66b blocks into a new data frame according to the sequencing arrangement of the data selection units.
Preferably, the receiving end further comprises a bubble adding module, configured to: and performing data selection on the integrated data by the data selection module according to a frame header sliding rule of the channel data to enable the position of the frame header to be positioned at the lowest position of the data frame, and adding bubbles to the frame header or the frame tail.
Preferably, the initial sliding rule is a position of the frame header in the current data, and the initialization value is 0.
The embodiment of the invention is provided with a control circuit beside a receiving end, compares the possible positions of all frame headers of input data with the characteristic code patterns of the frame headers through the control circuit to obtain code pattern comparison identifiers, and performs logic operation according to the code pattern comparison identifiers and the set channel masks to obtain frame header position indication and update the frame header sliding rules; and performing data selection on the integrated data in the receiving end according to the updated frame header sliding rule. The control circuit and the receiving end are separately processed in parallel, so that the time delay is reduced. Meanwhile, the generalized multi-channel serial data synchronization is realized according to the channel identification, and multiple channels share one set of receiving end and control circuit, so that the chip resources are effectively saved; the method has strong expansibility, and can be widely applied to 5G bearing networks such as FlexE, FlexO, ODUCn and the like. Meanwhile, bubble filling is added at the head or the tail of the line, so that the overhead is in the specific position of the corresponding data beat under the condition that the frame length is not integral multiple of the data bit width, and the subsequent processing is facilitated.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
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