CN100499405C - Implementing method of parallel frame locator for optical synchronous digital transmission system - Google Patents
Implementing method of parallel frame locator for optical synchronous digital transmission system Download PDFInfo
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- CN100499405C CN100499405C CNB031398391A CN03139839A CN100499405C CN 100499405 C CN100499405 C CN 100499405C CN B031398391 A CNB031398391 A CN B031398391A CN 03139839 A CN03139839 A CN 03139839A CN 100499405 C CN100499405 C CN 100499405C
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Abstract
The invention relates to a frame locating technique in optical synchronous digital transmission system; during STM-N frame data process of the optical synchronous digital transmission system, making frame locating operation at parallel system clock, and its characters: it can reduce working frequency of frame locator and provide system stability; and can select proper parallel digit according to actual requirement to apply to frame locating operation in the different-line speed frame data process.
Description
Technical field:
The present invention relates to the frame alignment technology in the optical synchronization digital transmission system (being called for short SDH/SONET).
Background technology:
Arrange to have the different expense of two big classes in the SDH frame structure, i.e. section overhead SOH and path overhead POH, the maintenance of the section of being respectively applied for layer and channel layer.Include among the section overhead SOH and decide frame information, be used to safeguard and information and other operating functions of performance monitoring.
Frame alignment byte A1 among the SOH and A2 are used for discerning the original position of frame.A1 and A2 have definite binary numeral, and promptly the A1 position 11110110, and A2 is 00101000.Concentrate in the STM-1 frame and arranged 6 frame alignment bytes, account for about 0.25% of frame length.Selecting this frame alignment length is the result who has taken all factors into consideration various factors, particularly pseudo-synchronous probability and synchronously settling time the two.Arrange according to existing, pseudo-synchronous probability equals (1/2)
48=3.55 x 10
-15, being almost 0, also can shorten greatly settling time synchronously.
ITU-T stipulates that choosing its subclass gets final product at present, but in order to guarantee combination property, is difficult for being less than 4 bytes.The specific implementation requirement is made a start, and whole 6 bytes are all necessary to be sent out, and receiving end allows certain flexibility, can select needed frame alignment pattern according to actual conditions, can not influence intercommunication.For the STM-N frame, then frame alignment byte is made up of 3N A1 byte and 3N A2 byte.
A kind of serial implementation method of frame alignment device as shown in Figure 1.In Fig. 1, frame alignment device operating rate is a linear speed speed.By choosing suitable frame alignment pattern, data and the frame alignment pattern that is latched in the d type flip flop compared, if both are equal, then think to have searched frame head; If both are unequal, then think not search frame head.
The serial implementation method of above-mentioned frame alignment device, need circuit working in very high frequency (as for STM-16, line speed is 2488.320Mbit/s, and circuit work frequency is 2488.320MHz so), thus cause circuit to realize difficulty, production and processing cost height.And adopt 8xK parallel-by-bit frame alignment device of the present invention, by selecting suitable K value (K is a positive integer), can reduce circuit work frequency, reduce the production and processing cost (as for STM-16, line speed is 2488.320Mbit/s, when selecting N to be 4, circuit work frequency only be line speed 1/32).
This purpose is: the optical synchronization digital transmission system concurrent frame locator under the 8xK parallel-by-bit speed in a kind of Optical synchronization digital transmission network is provided.
Summary of the invention:
Finish with content as follows;
A, search frame head, be specially: suppose that K is 1, the frame alignment pattern is 2A12A2, when searching two A1 bytes and and then searching 2 A2 bytes, has just searched frame head, wherein the bit wide of K value representation parallel data/8;
B, latch the 8bit parallel input data of 6 parallel clock beats to reg0[7:0]～reg5[7:0], compare with described frame alignment pattern simultaneously, be respectively:
Comparator 1:reg1[7:0]+reg2[7:0]+reg3[7:0]+reg4[7:0] and the frame alignment pattern
Comparator 2:reg0[7]+reg1[6:0]+reg2[7:0]+reg3[7:0]+reg4[7:0] and the frame alignment pattern
Comparator 3:reg0[7:6]+reg1[5:0]+reg2[7:0]+reg3[7:0]+reg4[7:0] and the frame alignment pattern
Comparator 4:reg0[7:5]+reg1[4:0]+reg2[7:0]+reg3[7:0]+reg4[7:0] and the frame alignment pattern
Comparator 5:reg0[7:4]+reg1[3:0]+reg2[7:0]+reg3[7:0]+reg4[7:0] and the frame alignment pattern
Comparator 6:reg0[7:3]+reg1[2:0]+reg2[7:0]+reg3[7:0]+reg4[7:0] and the frame alignment pattern
Comparator 7:reg0[7:2]+reg1[1:0]+reg2[7:0]+reg3[7:0]+reg4[7:0] and the frame alignment pattern
Comparator 8:reg0[7:1]+reg1[0]+reg2[7:0]+reg3[7:0]+reg4[7:0] and the frame alignment pattern
C, according to the result of 8 comparators, carry out priority encoding, priority order from high to low is followed successively by comparator 1～comparator 8; According to the output of encoder, the 8bit parallel input data is selected to be combined into correct data code flow output then:
If d comparator 1 equates that 8 parallel-by-bit data are output as reg5
If comparator 2 equates that 8 parallel-by-bit data are output as reg5[6:0]+reg4[7]
If comparator 3 equates that 8 parallel-by-bit data are output as reg5[5:0]+reg4[7:6]
If comparator 4 equates that 8 parallel-by-bit data are output as reg5[4:0]+reg4[7:5]
If comparator 5 equates that 8 parallel-by-bit data are output as reg5[3:0]+reg4[7:4]
If comparator 6 equates that 8 parallel-by-bit data are output as reg5[2:0]+reg4[7:3]
If comparator 7 equates that 8 parallel-by-bit data are output as reg5[1:0]+reg4[7:2]
If comparator 8 equates that 8 parallel-by-bit data are output as reg5[0]+reg4[7:1]
E, according to the SDH frame structure, can determine the position of frame alignment pattern in the SDH frame structure;
Like this, by step b and d, just can determine frame head and recover correct data code flow; This concurrent frame locator is operated under the parallel speed, and speed is 1/8 of line speed, can replace the consecutive frame locator fully on the function.
8xK concurrent frame locator of the present invention can be implemented in and carry out the frame alignment operation under the parallel clock (1/8K of line speed) in the STM-N frame data are handled.Logic statement of the present invention is simple, and the circuit implementation is simple and clear; Compare with the frame alignment device under the linear speed speed, operating frequency is reduced to the 1/8K of linear speed frequency, has increased the stability of a system, has reduced power consumption, is easy to technology and realizes.These all bring huge facility in the production application of reality, for cost has been saved in the production of machine system.
Description of drawings:
Accompanying drawing 1 is the circuit structure diagram that is operated in the consecutive frame locator under the linear speed speed;
Accompanying drawing 2 is to adopt Data Stream Processing FB(flow block) in the SDH equipment of Fig. 1 structure;
Accompanying drawing 3 is the functional block diagrams (N=1) that adopt concurrent frame locator of the present invention;
Accompanying drawing 4 is the process flow block diagram that adopt data flow in the SDH equipment of the present invention.
Execution mode:
Below for ease of explanation, suppose that K is 1, the frame alignment pattern is 2A12A20xF6F62828, promptly searches two A1 bytes and and then search 2 A2 bytes to think and searched frame head.Concurrent frame locator function block diagram as shown in Figure 3.
The 8bit parallel input data that latchs 6 parallel clock beats is to reg0[7:0]～reg5[7:0], carry out 8 parallel 32 bit comparisons simultaneously, be respectively:
Comparator 1:reg1[7:0]+reg2[7:0]+reg3[7:0]+reg4[7:0] and the frame alignment pattern
Comparator 2:reg0[7]+reg1[6:0]+reg2[7:0]+reg3[7:0]+reg4[7:0] and the frame alignment pattern
Comparator 3:reg0[7:6]+reg1[5:0]+reg2[7:0]+reg3[7:0]+reg4[7:0] and the frame alignment pattern
Comparator 4:reg0[7:5]+reg1[4:0]+reg2[7:0]+reg3[7:0]+reg4[7:0] and the frame alignment pattern
Comparator 5:reg0[7:4]+reg1[3:0]+reg2[7:0]+reg3[7:0]+reg4[7:0] and the frame alignment pattern
Comparator 6:reg0[7:3]+reg1[2:0]+reg2[7:0]+reg3[7:0]+reg4[7:0] and the frame alignment pattern
Comparator 7:reg0[7:2]+reg1[1:0]+reg2[7:0]+reg3[7:0]+reg4[7:0] and the frame alignment pattern
Comparator 8:reg0[7:1]+reg1[0]+reg2[7:0]+reg3[7:0]+reg4[7:0] and the frame alignment pattern
According to the result of 8 comparators, carry out priority encoding, priority order from high to low is followed successively by comparator 1～comparator 8, according to the output of encoder, the 8bit parallel input data is selected to be combined into correct data code flow output then:
If comparator 1 equates that 8 parallel-by-bit data are output as reg5
If comparator 2 equates that 8 parallel-by-bit data are output as reg5[6:0]+reg4[7]
If comparator 3 equates that 8 parallel-by-bit data are output as reg5[5:0]+reg4[7:6]
If comparator 4 equates that 8 parallel-by-bit data are output as reg5[4:0]+reg4[7:5]
If comparator 5 equates that 8 parallel-by-bit data are output as reg5[3:0]+reg4[7:4]
If comparator 6 equates that 8 parallel-by-bit data are output as reg5[2:0]+reg4[7:3]
If comparator 7 equates that 8 parallel-by-bit data are output as reg5[1:0]+reg4[7:2]
If comparator 8 equates that 8 parallel-by-bit data are output as reg5[0]+reg4[7:1]
According to the SDH frame structure, can determine the position of frame alignment pattern in the SDH frame structure.Like this, by step b and d, just can determine frame head and recover correct data code flow; This concurrent frame locator is operated under the parallel speed, and speed is 1/8 of line speed, can replace the consecutive frame locator fully on the function.
Fig. 1 is the circuit structure that is operated in the consecutive frame locator under the linear speed speed.Under the online rate that hastens of this circuit working,,, then think and found frame head if equate to comparing with the frame alignment pattern behind the serial linear speed data latching.
Fig. 2 adopts Data Stream Processing FB(flow block) in the SDH equipment of Fig. 1 structure.Receive the linear speed data of bit form, extract clock, subsequent processes is carried out after string and the conversion in the consecutive frame location.
Fig. 3 is the functional block diagram (N=1) that adopts concurrent frame locator of the present invention.The existing narration in detailed process front.
Fig. 4 is the process flow block diagram that adopts data flow in the SDH equipment of the present invention.Receive the linear speed data of bit form, extract clock, string and conversion, concurrent frame carries out subsequent treatment behind the location.
Comparison diagram 2 and Fig. 4, the operating frequency of concurrent frame locator has reduced, thereby the stability of system is provided, and is easy to technology and realizes.
Claims (1)
1, a kind of implementation method of optical synchronization digital transmission system concurrent frame locator is characterized in that: finish with content as follows;
A, search frame head, be specially: suppose that K is 1, the frame alignment pattern is 2A12A2, when searching two A1 bytes and and then searching 2 A2 bytes, has just searched frame head, wherein the bit wide of K value representation parallel data/8;
B, latch the 8bit parallel input data of 6 parallel clock beats to reg0[7:0]～reg5[7:0], compare with described frame alignment pattern simultaneously, be respectively:
Comparator 1:reg1[7:0]+reg2[7:0]+reg3[7:0]+reg4[7:0] and the frame alignment pattern
Comparator 2:reg0[7]+reg1[6:0]+reg2[7:0]+reg3[7:0]+reg4[7:0] and the frame alignment pattern
Comparator 3:reg0[7:6]+reg1[5:0]+reg2[7:0]+reg3[7:0]+reg4[7:0] and the frame alignment pattern
Comparator 4:reg0[7:5]+reg1[4:0]+reg2[7:0]+reg3[7:0]+reg4[7:0] and the frame alignment pattern
Comparator 5:reg0[7:4]+reg1[3:0]+reg2[7:0]+reg3[7:0]+reg4[7:0] and the frame alignment pattern
Comparator 6:reg0[7:3]+reg1[2:0]+reg2[7:0]+reg3[7:0]+reg4[7:0] and the frame alignment pattern
Comparator 7:reg0[7:2]+reg1[1:0]+reg2[7:0]+reg3[7:0]+reg4[7:0] and the frame alignment pattern
Comparator 8:reg0[7:1]+reg1[0]+reg2[7:0]+reg3[7:0]+reg4[7:0] and the frame alignment pattern
C, according to the result of 8 comparators, carry out priority encoding, priority order from high to low is followed successively by comparator 1～comparator 8; According to the output of encoder, the 8bit parallel input data is selected to be combined into correct data code flow output then:
If d comparator 1 equates that 8 parallel-by-bit data are output as reg5
If comparator 2 equates that 8 parallel-by-bit data are output as reg5[6:0]+reg4[7]
If comparator 3 equates that 8 parallel-by-bit data are output as reg5[5:0]+reg4[7:6]
If comparator 4 equates that 8 parallel-by-bit data are output as reg5[4:0]+reg4[7:5]
If comparator 5 equates that 8 parallel-by-bit data are output as reg5[3:0]+reg4[7:4]
If comparator 6 equates that 8 parallel-by-bit data are output as reg5[2:0]+reg4[7:3]
If comparator 7 equates that 8 parallel-by-bit data are output as reg5[1:0]+reg4[7:2]
If comparator 8 equates that 8 parallel-by-bit data are output as reg5[0]+reg4[7:1]
E, according to the SDH frame structure, determine the position of frame alignment pattern in the SDH frame structure.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101162958B (en) * | 2006-10-11 | 2012-04-18 | 中兴通讯股份有限公司 | Sampling method for positioning frame head signal in SDH transmission system |
| CN101605012B (en) * | 2009-07-02 | 2013-10-16 | 中兴通讯股份有限公司 | Method and device for realizing positioning of frame header of synchronous digital system |
| CN104935393B (en) * | 2015-06-02 | 2018-01-09 | 瑞斯康达科技发展股份有限公司 | A kind of frame synchornization method and device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5081654A (en) * | 1989-05-12 | 1992-01-14 | Alcatel Na Network Systems Corp. | Parallel bit detection circuit for detecting frame synchronization information imbedded within a serial bit stream and method for carrying out same |
| CN1214827C (en) * | 2001-02-08 | 2005-08-17 | 沈阳新松维尔康科技有限公司 | Distributed oxygen spplying equipment |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5081654A (en) * | 1989-05-12 | 1992-01-14 | Alcatel Na Network Systems Corp. | Parallel bit detection circuit for detecting frame synchronization information imbedded within a serial bit stream and method for carrying out same |
| CN1214827C (en) * | 2001-02-08 | 2005-08-17 | 沈阳新松维尔康科技有限公司 | Distributed oxygen spplying equipment |
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