CN112185836B - Load effect monitoring method and layout - Google Patents

Abstract

The application discloses a monitoring method and a layout of a load effect, wherein the method comprises the following steps: forming at least two types of device graphs and measuring graphs on a wafer through a photoetching process, wherein the characteristic sizes of the graphs of different types are different, and the characteristic size of the measuring graph is larger than that of the device graph; etching, etching the region of the wafer exposed by the device pattern to form a device groove, and etching the region of the wafer exposed by the measurement pattern to form a measurement groove; and measuring the depth of the measuring groove by using an atomic force microscope, and monitoring the load effect between different types of device grooves according to the depth of the measuring groove. This application obtains the degree of depth of measurationing the groove through atomic force microscope measurationing, and the depth through the measurationing groove of different grade type monitors the load effect between the device groove of different grade type, owing to need not carry out the section to the wafer, has solved among the correlation technique and has measurationed the time longer with the control load effect to the section sample through TEM, and the lower problem of monitoring efficiency.

Description

Monitoring method and layout of load effect

technical field

The present application relates to the technical field of semiconductor manufacturing, and in particular, to a method and layout for monitoring the channel load effect of a semiconductor device.

Background technique

In the etching process of semiconductor manufacturing, when the pattern to be etched is exposed to the reactive gas or solution, the etching rate of the pattern with a larger critical dimension (CD) is lower than that of the pattern with a smaller critical dimension, This is due to the fact that regions with larger critical dimensions are consumed to a greater extent than regions with smaller critical dimensions, resulting in lower concentrations of reactants, and the etch rate is proportional to the concentration of reactants, a phenomenon known as Loading effect

On a wafer with integrated semiconductor power devices, trench structures with different feature sizes (such as deep trench isolation (DTI) structures) are usually included. Due to the loading effect, the depths of the trench structures with different feature sizes are different. , when the influence of the load effect is large, and the depth difference of the trench structures with different feature sizes is too large, the breakdown voltage of the device will be lower, and the stability of the device will be reduced.

In view of this, in the related art, the wafer is usually sliced to obtain a sliced sample, and the sliced sample is measured by a transmission electron microscope (TEM) to obtain the depth of the trench structure with different feature sizes, so as to measure the depth of the groove structure with different feature sizes. The loading effect of the trench depth of the feature size is monitored.

However, the measurement time of sliced samples by TEM is long, and the monitoring efficiency is low; at the same time, real-time monitoring of the loading effect cannot be realized, and the monitoring timeliness is poor.

SUMMARY OF THE INVENTION

The present application provides a monitoring method and layout for a loading effect, which can solve the problems of relatively long time and low efficiency of monitoring the loading effect by TEM provided in the related art.

On the one hand, an embodiment of the present application provides a method for monitoring a load effect, including:

A device pattern and a measurement pattern are formed on the wafer by a photolithography process, the device pattern includes at least two types of device patterns, the measurement pattern includes at least two types of measurement patterns, and the different types of device patterns The feature sizes are different, and the feature sizes of different types of measurement patterns are different. For any one of the device patterns and the measurement patterns, the feature size of the measurement pattern is larger than the device pattern;

Etching is performed, and the area of the wafer exposed by the device pattern is etched to form a device trench, the device trench includes at least two types of device trenches, and the wafer is etched by the measurement pattern The exposed area is etched to form a measurement trench, the measurement trench includes at least two types of measurement trenches, different types of device trenches have different feature sizes, and different types of measurement trenches have different feature sizes different;

The depth of the measurement trenches is measured by an atomic force microscope, and the loading effect between different types of the device trenches is monitored according to the depth of the measurement trenches.

Optionally, the monitoring of the loading effect between the device trenches of different types according to the depth of the measurement trench includes:

Depending on the ratio of the depths of the different types of measurement trenches, the loading effect between the different types of device trenches is monitored.

Optionally, the device pattern includes a first type of device pattern and a second type of device pattern, and the measurement pattern includes a first type of measurement pattern and a second type of measurement pattern;

The device trench includes a first type of device trench and a second type of device trench, the measurement trench includes a first type of measurement trench and a second type of measurement trench, the first type of measurement trench A type of device trench is obtained by etching the first type of device trench, and the second type of device trench is obtained by etching the second type of device trench;

The monitoring of the loading effect between the different types of device trenches according to the ratio of the depths of the different types of measurement trenches includes:

calculating the ratio of the depths of the first type of measurement groove and the second type of measurement groove;

When the ratio is greater than a ratio threshold, it is determined that the loading effect between the device trenches of the first type and the device trenches of the second type does not meet manufacturing standards.

Optionally, the monitoring of the loading effect between the device trenches of different types according to the depth of the measurement trench includes:

Based on the difference in the depths of the different types of measurement trenches, the loading effect between the different types of device trenches is monitored.

Optionally, the device pattern includes a first type of device pattern and a second type of device pattern, and the measurement pattern includes a first type of measurement pattern and a second type of measurement pattern;

The device trench includes a first type of device trench and a second type of device trench, the measurement trench includes a first type of measurement trench and a second type of measurement trench, the first type of measurement trench A type of device trench is obtained by etching the first type of device trench, and the second type of device trench is obtained by etching the second type of device trench;

The monitoring of the loading effect between different types of device trenches according to the difference in the depths of the different types of measurement trenches includes:

calculating the difference between the depths of the measurement grooves of the first type and the measurement grooves of the second type;

When the difference is greater than a difference threshold, it is determined that the loading effect between the device trenches of the first type and the device trenches of the second type does not meet manufacturing standards.

Optionally, the device pattern is formed in a first area of the wafer, the measurement pattern is formed in a second area of the wafer, and the first area and the second area do not overlap.

Optionally, the second region includes at least two sub-regions, the feature sizes of the measurement patterns formed in each of the sub-regions are the same, and the feature sizes of the measurement patterns are different between different sub-regions.

Optionally, the measurement pattern includes a first type of measurement pattern and a second type of measurement pattern, and the feature size of the first type of measurement pattern is 13 micrometers (μm) to 20 micrometers.

Optionally, the feature size of the second type of measurement pattern is 4 microns to 12 microns.

On the other hand, an embodiment of the present application provides a layout of a semiconductor device, including:

A device pattern, the device pattern includes at least two types of device patterns, and the feature sizes of different types of device patterns are different, and in the preparation process of the semiconductor device, the device pattern is transferred to the wafer by a photolithography process , the region of the wafer exposed by the device pattern is etched to form a device trench, and the device trench includes at least two types of device trenches;

A measurement pattern, the measurement pattern includes at least two types of measurement patterns, each type of measurement pattern has a different feature size, and in the manufacturing process of the semiconductor device, the measurement pattern is processed by a photolithography process is transferred to the wafer, and the area of the wafer exposed by the measurement pattern is etched to form measurement grooves, the measurement grooves include at least two types of measurement grooves, through An atomic force microscope measures the depth of the measurement trenches and monitors loading effects between different types of the device trenches according to the depth of the measurement trenches;

Wherein, for any one of the device pattern and the measurement pattern, the feature size of the measurement pattern is larger than that of the device pattern.

Optionally, the measurement pattern is a rectangle.

Optionally, the device pattern is arranged in a first area of the layout, the measurement pattern is arranged in a second area of the layout, and the first area and the second area do not overlap.

Optionally, the second region includes at least two sub-regions, the feature sizes of the measurement patterns formed in each of the sub-regions are the same, and the feature sizes of the measurement patterns are different between different sub-regions.

Optionally, the measurement pattern includes a first type of measurement pattern and a second type of measurement pattern, and the feature size of the first type of measurement pattern is 13 μm to 20 μm.

Optionally, the feature size of the second type of measurement pattern is 4 microns to 12 microns.

The technical solution of the present application includes at least the following advantages:

When a device pattern is formed on a wafer by a photolithography process, a measurement pattern with a feature size larger than that of the device pattern is formed. After etching, different types of device trenches and different types of measurement trenches are respectively formed, which are measured by atomic force microscopy. The depth of the measurement groove is obtained, and the load effect between the grooves of different types of devices is monitored by measuring the depth of the groove. Since the measurement of the groove by the atomic force microscope does not require slicing the wafer, it solves the problem of the related technology. TEM takes a long time to measure sliced samples, and the monitoring efficiency is low; at the same time, since the loading effect between different types of device grooves is monitored through the measurement grooves on the same wafer, the monitoring of Real-time monitoring of load effects.

Description of drawings

In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the accompanying drawings that need to be used in the description of the specific embodiments or the prior art will be briefly introduced below. The drawings are some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without any creative effort.

FIG. 1 is a flowchart of a method for monitoring a load effect provided by an exemplary embodiment of the present application;

2 is a schematic cross-sectional view of forming a device pattern and a measurement pattern on a wafer provided by an exemplary embodiment of the present application;

3 is a schematic top view of a device pattern and a measurement pattern formed on a wafer provided by an exemplary embodiment of the present application;

4 is a schematic top view of a device pattern and a measurement pattern formed on a wafer provided by another exemplary embodiment of the present application;

5 is a schematic cross-sectional view of a device trench and a measurement trench formed after etching provided by an exemplary embodiment of the present application;

6 is a schematic diagram of a layout of a semiconductor device provided by an exemplary embodiment of the present application;

FIG. 7 is a schematic diagram of a layout of a semiconductor device provided by another exemplary embodiment of the present application.

Detailed ways

The technical solutions in the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

In the description of this application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the indicated device or element must have a specific orientation or a specific orientation. construction and operation, and therefore should not be construed as limitations on this application. Furthermore, the terms "first", "second", and "third" are used for descriptive purposes only and should not be construed to indicate or imply relative importance.

In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection connection, or integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal connection of two components, which can be a wireless connection or a wired connection connect. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood in specific situations.

In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as there is no conflict with each other.

Referring to FIG. 1 , it shows a flowchart of a method for monitoring a load effect provided by an exemplary embodiment of the present application. The method can be applied to monitor the loading effect of the depth of the trench formed by etching during the fabrication of the semiconductor device, and the method includes:

Step 101, forming a device pattern and a measurement pattern on the wafer by a photolithography process, the device pattern includes at least two types of device patterns, the measurement pattern includes at least two types of measurement patterns, and the features of different types of device patterns Different sizes, different types of measurement patterns have different feature sizes. For any device pattern and measurement pattern, the feature size of the measurement pattern is larger than the device pattern.

Referring to FIG. 2 , it shows a schematic cross-sectional view of forming a device pattern and a measurement pattern on a wafer provided by an exemplary embodiment of the present application. It should be noted that, in FIG. 2 , the device pattern and the measurement pattern are formed on the substrate 210 as an example, and the device pattern and the measurement pattern can also be formed on a dielectric layer, a metal layer or other thin film layers.

As shown in FIG. 2, a device pattern and a measurement pattern are formed on the substrate 210 through a photolithography process, wherein the device pattern includes at least two types of device patterns (in FIG. 2, the first type of device pattern 221 and the second type of device pattern The type of device pattern 222 is exemplified, the feature size of the first type of device pattern 221 is different from that of the second type of device pattern 222), and the measurement pattern includes at least two types of measurement patterns (in FIG. 2 ) Taking the measurement pattern 231 of the first type and the measurement pattern 232 of the second type as an example, the feature size of the measurement pattern 231 of the first type is different from that of the measurement pattern 232 of the second type).

In the embodiment of the present application, the type of the graphics is based on the feature size as the classification standard, the feature size of different types of graphics is different, and the feature size of the same type of graphics is the same. For any device pattern and measurement pattern, the feature size of the measurement pattern is larger than that of the device pattern. For example, in FIG. 2, the feature size of the measurement pattern 231 of the first type is larger than the feature size of the device pattern 222 of the second type. The feature size of one type of measurement pattern 231 is larger than the feature size of the first type of device pattern 221, the feature size of the second type of measurement pattern 232 is larger than the feature size of the second type of device pattern 222, the second type of The feature size of the measurement pattern 232 is larger than the feature size of the device pattern 221 of the first type.

Referring to FIG. 3, it shows a schematic top view of a device pattern and a measurement pattern formed on a wafer provided by an exemplary embodiment of the present application; with reference to FIG. Schematic top view of the device pattern and measurement pattern formed on the wafer. As shown in FIGS. 3 and 4 , the device pattern is formed on the first area 201 of the wafer 100 , the measurement pattern is formed on the second area 202 of the wafer 100 , and the first area 201 and the second area 202 do not overlap.

As shown in FIG. 3 , which shows a distribution diagram of a measurement pattern, in this distribution, the second area 202 includes at least two sub-areas (two sub-areas 2021 and 2022 are exemplified in FIG. 3 ) , the feature sizes of the measurement patterns formed in each sub-region are the same, and the feature sizes of the measurement patterns formed in each sub-region are different. For example, in FIG. 3, the first type of measurement pattern 231 is formed in the sub-area 2021, the second type of measurement pattern 232 is formed in the sub-area 2022, and the first type of measurement pattern 231 in the sub-area 2021 is formed. The feature size is the same, the feature size of the second type of measurement pattern 232 in the sub-region 2022 is the same, the features of the first type of measurement pattern 231 in the sub-region 2021 and the feature of the second type of measurement pattern 232 in the sub-region 2022 Different sizes.

As shown in FIG. 4, it shows a distribution diagram of another measurement pattern, in this distribution, measurement patterns of different feature sizes (in FIG. 4, the first type of measurement pattern 231 and the second type of measurement pattern The measurement patterns 232 of (for illustrative purposes) are distributed in the second area 202 .

Optionally, in the embodiment of the present application, the feature size of the first type of measurement pattern 231 is 4 micrometers to 12 micrometers (for example, it may be 8 micrometers); optionally, the features of the second type of measurement pattern 232 The size is 13 microns to 20 microns (for example, it may be 16 microns).

Optionally, in this embodiment of the present application, the feature size of the measurement pattern may be the width of the measurement pattern.

In step 102, etching is performed, and the area of the wafer exposed by the device pattern is etched to form a device trench, the device trench includes at least two types of device trenches, and the area of the wafer exposed by the measurement pattern is etched to form The measurement trenches include at least two types of measurement trenches. Different types of device trenches have different feature sizes, and different types of measurement trenches have different feature sizes.

Referring to FIG. 5 , a schematic cross-sectional view of the device trench and the measurement trench formed after etching is shown. As shown in FIG. 5 , a first device trench 241 is formed under the first type device pattern 221 , a second device trench 242 is formed under the second type device pattern 222 , and a first device trench 242 is formed under the first type measurement pattern 231 The measurement trenches 251 and the second measurement trenches 252 are formed under the measurement pattern 232 of the second type. Due to the loading effect, the depth h1 of the first device trench 241 , the depth h2 of the second device trench 242 , the depth h3 of the first measurement trench 251 , and the depth h4 of the second measurement trench 252 are different.

In step 103, the depth of the measurement trench is measured by an atomic force microscope, and the loading effect between the trenches of different types of devices is monitored according to the depth of the measurement trench.

Since it is difficult for atomic force microscopes to measure trenches with smaller widths, it is difficult to directly measure device trenches (eg, the first device trench 241 and the second device trench 242 ). The indirect measurement method of measuring the measurement trench 251 and the second measurement trench 252) monitors the loading effect between different types of device trenches.

Optionally, in step 103, "monitoring the loading effect between different types of device trenches according to the depths of the measurement trenches" includes but is not limited to: monitoring different types of device trenches according to the ratio of the depths of the different types of measurement trenches. the loading effect between the device trenches.

For example, monitoring can be performed by: calculating the ratio (h3/h4) of the depths of the first type of measurement grooves 251 and the second type of measurement grooves 252; when the ratio is greater than a ratio threshold, the first type is determined The loading effect between the device trenches 241 and the second type of device trenches 242 does not meet the manufacturing standards.

Optionally, in step 103, "monitoring the loading effect between different types of device trenches according to the depths of the measurement trenches" includes, but is not limited to, monitoring different Types of loading effects between device trenches.

For example, monitoring can be performed by: calculating the difference (h3-h4) of the depths of the first type of measurement groove 251 and the second type of measurement groove 252; when the difference is greater than the difference threshold, determine The loading effect between the device trenches 241 of the first type and the device trenches 242 of the second type does not meet the manufacturing standards.

Optionally, the semiconductor device in this embodiment of the present application is a power metal-oxide-semiconductor (MOS) device.

To sum up, in the embodiments of the present application, when a device pattern is formed on a wafer by a photolithography process, a measurement pattern with a feature size larger than the device pattern is formed, and after etching, different types of device trenches are formed, and different types of device trenches are formed. The measurement trench is measured by atomic force microscope to obtain the depth of the measurement trench, and the load effect between the trenches of different types of devices is monitored by measuring the depth of the trench. The wafer is sliced, which solves the problem that the measurement time of the sliced sample by TEM in the related art is relatively long and the monitoring efficiency is low. The load effect between them is monitored, and the real-time monitoring of the load effect is realized.

Referring to FIG. 6 , a schematic diagram of a layout of a semiconductor device provided by an exemplary embodiment of the present application is shown. The layout of the semiconductor device can be applied to the fabrication process in any of the above-mentioned embodiments, including:

There are at least two types of device patterns (the first type of device pattern 621 and the second type of device pattern 622 are exemplified in FIG. 6 ), and the feature sizes of each type of device pattern are different. During the preparation of the device, the device pattern is transferred to the wafer through a photolithography process, and the area of the wafer exposed by the device pattern is etched to form a device trench, and the formed device trench includes at least two types of trenches. .

At least two types of measurement patterns (the first type of measurement pattern 631 and the second type of measurement pattern 632 are exemplified in FIG. 6 ), each type of measurement pattern has a different feature size, in this In the preparation process of the semiconductor device corresponding to the layout, the measurement pattern is transferred to the wafer through a photolithography process, and the area of the wafer exposed by the measurement pattern is etched to form a measurement groove, and the formed measurement groove At least two types of measurement trenches are included, the depth of the measurement trenches is measured by an atomic force microscope and the loading effect between different types of device trenches is monitored according to the depth of the measurement trenches.

In the embodiment of the present application, the type of the graphics is based on the feature size as the classification standard, the feature size of different types of graphics is different, and the feature size of the same type of graphics is the same. Wherein, for any device pattern and the measurement pattern, the feature size of the measurement pattern is larger than that of the device pattern. For example, in FIG. 6 , the feature size of the first type of measurement pattern 631 is larger than that of the second type of device pattern 622 , and the feature size of the first type of measurement pattern 631 is larger than that of the first type of device pattern 621 The feature size of the second type of measurement pattern 632 is larger than that of the second type of device pattern 622 , and the feature size of the second type of measurement pattern 632 is larger than that of the first type of device pattern 621 .

Optionally, referring to FIG. 6 , the device pattern is arranged in the first area 601 of the layout, the measurement pattern is arranged in the second area 602 of the layout, and the first area 601 and the second area 602 do not overlap.

Referring to FIG. 7 , it shows a schematic diagram of a layout of a semiconductor device provided by another embodiment of the present application. The difference between the embodiment in FIG. 7 and the embodiment in FIG. 6 is that the second region 602 includes at least two sub-regions (the first sub-region 6021 and the second sub-region 6022 are exemplified in FIG. 7 ), and the The feature sizes of the measurement patterns are the same, and the feature sizes of the measurement patterns are different between different sub-regions. For example, in FIG. 7, the first type of measurement pattern 631 is formed in the sub-area 6021, the second type of measurement pattern 632 is formed in the sub-area 6022, and the first type of measurement pattern 631 in the sub-area 6021 is formed. The feature size is the same, the feature size of the second type of measurement pattern 632 in the sub-region 6022 is the same, the features of the first type of measurement pattern 631 in the sub-region 6021 and the feature of the second type of measurement pattern 632 in the sub-region 6022 Different sizes.

Optionally, in the embodiment of the present application, the feature size of the first type of measurement pattern 631 is 13 microns to 20 microns; optionally, the feature size of the second type of measurement pattern 632 is 4 microns to 12 microns.

Optionally, in the embodiment of the present application, the measurement pattern is a rectangle; optionally, the wide value range of the measurement pattern is 40 micrometers to 60 micrometers (for example, it may be 50 micrometers); The length of the pattern ranges from 70 microns to 100 microns (for example, it may be 80 microns).

Optionally, in this embodiment of the present application, the feature size of the measurement pattern may be the width of the measurement pattern.

Optionally, in the embodiment of the present application, the semiconductor device to which the layout of the semiconductor device is applied is a power MOS device.

To sum up, in the embodiment of the present application, by using a layout including a device pattern and a measurement pattern to perform photolithography, when forming a device pattern on a wafer, a measurement pattern with a feature size larger than the device pattern is formed, and after etching, respectively The device trench and the measurement trench are formed, and the depth of the measurement trench is measured by the atomic force microscope, and the depth of the device trench is monitored by measuring the depth of the trench. The slicing method solves the problem that the measurement time of the sliced sample by TEM is relatively long and the monitoring efficiency is low in the related art. Real-time monitoring of device trenches.

Obviously, the above-mentioned embodiments are only examples for clear description, and are not intended to limit the implementation manner. For those of ordinary skill in the art, changes or modifications in other different forms can also be made on the basis of the above description. There is no need and cannot be exhaustive of all implementations here. However, the obvious changes or changes derived from this are still within the scope of protection created by the present application.

Claims (15)

1. a monitoring method of load effect, is characterized in that, comprises: A device pattern and a measurement pattern are formed on the wafer by a photolithography process, the device pattern includes at least two types of device patterns, the measurement pattern includes at least two types of measurement patterns, and the different types of device patterns The feature sizes are different, and the feature sizes of different types of measurement patterns are different. For any one of the device patterns and the measurement patterns, the feature size of the measurement pattern is larger than the device pattern; Etching is performed, and the area of the wafer exposed by the device pattern is etched to form a device trench, the device trench includes at least two types of device trenches, and the wafer is etched by the measurement pattern The exposed area is etched to form a measurement trench, the measurement trench includes at least two types of measurement trenches, different types of device trenches have different feature sizes, and different types of measurement trenches have different feature sizes different; The depth of the measurement trenches is measured by an atomic force microscope, and the loading effect between different types of the device trenches is monitored according to the depth of the measurement trenches. 2 . The method according to claim 1 , wherein the monitoring of the loading effect between different types of the device trenches according to the depth of the measurement trenches comprises: 2 . Depending on the ratio of the depths of the different types of measurement trenches, the loading effect between the different types of device trenches is monitored. 3. The method according to claim 2, wherein the device pattern comprises a first type of device pattern and a second type of device pattern, and the measurement pattern comprises a first type of measurement pattern and a second type of device pattern type of measurement pattern; The device trench includes a first type of device trench and a second type of device trench, the measurement trench includes a first type of measurement trench and a second type of measurement trench, the first type of measurement trench A type of device trench is obtained by etching the first type of device trench, and the second type of device trench is obtained by etching the second type of device trench; The monitoring of the loading effect between the different types of device trenches according to the ratio of the depths of the different types of measurement trenches includes: calculating the ratio of the depths of the first type of measurement groove and the second type of measurement groove; When the ratio is greater than a ratio threshold, it is determined that the loading effect between the device trenches of the first type and the device trenches of the second type does not meet manufacturing standards. 4 . The method of claim 1 , wherein the monitoring of the loading effect between different types of the device trenches according to the depth of the measurement trenches comprises: 5 . The loading effect between different types of device trenches is monitored according to the difference in the depths of the different types of measurement trenches. 5. The method according to claim 2, wherein the device pattern comprises a first type of device pattern and a second type of device pattern, and the measurement pattern comprises a first type of measurement pattern and a second type of device pattern type of measurement pattern; The device trench includes a first type of device trench and a second type of device trench, the measurement trench includes a first type of measurement trench and a second type of measurement trench, the first type of measurement trench A type of device trench is obtained by etching the first type of device trench, and the second type of device trench is obtained by etching the second type of device trench; The monitoring of the loading effect between different types of device trenches according to the difference in the depths of the different types of measurement trenches includes: calculating the difference between the depths of the measurement grooves of the first type and the measurement grooves of the second type; When the difference is greater than a difference threshold, it is determined that the loading effect between the device trenches of the first type and the device trenches of the second type does not meet manufacturing standards. 6. The method according to any one of claims 1 to 5, wherein the device pattern is formed in a first area of the wafer, and the measurement pattern is formed in a second area of the wafer, The first area and the second area do not overlap. 7 . The method according to claim 6 , wherein the second region comprises at least two sub-regions, and the feature sizes of the measurement patterns formed in each of the sub-regions are the same, and between different sub-regions. 8 . The feature sizes of the measurement patterns are different. 8. The method according to claim 7, wherein the measurement pattern comprises a first type of measurement pattern and a second type of measurement pattern, and the characteristic size of the first type of measurement pattern is 13 microns to 20 microns. 9 . The method of claim 8 , wherein the feature size of the second type of measurement pattern is 4 μm to 12 μm. 10 . 10. A layout of a semiconductor device, comprising: A device pattern, the device pattern comprising at least two types of device patterns, each type of device pattern having a different feature size, the device pattern being transferred to a wafer by a photolithography process during the fabrication of the semiconductor device above, the area of the wafer exposed by the device pattern is etched to form a device trench, and the device trench includes at least two types of device trenches; A measurement pattern, the measurement pattern includes at least two types of measurement patterns, each type of measurement pattern has a different feature size, and in the manufacturing process of the semiconductor device, the measurement pattern is processed by a photolithography process is transferred to the wafer, and the area of the wafer exposed by the measurement pattern is etched to form measurement grooves, the measurement grooves include at least two types of measurement grooves, through An atomic force microscope measures the depth of the measurement trenches and monitors loading effects between different types of the device trenches according to the depth of the measurement trenches; Wherein, for any one of the device pattern and the measurement pattern, the feature size of the measurement pattern is larger than that of the device pattern. 11. The layout of claim 10, wherein the measurement pattern is a rectangle. 12. The layout according to claim 11, wherein the device pattern is arranged in a first area of the layout, the measurement pattern is arranged in a second area of the layout, the first area and the The second regions do not overlap. 13 . The layout according to claim 12 , wherein the second region comprises at least two sub-regions, the feature sizes of the measurement patterns formed in each of the sub-regions are the same, and between different sub-regions. 14 . The feature sizes of the measurement patterns are different. 14. The layout according to claim 13, wherein the measurement pattern comprises a first type of measurement pattern and a second type of measurement pattern, and the characteristic size of the first type of measurement pattern is 13 microns to 20 microns. 15 . The layout of claim 14 , wherein the feature size of the second type of measurement pattern is 4 μm to 12 μm. 16 .

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