CN112185834B - Method for monitoring layout of semiconductor device and depth of device groove - Google Patents

Abstract

The application discloses a method for monitoring the layout of a semiconductor device and the depth of a device groove, wherein the layout comprises the following steps: the device pattern is used for being transferred to a wafer through a photoetching process in the preparation process of the semiconductor device, and the region of the wafer exposed by the device pattern is etched to form a device groove; the measuring graph is used for being transferred to a wafer through a photoetching process in the preparation process of the semiconductor device, the area of the wafer exposed by the measuring graph is etched to form a measuring groove, and the depth of the measuring groove is measured through an atomic force microscope to monitor the depth of the device groove; wherein a ratio of the feature size of the measurement pattern to the feature size of the device pattern ranges from 20 to 60. The present application reduces loading effects by reducing the difference in feature sizes of metrology patterns and device patterns.

Description

Layout of semiconductor device and monitoring method of device trench depth

technical field

The present application relates to the technical field of semiconductor manufacturing, and in particular to a method for monitoring the layout of a semiconductor device and the depth of a trench in the device.

Background technique

In the fabrication process of semiconductor devices, especially power metal-oxide-semiconductor (MOS) devices, it is necessary to form trenches (such as trenches of deep trench isolation (DTI) structures) and A measurement groove that measures the depth of the groove.

In the preparation process of the MOS device provided by the related art, the feature size of the trench and the measurement trench differ greatly, usually by more than one hundred times or several hundred times. However, due to the loading effect, there is a certain probability that the feature size and the large difference will lead to a poor topography of the measurement groove (usually the surface of the measurement groove is rough, similar to the shape of grass), and the measurement groove has a poor topography. The trenches are difficult to measure for trench depth, requiring rework and reducing manufacturing efficiency.

SUMMARY OF THE INVENTION

The present application provides a layout of a semiconductor device, and the application of the layout to fabricate a semiconductor device can solve the problem of the measurement method of the trench depth provided in the related art, because there is a high probability that the measurement of the trench topography is poor. This leads to the problem of lower manufacturing efficiency.

On the one hand, an embodiment of the present application provides a layout of a semiconductor device, characterized in that it includes:

A device pattern, the device pattern is used to be transferred to a wafer by a photolithography process during the preparation process of the semiconductor device, and the region of the wafer exposed by the device pattern is etched to form a device trench ;

A measurement pattern, which is used to be transferred to the wafer by a photolithography process during the fabrication of the semiconductor device, and the wafer is engraved in the area exposed by the measurement pattern etching to form a measurement trench, and the depth of the measurement trench is measured by an atomic force microscope to monitor the depth of the device trench;

The value of the ratio of the feature size of the measurement pattern to the feature size of the device pattern ranges from 20 to 60.

Optionally, the measurement pattern is a rectangle.

Optionally, the feature size of the measurement pattern is 5 micrometers (μm) to 20 micrometers.

Optionally, the semiconductor device is a power MOS device.

On the other hand, an embodiment of the present application provides a method for monitoring the trench depth of a device, including:

A device pattern and a measurement pattern are formed on the wafer by a photolithography process, and the ratio of the feature size of the measurement pattern to the feature size of the device pattern ranges from 20 to 60;

Etching is performed, the area of the wafer exposed by the device pattern is etched to form the groove of the device, and the area of the wafer exposed by the measurement pattern is etched to form the measurement groove;

The depth of the measurement trench is measured by atomic force microscopy (AFM), and the depth of the device trench is monitored according to the depth of the measurement trench.

Optionally, the measurement pattern is a rectangle.

Optionally, the feature size of the measurement pattern is 5 microns to 20 microns.

Optionally, the device is a power MOS device.

The technical solution of the present application includes at least the following advantages:

By using the layout including the device pattern and the measurement pattern to perform photolithography, the device pattern is formed on the wafer and the measurement pattern is formed simultaneously. After etching, the device trench and the measurement trench are respectively formed, which are measured by atomic force microscopy. The depth of the trench is measured, and the depth of the device trench is monitored based on the depth of the measurement trench. Since the difference between the feature size of the measurement pattern and the feature size of the device pattern is small (the difference is a multiple of 20 to 60), the During the etching process, the reactant supply, by-product generation, deposition, and reaction gas extraction behaviors of the measurement trench and the device trench are closer, which reduces the influence of the load effect and solves the problem of formation caused by the load effect in the related art. The problem of poor topography of the measurement trench improves the manufacturing efficiency.

Description of drawings

In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the accompanying drawings that need to be used in the description of the specific embodiments or the prior art will be briefly introduced below. The drawings are some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without any creative effort.

FIG. 1 is a flowchart of a method for monitoring trench depth provided by an exemplary embodiment of the present application;

2 is a schematic top view of a device pattern and a measurement pattern formed on a wafer provided by an exemplary embodiment of the present application;

3 is a schematic top view of a measurement pattern formed on a wafer provided by an exemplary embodiment of the present application;

4 is a schematic top view of a measurement pattern formed on a wafer provided by an exemplary embodiment of the present application;

5 is a schematic top view of a measurement pattern formed on a wafer provided by an exemplary embodiment of the present application;

6 is a schematic top view of a measurement pattern formed on a wafer provided by an exemplary embodiment of the present application;

FIG. 7 is a schematic diagram of a layout of a semiconductor device provided by an exemplary embodiment of the present application.

Detailed ways

The technical solutions in the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

In the description of this application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the indicated device or element must have a specific orientation or a specific orientation. construction and operation, and therefore should not be construed as limitations on this application. Furthermore, the terms "first", "second", and "third" are used for descriptive purposes only and should not be construed to indicate or imply relative importance.

In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection connection, or integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal connection of two components, which can be a wireless connection or a wired connection connect. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood in specific situations.

In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as there is no conflict with each other.

Referring to FIG. 1 , a flowchart of a trench depth monitoring method provided by an exemplary embodiment of the present application is shown. The method can be applied to monitor the depth of the trench formed by etching during the preparation of the semiconductor device, and the method includes:

In step 101, a device pattern and a measurement pattern are formed on the wafer by a photolithography process, and the ratio of the feature size of the measurement pattern to the feature size of the device pattern ranges from 20 to 60.

Referring to FIG. 2 , it shows a schematic top view of a device pattern and a measurement pattern formed on a wafer provided by an exemplary embodiment of the present application; with reference to FIGS. 3 to 6 , it shows different implementations in the present application. A schematic top view of the measurement pattern in the example.

As shown in FIG. 2 , the device pattern 210 is formed on the first area 201 of the wafer 100 , the measurement pattern 220 is formed on the second area 202 of the wafer 100 , and the first area 201 and the second area 202 do not overlap. The ratio of the feature size of the measurement pattern 220 to the feature size of the device pattern 210 ranges from 20 to 60. Optionally, the second area 202 may be an area corresponding to a measurement pattern in the related art.

In the following, the size of the second region 202 is 50 μm×80 μm for exemplary illustration. In FIG. 3, the feature size of the measurement pattern 220 is 8 microns; in FIG. 4, the feature size of the measurement pattern 220 is 10 microns; in FIG. 5, the feature size of the measurement pattern 220 is 16 microns; The feature size of the measurement pattern 220 is 20 microns.

Optionally, in the embodiment of the present application, the measurement pattern is a rectangle; optionally, the value range of the feature size of the measurement pattern is 8 micrometers to 20 micrometers.

Optionally, in the embodiment of the present application, the second area where the measurement pattern is located is a rectangle; is 50 microns in Figures 3 to 6); optionally, the length of the second region where the measurement pattern is located ranges from 70 microns to 100 microns (for example, it can be 80 microns in Figures 3 to 6). microns).

In step 102, etching is performed, the region of the wafer exposed by the device pattern is etched to form a device trench, and the region of the wafer exposed by the measurement pattern is etched to form a measurement trench.

The applicant has found that setting the value range of the ratio of the feature size of the measurement pattern 220 to the feature size of the device pattern 210 is 20 to 60, so that the measurement trench and the device trench can be supplied with reactants, The by-product generation, deposition and reaction gas extraction behaviors are closer, reducing the influence of the loading effect, so that the morphology of the formed measurement trench is better.

Step 103 , measure the depth of the measurement trench by an atomic force microscope, and monitor the depth of the device trench according to the depth of the measurement trench.

Optionally, the semiconductor device in this embodiment of the present application is a power MOS device.

To sum up, in the embodiment of the present application, by using a layout including a device pattern and a measurement pattern to perform photolithography, the device pattern is formed on the wafer while the measurement pattern is formed, and the device groove and the device trench are formed respectively after etching. To measure the trench, the depth of the trench is measured by atomic force microscope, and the depth of the trench of the device is monitored based on the depth of the trench, because the difference between the feature size of the measurement pattern and the feature size of the device pattern is small ( The difference multiples are 20 to 60), so that the reactant supply, by-product generation, deposition and reaction gas extraction behavior of the measurement trench and the device trench during the etching process are closer, reducing the influence of the loading effect, The problem of the poor shape of the measurement trench formed due to the load effect in the related art is solved, and the manufacturing efficiency is improved.

Referring to FIG. 7 , a schematic diagram of a layout of a semiconductor device provided by an exemplary embodiment of the present application is shown. The layout of the semiconductor device can be applied to any of the above method embodiments, and includes:

The device pattern 710 is used to be transferred onto a wafer by a photolithography process during the fabrication of a semiconductor device, and the region of the wafer exposed by the device pattern 710 is etched to form device trenches.

The measurement pattern 720 is used to be transferred to the wafer through a photolithography process during the preparation of the semiconductor device, and the area of the wafer exposed by the measurement pattern 720 is etched to form a measurement groove. Microscope measurements measure the depth of the trenches to monitor the depth of the device trenches.

The ratio of the feature size of the measurement pattern 720 to the feature size of the device pattern 710 ranges from 20 to 60.

Optionally, the measurement pattern 720 is a rectangle; optionally, the feature size of the measurement pattern 720 is 8 micrometers to 20 micrometers.

Optionally, the semiconductor device is a power MOS device.

Obviously, the above-mentioned embodiments are only examples for clear description, and are not intended to limit the implementation manner. For those of ordinary skill in the art, changes or modifications in other different forms can also be made on the basis of the above description. There is no need and cannot be exhaustive of all implementations here. And the obvious changes or changes derived from this are still within the scope of protection created by the present application.

Claims (8)

1. A layout of a semiconductor device, comprising:

the device pattern is used for being transferred to a wafer through a photoetching process in the preparation process of the semiconductor device, and the region of the wafer exposed by the device pattern is etched to form a device groove;

the measuring graph is used for being transferred onto the wafer through a photoetching process in the preparation process of the semiconductor device, the area of the wafer exposed by the measuring graph is etched to form a measuring groove, and the depth of the measuring groove is measured through an atomic force microscope to monitor the depth of the device groove;

wherein a ratio of the feature size of the metrology pattern to the feature size of the device pattern ranges from 20 to 60.

2. The layout of claim 1, wherein the metrology pattern is rectangular.

3. The layout of claim 2, wherein the feature size of the metrology pattern is from 5 microns to 20 microns.

4. A layout according to any one of claims 1 to 3, wherein said semiconductor device is a power device.

5. A method of monitoring device trench depth, comprising:

forming a device graph and a measurement graph on a wafer through a photoetching process, wherein the value range of the ratio of the characteristic dimension of the measurement graph to the characteristic dimension of the device graph is 20-60;

etching is carried out, the region of the wafer exposed by the device pattern is etched to form a groove of the device, and the region of the wafer exposed by the measurement pattern is etched to form a measurement groove;

and measuring the depth of the measuring groove through an atomic force microscope, and monitoring the depth of the device groove according to the depth of the measuring groove.

6. The method of claim 5, wherein the metrology pattern is rectangular.

7. The method of claim 6, wherein the feature size of the metrology pattern is from 5 microns to 20 microns.

8. The method of any of claims 5 to 7, wherein the device is a power MOS device.

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