CN112164718A - Split gate device with control gate protection layer and method of manufacturing the same - Google Patents
Split gate device with control gate protection layer and method of manufacturing the same Download PDFInfo
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- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
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- H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
- H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
- H10D30/0295—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the source electrodes
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- H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
- H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
- H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
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- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
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- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
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Abstract
The invention provides a separation gate device with a control gate protective layer and a manufacturing method thereof, wherein the separation gate device comprises a first conductive type substrate, a first conductive type drift region, a second conductive type well region, a heavily doped first conductive type region, a heavily doped second conductive type region, a first dielectric oxide layer, a second dielectric oxide layer, a third dielectric oxide layer, a fourth dielectric oxide layer, a fifth dielectric oxide layer, a control gate polycrystalline electrode, a separation gate polycrystalline electrode and a source electrode metal contact; the second conductive type region is positioned below the heavily doped second conductive type region and serves as a control gate protective layer, and when the second conductive type region is in an off state and is voltage-resistant state, electric field lines originally pointing to the control gate are transferred to ionized negative charges of the second conductive type region, so that the electric field peak value of the control gate close to the drift region is successfully reduced, and the possible premature breakdown at the position is eliminated.
Description
Technical Field
The invention belongs to the technical field of semiconductor process manufacturing, and particularly relates to a split gate device with a control gate protective layer.
Background
The power device is widely applied to various fields such as mobile communication, automotive electronics, mobile terminals and the like due to the superior characteristics of the power device, and the groove-type vertical channel VDMOS is one of the most widely applied power devices, and the improvement of the structure of the groove-type vertical channel VDMOS is continuous. The Split-Gate VDMOS device (Split-Gate VDMOS) has the advantages that the Split Gate electrode plays a role in auxiliary depletion of the longitudinal field plate, so that the doping concentration of a drift region is improved, the on-resistance of the device is reduced, meanwhile, the capacitance between the Gate and the drain is shielded, and excellent switching characteristics are brought, so that the Split-Gate VDMOS device is widely concerned. In a traditional split gate device, the too short control gate length easily causes channel breaking and on-resistance increase, when the control gate length is longer, electric field lines pointing to the control gate will cause the peak value of the electric field of a silicon layer close to the control gate, which may cause early breakdown and even gate oxide breakdown at the corner of the control gate, and the gate oxide layer is thinner and the doping concentration of a drift region is increased, so that the gate oxide layer is more obvious.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides the separation gate device with the control gate protective layer, which reduces electric field lines pointing to the control gate when the device is in an off state and is resistant to voltage, reduces the electric field of a silicon layer close to the gate, eliminates the premature breakdown, and has the function of reducing the surface field of a drift region.
In order to achieve the purpose, the technical scheme of the invention is as follows:
heavily doped first conductive type substrate 11, first conductive type drift region 12, first dielectric oxide layer 31, split gate polycrystalline electrode 41, second dielectric oxide layer 32, third dielectric oxide layer 33, control gate polycrystalline electrode 42, fourth dielectric oxide layer 34, second conductive type well region 21, heavily doped first conductive type region 13, fifth dielectric oxide layer 35, second conductive type region 22, heavily doped second conductive type region 23, and source metal contact 51;
the first conductive type drift region 12 is located above the heavily doped first conductive type substrate 11, the trench structure composed of the first dielectric oxide layer 31, the second dielectric oxide layer 32, the third dielectric oxide layer 33, the fourth dielectric oxide layer 34, the control gate polycrystalline electrode 41 and the separation gate polycrystalline electrode 42 is located on two sides of the first conductive type drift region 12, the fifth dielectric oxide layer 35 and the heavily doped first conductive type region 13 are located on the left and right sides of the source metal contact 51 on the surface of the device, the heavily doped second conductive type region 23 is located below the source metal contact 51 in the second conductive type well region 21 and is in short connection with the heavily doped first conductive type region 13, and the second conductive type region 22 is located below the heavily doped second conductive type region 23 and is connected with the second conductive type well region 21.
The second conductive type region 22 is located below the heavily doped second conductive type region 23 and connected to the second conductive type well region 21 as a control gate protection layer, which functions to reduce the peak value of the electric field at the corner of the control gate.
Preferably, the heavily doped second conductive type region 23 is connected to the second conductive type well region 21, and the heavily doped second conductive type region 23 is connected to or disconnected from the second conductive type region 22.
Preferably, the second conductivity type region 22 is obtained by one or more implantations.
Preferably, the source metal contact 51 further extends to a position within the second conductivity type well region 21 close to the first conductivity type drift region 12 or within the first conductivity type drift region 12.
Preferably, the lower boundary of the second conductive type region 22 is higher or lower than the lower edge of the control gate poly electrode 41, or continuously extends to any position in the drift region.
Preferably, the semiconductor material used is Si or SiC material, and the semiconductor device to which the same control gate protective layer structure is applied is a trench gate VDMOS.
Preferably, the first conductivity type is N-type, and the second conductivity type is P-type; or the first conductive type is P type, and the second conductive type is N type.
The invention also provides a manufacturing method of the split gate device with the control gate protective layer, which comprises the following steps:
step 1: obtaining a drift region on a substrate in an epitaxial or injection push junction mode;
step 2: etching the drift region by the deep groove and carrying out thermal oxidation to obtain a first dielectric oxide layer;
and step 3: depositing and etching to obtain a separation gate polycrystalline electrode;
and 4, step 4: filling the deep groove with the second dielectric oxide layer, and oxidizing the gate after etching to obtain a third dielectric oxide layer;
and 5: depositing and etching to obtain a control gate polycrystalline electrode, and depositing a fourth dielectric oxide layer;
step 6: injecting a junction-pushing second conductive type well region and a heavily-doped first conductive type region;
and 7: performing thermal oxidation to obtain a fifth dielectric oxide layer for injection protection, and etching the source contact hole;
and 8: injecting a heavily doped second conductive type region and a second conductive type region positioned below the heavily doped second conductive type region through the source contact hole;
and step 9: the metal deposition forms the source metal contact.
Preferably, in the manufacturing step 4, the gate oxide layer is obtained by thermal oxidation and deposition.
The invention has the beneficial effects that: the control gate protective layer is introduced by injecting the second conductive type region into the source contact hole, so that the increase of the surface field of the device along with the concentration of the drift region is successfully inhibited, the electric field peak value of the drift region close to the control gate is shielded, the possible advanced breakdown at the position is eliminated, and the doping concentration of the device is further improved, and the specific on-resistance is further reduced.
Drawings
FIG. 1 is a schematic diagram of a conventional split-gate VDMOS device;
fig. 2 is a schematic structural diagram of a split-gate device with a control gate protection layer according to embodiment 1 of the present invention;
fig. 3 is a schematic structural diagram of a split-gate device with a control gate protection layer according to embodiment 2 of the present invention;
fig. 4 is a schematic structural diagram of a split-gate device with a control gate protection layer according to embodiment 3 of the present invention;
FIG. 5 is a schematic diagram of a split-gate device with a control gate protection layer according to embodiment 4 of the present invention
6(a) -6(l) are schematic diagrams illustrating the process for manufacturing the split-gate device with the control gate protection layer according to embodiment 1;
fig. 6 is a graph showing simulation results of the conventional split-gate device and the split-gate device having the control gate protective layer in example 1 under the conditions of a gate oxide thickness of 15nm and a drift region resistivity of 0.09 Ω · cm;
FIG. 7 is a simulated schematic diagram of breakdown curves of a conventional split-gate device and a split-gate device with a control gate protective layer in example 1;
fig. 8 is a simulated withstand voltage curve of the conventional split-gate device and the split-gate device with the control gate protective layer in example 1;
fig. 9 shows electric field distribution along the line AA' in fig. 7 for the conventional split-gate device and the split-gate device with the control gate protective layer in example 1;
11 is a heavily doped first conductive type substrate, 12 is a first conductive type drift region, 13 is a heavily doped first conductive type region, 14 is a first conductive type region, 21 is a second conductive type well region, 22 is a second conductive type region, 23 is a heavily doped second conductive type region, 24 is a fourth dielectric oxide layer, 31 is a first dielectric oxide layer, 32 is a second dielectric oxide layer, 33 is a third dielectric oxide layer, 34 is a fourth dielectric oxide layer, 35 is a fifth dielectric oxide layer, 41 is a split gate poly electrode, 42 is a control gate poly electrode, and 51 is a source metal contact.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As shown in fig. 1, a schematic diagram of a conventional split-gate device structure is characterized in that a heavily doped second conductive type region 23 located in a second conductive type well region 21 is injected through a source contact hole to make ohmic contact without a lower second conductive type region 22; the electric field on the surface of the drift region is rapidly increased along with the increase of the concentration of the drift region, and the electric field peak exists in the first conduction type drift region 12 close to the control gate during the off-state withstand voltage, so that early breakdown and even gate oxide breakdown can be caused.
As shown in fig. 7, which is a graph of simulation results of a conventional split-gate device and a split-gate device with a control gate protective layer in embodiment 1, fig. 8 is a graph of simulation withstand voltage curves of the two, and fig. 9 is a graph of electric field distribution of the two along the line AA 'in fig. 7, it can be seen that by introducing the control gate protective layer, the split-gate device with the control gate protective layer in embodiment 1 successfully reduces the electric field peak value at the point a' of the control gate, and improves the withstand voltage of the device.
Example 1
Fig. 2 is a diagram of a split-gate device with a control gate protection layer according to embodiment 1 of the present invention, which specifically includes:
heavily doped first conductive type substrate 11, first conductive type drift region 12, first dielectric oxide layer 31, split gate polycrystalline electrode 41, second dielectric oxide layer 32, third dielectric oxide layer 33, control gate polycrystalline electrode 42, fourth dielectric oxide layer 34, second conductive type well region 21, heavily doped first conductive type region 13, fifth dielectric oxide layer 35, second conductive type region 22, heavily doped second conductive type region 23, and source metal contact 51;
the first conductive type drift region 12 is located above the heavily doped first conductive type substrate 11, the trench structure composed of the first dielectric oxide layer 31, the second dielectric oxide layer 32, the third dielectric oxide layer 33, the fourth dielectric oxide layer 34, the control gate polycrystalline electrode 41 and the separation gate polycrystalline electrode 42 is located on two sides of the first conductive type drift region 12, the fifth dielectric oxide layer 35 and the heavily doped first conductive type region 13 are located on the left and right sides of the source metal contact 51 on the surface of the device, the heavily doped second conductive type region 23 is located below the source metal contact 51 in the second conductive type well region 21 and is in short connection with the heavily doped first conductive type region 13, and the second conductive type region 22 is located below the heavily doped second conductive type region 23 and is connected with the second conductive type well region 21.
The second conductive type region 22 is located below the heavily doped second conductive type region 23 and connected to the second conductive type well region 21 as a control gate protection layer, which functions to reduce the peak value of the electric field at the corner of the control gate.
The embodiment also provides a method for manufacturing a VDMOS device with a super junction structure, which specifically includes the following steps, as shown in fig. 6(a) -6 (l):
step 1: obtaining a drift region on the substrate by means of epitaxy or implantation, as shown in fig. 6 (a);
step 2: etching the drift region by the deep groove and carrying out thermal oxidation to obtain a first dielectric oxide layer, as shown in FIG. 6(b) and FIG. 6 (c);
and step 3: depositing and etching to obtain a separation gate polycrystalline electrode as shown in FIG. 6 (d);
and 4, step 4: filling the deep groove with the second dielectric oxide layer, as shown in fig. 6(e), and oxidizing the gate after etching to obtain a third dielectric oxide layer as shown in fig. 6(f) and fig. 6 (g);
and 5: depositing and etching to obtain a control gate polycrystalline electrode, and depositing a fourth dielectric oxide layer, as shown in fig. 6 (h);
step 6: injecting a junction-push second conductive type well region and a heavily doped first conductive type region, as shown in fig. 6 (i);
and 7: performing thermal oxidation to obtain a fifth dielectric oxide layer for injection protection, and etching the source contact hole, as shown in fig. 6 (j);
and 8: implanting a heavily doped second conductive type region and a second conductive type region thereunder through the source contact hole, as shown in fig. 6 (k);
and step 9: the metal deposition forms the source metal contact as shown in fig. 6 (l).
Further, the heavily doped second conductivity type region 23 is connected to the second conductivity type well region 21, and the heavily doped second conductivity type region 23 may be connected to or disconnected from the second conductivity type region 22;
further, the second conductive type region 22 is obtained by one or more times of implantation, and the doping concentration thereof varies with the doping concentration of the first conductive type drift region 12;
further, the source metal contact 51 further extends to a position near the first conductive-type region 12 in the second conductive-type well region 21 or in the first conductive-type drift region 12.
Further, in the manufacturing step 4, the gate oxide layer is obtained by thermal oxidation and deposition.
Furthermore, the same super junction structure and the manufacturing method can be used for other groove type vertical channel devices of the same type, and the used semiconductor material can be a new generation semiconductor material such as Si or SiC; the semiconductor device to which the same control gate protective layer structure is applied is a trench gate VDMOS.
Example 2
Fig. 3 is a schematic structural diagram of a split-gate device with a control gate protection layer according to embodiment 2 of the present invention, which is different from embodiment 1 in that: the second conductivity type region 22 is formed by a plurality of different dose and energy implants, wherein the larger the energy, the smaller the implant dose, forming a trapezoidal second conductivity type region 22 with decreasing width from top to bottom. By reducing the width of the deep second conductivity-type region 22, the JFET effect is reduced there, further reducing the device specific on-resistance.
Example 3
Fig. 4(a) is a schematic structural diagram of a split-gate device with a control gate protection layer according to embodiment 3 of the present invention, in which on the basis of embodiments 1 and 2, a source metal contact 51 is extended to a position close to the drift region 12 in the second conductivity-type well region 21, and the second conductivity-type region 22 is introduced into the deep portion of the drift region in cooperation with a higher-energy implantation to further optimize the internal electric field of the drift region of the device;
fig. 4(b) shows another variation of embodiment 3 of the present invention, in which the source metal contact 51 is extended into the first conductive type drift region 12 to form a schottky contact and reduce the reverse recovery time of the device, the heavily doped second conductive type region 23 and the second conductive type region 22 function to shield the electric field peak at the schottky junction and optimize the field in the device body, and the rest of the manufacturing method and the operation principle are the same as those of embodiment 1.
Example 4
Fig. 5(b) is a schematic structural view of a split-gate device having a control gate protection layer according to embodiment 4 of the present invention, which is different from embodiment 1 in that an inclined first conductivity type implantation as shown in fig. 5(a) is added in the manufacturing step 4 shown in fig. 6(f), and local first conductivity type dopants are formed in the drift region at both sides of the second conductivity type region 22 to suppress an increase in on-resistance due to the JFET effect at that position, and the remaining manufacturing method and the operating principle are substantially the same as those of embodiment 1.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes be made by those skilled in the art without departing from the spirit and technical spirit of the present invention, and be covered by the appended claims.
Claims (9)
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| CN114628524A (en) * | 2022-02-09 | 2022-06-14 | 湖南大学 | A deep trench split-gate MOSFET with low specific on-resistance |
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