Detailed Description
The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation. The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1
As shown in fig. 1, a voltage source circuit based on an operational amplifier bootstrap and feedback circuit includes a digital-to-analog conversion excitation source, an operational amplifier bootstrap and feedback topology network circuit, and a push-pull output topology network circuit;
the output end of the digital-to-analog conversion excitation source is connected with the input end of the operational amplifier bootstrap and feedback topology network circuit and is used for providing a control circuit for the operational amplifier bootstrap and feedback topology network circuit so that the circuit of the digital-to-analog conversion excitation source is digitally controllable;
the output end of the operational amplifier bootstrap and feedback topological network circuit is connected with the input end of the push-pull output topological network circuit; meanwhile, the operation amplifier bootstrap and feedback topology network circuit realizes negative feedback by collecting the output node voltage of the push-pull output topology network circuit, and ensures that the push-pull output topology network circuit outputs a constant voltage value;
the operation amplifier bootstrap and feedback topology network circuit adjusts a voltage rail through bootstrap to realize a larger voltage output range, and converts voltage signal excitation into voltage output with stronger load capacity through the push-pull output topology network circuit to realize voltage output of more than 100V and current output of more than 1A.
In a specific embodiment, the digital-to-analog conversion excitation source comprises a digital-to-analog converter, a reference voltage source and an output stage buffer circuit;
the reference voltage source is used for providing reference voltage for the digital-to-analog converter;
the digital-to-analog converter converts a reference voltage source into a digital signal and is connected with the input end of the operational amplifier bootstrap and feedback topology network circuit through an output stage buffer circuit.
The digital-to-analog converter can adopt a high-precision integrated or discrete digital-to-analog converter; the reference voltage source can adopt a discrete or on-chip integrated low-temperature drift reference voltage source; a high precision reference voltage can be directly supplied to a digital-to-analog converter having a high precision.
The output stage buffer circuit described in this embodiment may be an amplifying or following operational amplifier output buffer circuit, which is implemented by using a prior art scheme, specifically, by using an operational amplifier, and will not be described in detail herein.
In a specific embodiment, the digital-to-analog conversion driver further comprises a first operational amplifier; the reference voltage source can also provide high-precision reference voltage for the digital-to-analog converter by the first operational amplifier to follow the output or amplify the output.
In a specific embodiment, the operational amplifier bootstrap and feedback topology network circuit comprises a second operational amplifier, a positive high-voltage power supply, a negative high-voltage power supply, a first triode, a second triode, a voltage stabilizing diode for determining the working voltage range of the second operational amplifier, and a resistor;
the positive high-voltage power supply supplies power to the second operational amplifier through the first triode; the negative high-voltage power supply supplies power to the second operational amplifier through the second triode;
or the operation amplifier bootstrap and feedback topology network circuit comprises a second operation amplifier, a positive high-voltage power supply, a negative high-voltage power supply, a first MOS tube, a second MOS tube, a voltage stabilizing diode for determining the working voltage range of the second operation amplifier and a resistor;
the positive high-voltage power supply supplies power to the second operational amplifier through the first MOS tube; and the negative high-voltage power supply supplies power to the second operational amplifier through the second MOS tube.
Example 2
As shown in fig. 2, the operational amplifier bootstrap and feedback topology network circuit provided in this embodiment includes an operational amplifier a1, a positive high-voltage power supply HV +, a negative high-voltage power supply HV-, a positive voltage rail power supply NMOS transistor Q1, a negative voltage rail power supply PMOS transistor Q2, a same-direction amplification proportional resistor R1, a same-direction amplification proportional resistor R2, a resistor R15, a resistor R16, a positive voltage rail voltage regulator ZD1, and a negative voltage rail voltage regulator ZD 2;
the positive input end of the operational amplifier A1 is connected with the output end of the output stage buffer circuit, so that the digital-to-analog conversion excitation source is used for providing a digital controllable weak excitation source for the operational amplifier bootstrap and feedback topology network circuit through the output stage buffer circuit;
the negative input end of the operational amplifier A1 is grounded through a homodromous amplification proportional resistor R2;
the positive high-voltage power supply HV + and the positive voltage rail respectively supply power to the D pole of the NMOS transistor Q1 and one end of the resistor R15;
the S pole of the positive voltage rail power supply NMOS tube Q1 is connected with a positive power supply end; the other end of the resistor R15 is connected with the output end of the operational amplifier A1 through a positive voltage rail voltage regulator tube ZD 1;
the G pole of the NMOS transistor Q1 for supplying power to the positive voltage rail is connected between a resistor R15 and a positive voltage rail voltage regulator ZD 1;
the equidirectional amplification proportional resistor R1 is connected in series between the negative input end of the operational amplifier A1 and the output end of the operational amplifier A1;
the negative electrode of the negative high-voltage power supply HV-is connected with the negative power supply end of the operational amplifier A1 through the D electrode and the S electrode of a negative voltage rail power supply PMOS tube Q2 in sequence;
the negative electrode of the negative high-voltage power supply HV-is connected with the output end of the operational amplifier A1 through a resistor R16 and a negative voltage rail voltage regulator tube ZD 2;
the G electrode of the negative voltage rail power supply PMOS tube Q2 is connected between the resistor R16 and the negative voltage rail voltage regulator tube ZD 2.
In the present embodiment, the operational amplifier a1 is characterized by having a larger supply voltage rail, but still insufficient output range for the voltage source configuration.
In this embodiment, the positive voltage rail power supply MOS transistor Q1 and the negative voltage rail power supply MOS transistor Q2 are characterized in that the positive voltage rail power supply MOS transistor is an NMOS transistor, the negative voltage rail power supply MOS transistor is a PMOS transistor, and these MOS transistors can be replaced by equivalent triodes.
In this embodiment, the positive voltage rail zener ZD1 and the negative voltage rail zener ZD2 are characterized in that the voltage value Uzd of the positive voltage rail zener ZD1 and the negative voltage rail zener ZD2 should be less than or equal to or slightly greater than one half of the maximum voltage rail for normal operation of the operational amplifier, and these zener diodes are used to determine the voltage range of the operational amplifier a1, and it can be assumed that the output voltage value of the operational amplifier a1 is Uout, and the threshold voltages of the positive voltage rail power supply NMOS Q1 and the negative voltage rail power supply PMOS Q2 are Uth, and then the voltage rail for the operational amplifier a1 to operate is Uout-Uzd + Uth-Uout + Uzd-Uth.
In this embodiment, the equidirectional amplifying proportional resistors R1 and R2 are characterized in that the resistance values thereof are determined according to the range of the output voltage, and assuming that the theoretical voltage range of the voltage source is-Umax- + Umax, the maximum current flowing through the proportional resistor is Umax/(R1+ R2), and the current value should be much smaller than the maximum output current Imax of the operational amplifier. According to the principle of the in-phase proportional amplification structure, the theoretical output value Uout of the operational amplifier structure is user signal (R1+ R2)/R2.
In this embodiment, the positive high voltage source HV + and the negative high voltage source HV-, are characterized in that the voltage values are determined by the output range of the voltage sources, and if the theoretical voltage range of the voltage sources is-Umax to + Umax, the input voltages of the positive and negative high voltage sources should satisfy HV + ≧ Umax, and HV- ≦ -Umax.
Example 3
As shown in fig. 3, the present embodiment further provides another operational amplifier bootstrapping and feedback topology network circuit, specifically, the operational amplifier bootstrapping and feedback topology network circuit includes an operational amplifier a2, a positive high-voltage power supply HV +, a negative high-voltage power supply HV-, a positive voltage rail power supply NMOS transistor Q3, a negative voltage rail power supply PMOS transistor Q4, a positive feedback proportional resistor R3, a positive feedback proportional resistor R4, a negative feedback resistor R5, a resistor R17, a resistor R18, a positive voltage rail voltage regulator ZD3, and a negative voltage rail voltage regulator ZD 4;
the positive electrode of the positive high-voltage power supply HV + is connected with the positive power supply end of the operational amplifier A2 through the D electrode and the S electrode of the NMOS tube Q3 powered by the positive voltage rail in sequence; meanwhile, the anode of the positive high-voltage power supply HV + is connected with the output end of the operational amplifier A2 through a resistor R17 and a positive voltage rail voltage regulator tube ZD3 in sequence;
the G pole of the positive voltage rail power supply NMOS tube Q3 is connected between a resistor R17 and a positive voltage rail voltage regulator tube ZD 3;
the negative electrode of the negative high-voltage power supply HV-is connected with the negative power end of the operational amplifier A2 through the D electrode and the S electrode of the negative voltage rail power supply NMOS tube Q4 in sequence; meanwhile, the negative electrode of the negative high-voltage power supply HV-is also connected with the output end of the operational amplifier A2 through a resistor R18 and a negative voltage rail voltage regulator tube ZD4 in sequence;
the G electrode of the negative voltage rail power supply NMOS tube Q4 is connected between a resistor R18 and a positive voltage rail voltage regulator tube ZD 4;
the negative feedback resistor R5 is connected in series between the negative input end and the output end of the operational amplifier A2;
the positive input end of the operational amplifier A2 is sequentially connected with a positive feedback proportional resistor R4 and the positive end of a digital-to-analog conversion excitation source; the negative end of the digital-to-analog conversion excitation source is connected with the output end of the operational amplifier A2; meanwhile, the positive input end of the operational amplifier A2 is grounded through the positive feedback proportional resistor R3.
The digital-to-analog conversion excitation source is connected with the operational amplifier A2 through an output stage buffer circuit and used for providing a digital controllable weak current excitation source for an operational amplifier bootstrap and feedback topology network circuit.
In this embodiment, the precision operational amplifier A2 is characterized in that the operational amplifier A2 used in the structure of comparative example 1 has a relatively low operating voltage rail, but has a lower input bias voltage than the operational amplifier a1 of comparative example 1. The dc output deviation of this circuit is therefore smaller than in comparative example 1.
In this embodiment, the positive voltage rail power supply MOS transistor Q3 and the negative voltage rail power supply MOS transistor Q4 are characterized in that the positive voltage rail power supply MOS transistor is an NMOS transistor, the negative voltage rail power supply MOS transistor is a PMOS transistor, and these MOS transistors can be replaced by equivalent triodes.
In this embodiment, the positive voltage rail zener ZD3 and the negative voltage rail zener ZD4 are characterized in that the regulated voltage value Uzd should be less than or equal to or slightly greater than one half of the maximum voltage rail for normal operation of the operational amplifier, and these regulators are used to determine the voltage range of the operation of the high voltage operational amplifier a2, and it can be assumed that the output voltage value of the operational amplifier a2 is Uout, and the threshold voltages of the positive voltage rail power supply NMOS Q3 and the negative voltage rail power supply PMOS Q4 are Uth, and then the voltage rail of the operation of the operational amplifier a2 is Uout-Uzd + Uth-Uout + Uzd-Uth at this time.
In this embodiment, the positive feedback proportional resistors R3 and R4 are characterized in that the principle of proportional amplification, the theoretical output value Uout of the operational amplifier structure is user signal R4/R3, and the circuit has both positive feedback and negative feedback, and according to the general principle of operational amplification, in order to realize negative feedback to stabilize the output voltage of the circuit, the strength of negative feedback must be much greater than that of positive feedback, so the resistor should be selected such that R5 is much smaller than R4, otherwise the loop would be unstable.
Example 4
As shown in fig. 4, fig. 4 is a basic topology of the voltage source structure in the present invention, and the circuit structure includes a digital-to-analog conversion excitation source 401 of push-pull output, and the internal structure is the digital-to-analog conversion excitation source structure in embodiment 2 and embodiment 3. The push-pull output topology network circuit in the embodiment comprises voltage division MOS tubes Q5, Q6 and Q7 of a positive voltage rail, voltage division MOS tubes Q8, Q9 and Q10 of a negative voltage rail, a positive voltage rail voltage-stabilized power supply V _ set +, a negative voltage rail voltage-stabilized power supply V _ set-, a grid voltage division resistor R6, R7, R8 and R9, a positive high-voltage source HV +, a negative high-voltage source HV-, and a resistor R10;
the positive electrode of the positive high-voltage source HV + is connected with the positive electrode of the positive voltage rail stabilized voltage supply V _ set + through the grid voltage dividing resistor R6 and the grid voltage dividing resistor R7 in sequence;
the negative electrode of the positive voltage rail voltage-stabilized power supply V _ set + is grounded;
the G electrode of the voltage division MOS transistor Q5 is connected between the grid voltage division resistor R6 and the grid voltage division resistor R7;
the D electrode of the voltage division MOS tube Q5 is connected between the grid voltage division resistor R6 and the positive high-voltage source HV +;
the S pole of the voltage division MOS tube Q5 is connected with the D pole of the voltage division MOS tube Q6;
the S pole of the voltage division MOS tube Q6 is respectively connected with the positive end of the operational amplifier bootstrap and feedback topology network circuit and the D pole of the voltage division MOS tube Q7;
the output end of the second operational amplifier is output through a resistor 10;
the G electrode of the voltage division MOS tube Q7 is connected between the output end of the second operational amplifier and the resistor 10;
the S pole of the voltage division MOS tube Q7 is connected with the output end of the resistor R10;
the negative electrode of the negative high-voltage source HV-sequentially passes through the D pole and the S pole of the voltage division MOS tube Q10 and the D pole and the S pole of the voltage division MOS tube Q9, and the D pole and the S pole of the voltage division MOS tube Q7 are connected to the output end of the resistor R10;
meanwhile, the negative electrode of the negative high-voltage source HV-is connected with the negative electrode of the negative voltage rail stabilized voltage supply V _ set-sequentially through the grid voltage dividing resistor R9 and the grid voltage dividing resistor R8;
the G electrode of the voltage division MOS transistor Q10 is connected between the grid voltage division resistor R9 and the grid voltage division resistor R8;
the G electrode of the voltage division MOS tube Q9 is connected between a negative voltage rail voltage-stabilized power supply V _ set-and a grid voltage division resistor R8;
the S pole of the voltage division MOS tube Q9 is also connected with the negative end of the operational amplifier bootstrap and feedback topology network circuit;
and the G electrode of the voltage division MOS tube Q8 is connected between the output end of the operational amplifier bootstrap and feedback topology network circuit and the resistor R10.
In this embodiment, the voltage amplification factor of the push-pull output topology network circuit is 1, that is, the push-pull output topology network circuit of the output stage only provides the current capability extension, and the amplitude of the output voltage is completely determined by the output excitation voltage source 401.
In this embodiment, the positive voltage rail regulated power supply V _ set + and the negative voltage rail regulated power supply V _ set-are generated by isolated transformer coils, a center tap of the transformer coils is connected to an output port of the operational amplifier in the 401 structure, and an output node of the 401 structure is used as a ground terminal of the two power supplies, amplitudes of the positive and negative voltage rail regulated power supplies are completely the same, the voltage amplitude should meet a specific power supply range Amp _ V + and Amp _ V-required by the 401 structure, and in combination with the operational amplifier bootstrap and feedback topology network circuit in embodiment 3, the amplitude of the regulated power supply should meet the condition that Amp _ V + is V _ set + -Uth > Uzd. Where Uth is the turn-on threshold voltage of the MOS transistor Q6 in fig. 4, and Uzd is the regulated voltage of the regulator used in embodiment 3.
In this embodiment, the value of the voltage dividing resistor is related to the power sharing condition of each tube in the voltage source series output structure, and assuming that the output voltage is Uout, the voltage value of the regulated power supply is Uset, and the output voltage of the high voltage is HV, the divided voltage of R6 is:
by analogy, it can be verified that the partial pressure across R7 is:
calculating according to the threshold voltage Uth of the MOS tube, the voltage at two ends of the MOS tube Q5 is as follows:
the voltage across the MOS transistor Q6 is:
in this experimental example, the load currents of the single-side power tubes are the same on the main power circuit with the serial voltage division, and in order to ensure that the load power consumptions of the two power tubes Q5 and Q6 are the same in the normal working process, the power dissipation relation P is providedQ5=PQ6The following can be obtained:
IQ5UQ5=IQ6UQ6→UQ5=UQ6
the values of R6 and R7 can be obtained by the derivation, and the values of the resistors can ensure that the power consumption of Q5 and Q6 are approximately the same. In addition, R6 and R7 should satisfy the principle that the current flowing through the voltage-dividing resistor is small, and in principle, the current flowing through the voltage-dividing resistor should be only 0.1% -% 1 of the current flowing through the MOS transistor, and this assumption needs to be adjusted according to actual situations.
In this experimental example, the operational amplifier bootstrap and feedback topology network circuit needs to acquire the voltage of the output node VOUT for feeding back the output voltage of the operational amplifier bootstrap and feedback topology network circuit, thereby realizing stable output of the voltage source structure.
In this experimental example, the resistor R10 is used to limit the output current of the bootstrap and feedback topology network circuit of the operational amplifier, and ensure that the operational amplifier structure and the like therein will not malfunction or be damaged due to the excessive load current of the voltage source.
In the experimental example, the circuit of the positive voltage part and the circuit of the negative voltage part have basically symmetrical operating principles, and the operating condition of the negative voltage part can be deduced from the operating condition of the positive voltage part.
In this embodiment, the voltage output power envelope is as shown in fig. 5, the power envelope of a general voltage source mainly outputs a positive voltage and outputs a current to the outside and outputs a negative voltage and is inputted with a current, that is, one quadrant and three quadrants in fig. 5, the power envelope of the voltage source structure related in this embodiment can completely load four quadrants, that is, has a power capability of four quadrants, and because of this characteristic, this embodiment can implement a partial function of an electronic load.
In a specific embodiment, based on the circuit structure of fig. 4, in order to further extend the function of main power path overcurrent protection, a first overcurrent protection circuit is connected in series between the positive high-voltage power supply HV + and the D pole of the voltage-dividing MOS transistor Q5, and the first overcurrent protection circuit is used for limiting the output current when the positive high-voltage power supply HV + outputs. And a second overcurrent protection circuit is connected in series between the negative high-voltage source HV-and the D pole of the MOS tube Q10, and is used for limiting the backward flow current when the negative high-voltage source HV-outputs.
In a specific embodiment, as shown in fig. 6, the first overcurrent protection circuit includes a resistor R19, a resistor R20, a resistor R11, a resistor R12, an NPN transistor N1, and an NPN transistor N2;
the positive electrode of the positive high-voltage source HV + is respectively connected with one end of the resistor R19 and the C electrode of the NPN triode N2;
the other end of the resistor R19 is respectively connected with the C pole of the NPN triode N1 and the B pole of the NPN triode N2;
resistors R11 and R12 are connected in parallel between the E pole of the NPN triode N2 and the D pole of the voltage division MOS transistor Q5;
the B pole of the NPN triode N1 is connected with the E pole of the NPN triode N2 through a resistor R20;
the E pole of the NPN triode N1 is connected with the D pole of the voltage division MOS tube Q5.
Specifically, the current limiting value of the first overcurrent protection circuit is related to the values of the parallel resistors R11 and R12 in fig. 6, and can be obtained as follows:
in a specific embodiment, as shown in fig. 7, the second overcurrent protection circuit includes a resistor R21, a resistor R22, a resistor R13, a resistor R14, a PNP transistor N3, and a PNP transistor N4;
the negative electrode of the negative high-voltage source HV-is respectively connected with one end of the resistor R21 and the C electrode of the PNP triode N4;
the other end of the resistor R21 is respectively connected with the C pole of the PNP triode N3 and the B pole of the PNP triode N4;
the E pole of the PNP triode N4 and the D pole of the voltage division MOS tube Q10 are connected with a resistor R13 and a resistor R14 in parallel;
the B pole of the PNP triode N1 is connected with the E pole of the PNP triode N4 through a resistor R22;
the pole E of the PNP triode N3 is connected with the pole D of the voltage division MOS tube Q10.
Specifically, the current limiting value of the second overcurrent protection circuit is related to the values of the parallel resistors R13 and R14 in fig. 7, and can be obtained as follows:
it should be understood that the above-described embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the claims of the present invention.