CN112151381B - Semiconductor structure and forming method thereof - Google Patents

Abstract

A semiconductor structure and a method for forming the same, the method for forming the same includes: providing a substrate, forming an interlayer dielectric layer on the substrate, forming an opening in the interlayer dielectric layer, and forming an initial gate structure in the opening, wherein the initial gate structure comprises an initial gate dielectric layer positioned at the bottom and on the side wall of the opening, an initial work function layer conformally covering the initial gate dielectric layer and an initial gate electrode layer positioned in the residual opening exposed by the initial work function layer; etching the initial gate electrode layer with partial thickness, and taking the rest initial gate electrode layer as a gate electrode layer; after forming the gate electrode layer, etching the initial work function layer and the initial gate dielectric layer with partial height on the side wall of the opening, wherein the remaining initial work function layer is used as a work function layer, and the remaining initial gate dielectric layer is used as a gate dielectric layer; forming a first protective layer on top of the gate electrode layer; and forming a second protective layer on top of the work function layer and the gate dielectric layer. The embodiment of the invention is beneficial to improving the performance of the semiconductor structure.

Description

Semiconductor structure and method of forming the same

Technical Field

The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same.

Background Art

As MOSFET devices scale down, the devices require a stacked structure with a high dielectric constant (high-k) as the gate insulating layer and a metal as the gate conductive layer to suppress problems such as high gate leakage and reduced gate capacitance caused by polysilicon gate depletion.

In order to more effectively control the profile of the gate stack, the industry currently generally adopts the gate last process, that is, usually first depositing a dummy gate made of polysilicon or other materials on the substrate, depositing an interlayer dielectric layer (ILD), removing the dummy gate, and then filling the remaining gate trench with a stack of high-k metal gate (HK/MG) layers. After that, the ILD is etched to form a contact hole that exposes the source and drain doping regions, and a metal material is deposited in the contact hole to form a contact hole plug.

However, as the integration of devices increases, the feature size of devices continues to shrink, and the gate length and the size of the source and drain regions are reduced in proportion, which brings great challenges to the contact process.

Summary of the invention

The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.

To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, an interlayer dielectric layer is formed on the substrate, an opening is formed in the interlayer dielectric layer to expose the substrate, an initial gate structure is formed in the opening, the initial gate structure includes an initial gate dielectric layer located on the bottom and side walls of the opening, an initial work function layer conformally covering the initial gate dielectric layer, and an initial gate electrode layer located in the remaining opening exposed by the initial work function layer; etching a portion of the thickness of the initial gate electrode layer, and the remaining initial gate electrode layer serves as a gate electrode layer; after forming the gate electrode layer, etching a portion of the height of the initial work function layer and the initial gate dielectric layer on the side walls of the opening, and the remaining initial work function layer serves as a work function layer, and the remaining initial gate dielectric layer serves as a gate dielectric layer; forming a first protective layer on top of the gate electrode layer; and forming a second protective layer on top of the work function layer and the gate dielectric layer.

Correspondingly, an embodiment of the present invention also provides a semiconductor structure, comprising: a substrate; an interlayer dielectric layer located on the substrate, an opening exposing the substrate being formed in the interlayer dielectric layer; an initial gate dielectric layer located on the bottom and side walls of the opening; an initial work function layer conformally covering the initial gate dielectric layer; a gate electrode layer located in the remaining opening exposed by the initial work function layer, the top of the gate electrode layer being lower than the tops of the initial gate dielectric layer and the initial work function layer.

Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

According to the embodiment of the present invention, after etching a partial thickness of the initial gate electrode layer, the remaining initial gate electrode layer is used as the gate electrode layer, and then the partial height of the initial work function layer and the initial gate dielectric layer on the side wall of the opening are etched, and the remaining initial work function layer is used as the work function layer, and the remaining initial gate dielectric layer is used as the gate dielectric layer. The initial work function layer, the initial gate dielectric layer, and the initial gate electrode layer are etched respectively by performing two etching processes, thereby preventing the process of etching the initial gate electrode layer from affecting the process of etching the initial work function layer and the initial gate electrode layer, which is beneficial to improving the uniformity of the etching rate of the initial work function layer and the initial gate dielectric layer, and further improving the height uniformity of the work function layer and the gate dielectric layer, and is beneficial to accurately control the etching amount of the initial work function layer and the initial gate dielectric layer, preventing the problem of the work function layer and the gate dielectric layer being too small in height, thereby reducing the probability of leakage current, breakdown, and other problems due to the close distance between the top of the work function layer and the gate dielectric layer and the substrate, thereby improving the performance of the semiconductor structure.

In an optional solution, the substrate includes a first device region for forming a first device and a second device region for forming a second device. In a direction perpendicular to the sidewall of the initial gate structure, the width of the initial gate electrode layer in the second device region is greater than the width of the initial gate electrode layer in the first device region. Compared with the first device region, the exposed area of the initial gate electrode layer in the second device region is larger. In the step of etching the initial gate electrode layer, the etching rate of the initial gate electrode layer in the second device region is faster. Compared with the solution of etching the initial gate electrode layer, the initial work function layer and the initial gate dielectric layer in the same step, the embodiment of the present invention performs two steps. The secondary etching process etches the initial work function layer and the initial gate dielectric layer, as well as the initial gate electrode layer, respectively, which is beneficial to preventing the problem of different areas of the initial work function layer and the initial gate dielectric layer side walls exposed by the remaining initial gate electrode layer due to different etching rates of the initial gate electrode layer in different device areas, thereby avoiding the problem of different etching rates of the initial work function layer and the initial gate dielectric layer in different device areas; therefore, the embodiment of the present invention is more effective in improving the uniformity of the etching rates of the initial work function layer and the initial gate dielectric layer, thereby significantly improving the height uniformity of the work function layer and the gate dielectric layer of different devices.

BRIEF DESCRIPTION OF THE DRAWINGS

1 to 3 are schematic structural diagrams corresponding to various steps in a method for forming a semiconductor structure;

4 to 9 are schematic structural diagrams corresponding to the steps in an embodiment of a method for forming a semiconductor structure of the present invention;

10 to 13 are schematic structural diagrams corresponding to steps in another embodiment of a method for forming a semiconductor structure of the present invention;

FIG. 14 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention.

DETAILED DESCRIPTION

The devices currently formed still have the problem of poor performance. The reasons for the poor performance of the devices are now analyzed in combination with a method for forming a semiconductor structure.

1 to 3 , schematic structural diagrams corresponding to various steps in a method for forming a semiconductor structure are shown.

Referring to Figure 1, a substrate 1 is provided, on which an interlayer dielectric layer 2 is formed, an opening (not marked) exposing the substrate 1 is formed in the interlayer dielectric layer 2, an initial gate structure 6 is formed in the opening, and the initial gate structure 6 includes an initial gate dielectric layer 3 located on the bottom and sidewalls of the opening, an initial work function layer 4 conformally covering the initial gate dielectric layer 3, and an initial gate electrode layer 5 located in the remaining opening exposed by the initial work function layer 4.

Referring to Figure 2, a partial thickness of the initial gate electrode layer 5 and a partial height of the initial work function layer 4 and the initial gate dielectric layer 3 on the side wall of the opening are etched, and the remaining initial gate electrode layer 5 serves as the gate electrode layer 9, the remaining initial work function layer 4 serves as the work function layer 8, and the remaining initial gate dielectric layer 3 serves as the gate dielectric layer 7. The gate electrode layer 9, the work function layer 8, and the gate dielectric layer 7 constitute a gate structure 10.

3 , a protection layer 11 is formed on top of the gate structure 10 .

In the formation method, the initial gate electrode layer 5, the initial work function layer 4, and the initial gate dielectric layer 3 are etched in the same step. However, the process step of etching the initial gate electrode layer 5 has a greater impact on the process of etching the initial work function layer 4 and the initial gate dielectric layer 3. For example, when the etching rate uniformity of the initial gate electrode layer 5 is poor, in the step of etching the initial gate electrode layer 5, the area of the side walls of the initial work function layer 4 and the initial gate dielectric layer 3 exposed by the remaining initial gate electrode layer 5 will also be different.

Specifically, along the direction perpendicular to the side wall of the initial gate structure 6, when the width of the initial gate electrode layer 6 is wider, the etching rate of the initial gate electrode layer 5 is faster, and the area of the side walls of the initial work function layer 4 and the initial gate dielectric layer 3 exposed by the remaining initial gate electrode layer 5 is larger, and the etching rate of the initial work function layer 4 and the initial gate dielectric layer 3 is correspondingly faster.

Therefore, when there is a difference in the area of the side walls of the initial work function layer 4 and the initial gate dielectric layer 3 exposed by the remaining initial gate electrode layer 5, this will easily lead to poor uniformity in the etching rate of the initial work function layer 4 and the initial gate dielectric layer 3, thereby resulting in poor uniformity in the height of the work function layer 8 and the gate dielectric layer 7; moreover, this will easily lead to difficulty in accurately controlling the etching amount of the initial work function layer 4 and the initial gate dielectric layer 3, thereby easily resulting in the problem of the height of the work function layer 8 and the gate dielectric layer 7 being too small, and further resulting in a high probability of leakage current, breakdown and other problems due to the top of the work function layer 8 and the gate dielectric layer 7 being too close to the substrate 1, and the performance of the formed semiconductor structure is poor.

In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, an interlayer dielectric layer is formed on the substrate, an opening is formed in the interlayer dielectric layer to expose the substrate, an initial gate structure is formed in the opening, the initial gate structure includes an initial gate dielectric layer located on the bottom and side walls of the opening, an initial work function layer conformally covering the initial gate dielectric layer, and an initial gate electrode layer located in the remaining opening exposed by the initial work function layer; etching a portion of the thickness of the initial gate electrode layer, and the remaining initial gate electrode layer serves as a gate electrode layer; after forming the gate electrode layer, etching a portion of the height of the initial work function layer and the initial gate dielectric layer on the side walls of the opening, and the remaining initial work function layer serves as a work function layer, and the remaining initial gate dielectric layer serves as a gate dielectric layer; forming a first protective layer on top of the gate electrode layer; and forming a second protective layer on top of the work function layer and the gate dielectric layer.

According to the embodiment of the present invention, after etching a partial thickness of the initial gate electrode layer, the remaining initial gate electrode layer is used as the gate electrode layer, and then the partial height of the initial work function layer and the initial gate dielectric layer on the side wall of the opening are etched, and the remaining initial work function layer is used as the work function layer, and the remaining initial gate dielectric layer is used as the gate dielectric layer. The initial work function layer, the initial gate dielectric layer, and the initial gate electrode layer are etched respectively by performing two etching processes, thereby preventing the process of etching the initial gate electrode layer from affecting the process of etching the initial work function layer and the initial gate electrode layer, which is beneficial to improving the uniformity of the etching rate of the initial work function layer and the initial gate dielectric layer, and further improving the height uniformity of the work function layer and the gate dielectric layer, and is beneficial to accurately control the etching amount of the initial work function layer and the initial gate dielectric layer, preventing the problem of the work function layer and the gate dielectric layer being too small in height, thereby reducing the probability of leakage current, breakdown, and other problems due to the close distance between the top of the work function layer and the gate dielectric layer and the substrate, thereby improving the performance of the semiconductor structure.

In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

4 to 9 are schematic structural diagrams corresponding to the steps in an embodiment of a method for forming a semiconductor structure of the present invention.

Referring to Figure 4, a substrate 100 is provided, on which an interlayer dielectric layer 110 is formed, an opening (not marked) exposing the substrate 100 is formed in the interlayer dielectric layer 110, an initial gate structure 120 is formed in the opening, and the initial gate structure 120 includes an initial gate dielectric layer 121 located on the bottom and sidewalls of the opening, an initial work function layer 122 conformally covering the initial gate dielectric layer 121, and an initial gate electrode layer 123 located in the remaining opening exposed by the initial work function layer 122.

The substrate 100 is used to provide a process platform for subsequent process steps.

In this embodiment, the semiconductor structure formed is a planar transistor as an example, and the substrate 100 accordingly only includes a substrate (not shown). In other embodiments, when the semiconductor structure formed is a fin field effect transistor (FinFET), the substrate should include a substrate and a fin protruding from the substrate.

In this embodiment, the material of the substrate is silicon. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be a silicon on insulator substrate or a germanium on insulator substrate.

In this embodiment, the substrate includes a first device region I for forming a first device and a second device region I for forming a second device, and along a direction perpendicular to the sidewall of the initial gate structure 120, the width of the initial gate electrode layer 123 of the second device region II is greater than the width of the initial gate electrode layer 123 of the first device region I. In other words, the critical dimension (Critical Dimension, CD) of the second device is greater than the critical dimension of the first device.

In this embodiment, the substrate further includes an isolation region (not shown) located between the first device region I and the second device region II, and the isolation region is used to achieve isolation between adjacent device regions.

Correspondingly, an isolation structure 103 is also formed in the substrate 100 of the isolation region. The material of the isolation structure 103 is a dielectric material. Specifically, the material of the isolation structure 103 includes one or more of silicon nitride, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride. In this embodiment, the material of the isolation structure 103 includes silicon oxide.

In this embodiment, the isolation structure 103 is a shallow trench isolation (STI) structure.

The interlayer dielectric layer 110 is used to isolate adjacent devices. Therefore, the material of the interlayer dielectric layer 110 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon nitride oxide. In this embodiment, the material of the interlayer dielectric layer 110 is silicon oxide.

The opening is used to provide a spatial location for forming the initial gate structure 120 .

The initial gate structure 120 is used for subsequently forming a gate structure.

In this embodiment, the initial gate structure 120 is formed by a gate last process, and the initial gate structure 120 is a metal gate structure.

The initial gate dielectric layer 121 is used to form a gate dielectric layer after a subsequent etching process; the initial work function layer 122 is used to form a work function layer after a subsequent etching process; and the initial gate electrode layer 123 is used to form a gate electrode layer after a subsequent etching process.

In this embodiment, the material of the initial gate dielectric layer 121 is a high-k dielectric material; wherein the high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the initial gate dielectric layer 121 is HfO ₂ . In other embodiments, the material of the initial gate dielectric layer may also be selected from ZrO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al ₂ O ₃ , etc.

In some other embodiments, the initial gate dielectric layer may include a gate oxide layer located at the bottom of the opening and an initial high-k dielectric layer located on the gate oxide layer and on the sidewalls of the opening. The gate oxide layer may be made of silicon oxide or silicon oxynitride.

When an NMOS transistor is formed, the material of the initial work function layer 122 includes one or more of titanium aluminide, tantalum carbide, aluminum or titanium carbide; when a PMOS transistor is formed, the material of the initial work function layer 122 includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride and tantalum carbide.

In this embodiment, the material of the initial gate electrode layer 123 is tungsten. In other embodiments, the material of the initial gate electrode layer can also be magnesium tungsten alloy, Al, Cu, Ag, Au, Pt, Ni or Ti.

In this embodiment, a sidewall 101 is formed on the sidewall of the initial gate structure 120. The sidewall 101 is used to protect the sidewall of the initial gate structure 120, and is also used to define the formation area of the source and drain doping regions.

The material of the sidewall 101 can be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride oxide, silicon oxycarbide, boron nitride and boron carbonitride, and the sidewall 101 can be a single-layer structure or a stacked structure. In this embodiment, the sidewall 101 is a single-layer structure, and the material of the sidewall 101 is silicon nitride.

In this embodiment, source-drain doped regions 125 are further formed in the substrate 100 on both sides of the initial gate structure 120 . Accordingly, the interlayer dielectric layer 110 also covers the source-drain doped regions 125 .

When an NMOS transistor is formed, the source-drain doped region 125 includes a stress layer doped with N-type ions, the material of the stress layer is Si or SiC, and the stress layer provides tensile stress for the channel region of the NMOS transistor, thereby facilitating the improvement of the carrier mobility of the NMOS transistor, wherein the N-type ions are P ions, As ions or Sb ions; when a PMOS transistor is formed, the source-drain doped region 125 includes a stress layer doped with P-type ions, the material of the stress layer is Si or SiGe, and the stress layer provides compressive stress for the channel region of the PMOS transistor, thereby facilitating the improvement of the carrier mobility of the PMOS transistor, wherein the P-type ions are B ions, Ga ions or In ions.

In this embodiment, a contact etch stop layer 102 is formed on the substrate 100 to conformally cover the source/drain doped regions 125 , the isolation structure 103 , and the sidewalls of the spacer 101 . The interlayer dielectric layer 110 covers the contact etch stop layer 102 .

The contact hole etching barrier layer 102 is used to define an etching stop position in a subsequent contact hole etching process, thereby reducing damage to the source-drain doped region 125 caused by the contact hole etching process.

In this embodiment, the material of the contact hole etching stop layer 102 is silicon nitride. Silicon nitride has a high density and hardness, thereby ensuring that the contact hole etching stop layer 102 can play a role in defining the etching stop position in the subsequent contact hole etching process.

5 , a portion of the initial gate electrode layer 123 (as shown in FIG. 4 ) is etched, and the remaining initial gate electrode layer 123 serves as a gate electrode layer 133 .

The gate electrode layer 133 is used to electrically lead out the gate structure, thereby achieving subsequent electrical connection between the gate structure and an external circuit or other interconnection structures.

By first etching a partial thickness of the initial gate electrode layer 123, and then etching a partial height of the initial work function layer 122 and the initial gate dielectric layer 121 on the side wall of the opening, the remaining initial work function layer 122 is used as the work function layer, and the remaining initial gate dielectric layer 121 is used as the gate dielectric layer, thereby separating the step of etching the initial gate electrode layer 123 from the step of etching the initial work function layer 122 and the initial gate dielectric layer 121, and preventing the process of etching the initial gate electrode layer 123 from affecting the process of etching the initial work function layer 122 and the initial gate electrode layer 121, for example: preventing the problem of different areas of the initial work function layer 122 and the initial gate dielectric 121 exposed on the side wall of the remaining initial gate electrode layer 123 due to different etching rates of the initial gate electrode layer 123, thereby facilitating improving the uniformity of the subsequent etching rates of the initial work function layer 122 and the initial gate dielectric layer 121, and further improving the height uniformity of the work function layer and the gate dielectric layer.

Moreover, this embodiment helps to accurately control the etching amount of the initial work function layer 122 and the initial gate dielectric layer 121 by first etching a portion of the thickness of the initial gate electrode layer 123, thereby preventing the problem of the work function layer and the gate dielectric layer being too small in height, thereby reducing the probability of leakage current, breakdown and other problems caused by the top of the work function layer and the gate dielectric layer being too close to the substrate 100, thereby improving the performance of the semiconductor structure.

In this embodiment, the substrate 100 includes a first device region I and a second device region II. Along a direction perpendicular to the sidewall of the opening, the width of the initial gate electrode layer 123 of the second device region II is greater than the width of the initial gate electrode layer 123 of the first device region II.

Compared with the first device area I, the initial gate electrode layer 123 of the second device area II is exposed in a larger area. In the step of etching the initial gate electrode layer 123, the etching rate of the initial gate electrode layer 123 of the second device area II is faster. This embodiment performs two etching processes to respectively etch the initial work function layer 122 and the initial gate dielectric layer 121, as well as the initial gate electrode layer 123, which is beneficial to prevent the problem of different areas of the side walls of the initial work function layer 122 and the initial gate dielectric layer 121 exposed by the remaining initial gate electrode layer 123 due to the different etching rates of the initial gate electrode layer 123 in different device areas, thereby avoiding the problem of different etching rates of the initial work function layer 122 and the initial gate dielectric layer 121 in different device areas; therefore, this embodiment has a more significant effect on improving the uniformity of the etching rates of the initial work function layer 122 and the initial gate dielectric layer 121, thereby significantly improving the height uniformity of the work function layer and the gate dielectric layer of different devices.

In this embodiment, a dry etching process is used to etch a portion of the thickness of the initial gate electrode layer 123. The dry etching process is a process commonly used in semiconductor processes for etching metal materials, and the dry etching process has good cross-section controllability. At the same time, the use of the dry etching process is also conducive to improving the etching efficiency of the initial gate electrode layer 123 and accurately controlling the etching amount of the initial gate electrode layer 123.

In this embodiment, the material of the initial gate electrode layer 123 is tungsten, and the etching gas of the dry etching process includes CF ₄ and Cl ₂ .

_CF4 and _Cl2 are commonly used etching gases for etching the initial gate electrode layer 123 in semiconductor processes, and have high process compatibility. In the process of the dry etching process, it is easy to adjust the etching gas ratio, process pressure, process temperature and other parameters in the dry etching process so that the etching selectivity ratio between the initial gate electrode layer 123 and the initial gate dielectric layer 121, and the etching selectivity ratio between the initial gate electrode layer 123 and the initial work function layer 122 are both large, so that the initial gate electrode layer 123 can be etched in a maskless etching manner, and at the same time, the damage to the initial gate dielectric layer 121 and the initial work function layer 122 is small.

6 and 7 , a first protection layer 112 is formed on the top of the gate electrode layer 133 (as shown in FIG. 7 ).

The first protective layer 112 is used to protect the top of the gate electrode layer 133. In the subsequent self-aligned etching process for forming contact holes to expose the source and drain doping regions 125, the first protective layer 112 can also define the stop position of the self-aligned etching process, thereby preventing the etching process from causing damage to the gate electrode layer 133, and further preventing the contact hole plug from bridging the gate electrode layer 133 after the subsequent formation of the contact hole plug.

In this embodiment, the first protection layer 112 is formed before etching a portion of the height of the initial work function layer 122 and the initial gate dielectric layer 121 on the sidewall of the opening.

In the present embodiment, in the step of forming the first protective layer 112 on the top of the gate electrode layer 133, the first protective layer 112 exposes the top of the initial work function layer 122 and the initial gate dielectric layer 121, and the first protective layer 112 covers the side walls of the initial work function layer 122 exposed by the gate electrode layer 133, so that the first protective layer 112 can be used as an etching mask for subsequent etching of the initial work function layer 122 and the initial gate dielectric layer 121, which is beneficial to simplify the process flow and improve process integration.

Moreover, after forming the first protective layer 112, the first protective layer 112 covers the side walls of the initial work function layer 122 exposed by the gate electrode layer 133, and the areas of the initial work function layer 122 and the initial gate dielectric layer 121 exposed by the first protective layer 112 in the first device area I and the second device area II are the same, thereby significantly improving the subsequent uniformity of the etching rate of the initial work function layer 122 and the initial gate dielectric layer 121 in different device areas.

In this embodiment, the material of the first protective layer 112 is silicon nitride. Silicon nitride has relatively high hardness and density, which is beneficial to improving the protective effect of the first protective layer 112 on the gate electrode layer 133.

In other embodiments, the material of the first protective layer may also be silicon oxide or polysilicon.

In this embodiment, the step of forming the first protective layer 112 includes: as shown in Figure 6, forming a first protective material layer 111 covering the gate electrode layer 133, the initial work function layer 122 and the initial gate dielectric layer 121; as shown in Figure 7, using a planarization process to remove the first protective material layer 111 above the top of the initial work function layer 122 and the initial gate dielectric layer 121, and the remaining first protective material layer 111 located on the top of the gate electrode layer 133 is used as the first protective layer 112.

In this embodiment, the first protective material layer 111 is formed by an atomic layer deposition (ALD) process.

The atomic layer deposition process has good gap filling performance and step coverage capability, thereby improving the coverage capability of the first protective material layer 111. Moreover, the atomic layer deposition process includes multiple atomic layer deposition cycles to form a film layer of desired thickness, which is beneficial to improving the thickness uniformity and density of the first protective material layer 111, while enabling the thickness of the first protective material layer 111 to be precisely controlled, which is correspondingly beneficial to improving the formation quality of the first protective layer 112 and precisely controlling the thickness of the first protective layer 112.

The atomic layer deposition process has good step coverage capability. Therefore, in this embodiment, the first protective material layer 111 conformally covers the gate electrode layer 133 , the interlayer dielectric layer 110 , and the top of the initial gate dielectric layer 121 and the initial work function layer 122 .

Specifically, the width of the gate electrode layer 133 of the first device area I is relatively small. In the step of forming the first protective material layer 111, as the thickness of the deposited material increases, the first protective material layer 111 located on the side wall of the initial work function layer 132 of the first device area I gradually contacts, thereby being able to fill the remaining opening exposed by the gate electrode layer 133 of the first device area I.

In the present embodiment, the width of the gate electrode layer 133 of the second device region II is relatively large. In the step of forming the first protective material layer 111, the first protective material layer 111 located on the side wall of the initial work function layer 132 in the second device region II is difficult to gradually contact. Therefore, in the present embodiment, the thickness of the formed first protective material layer 111 is relatively large, so that the first protective material layer 111 located on the top of the gate electrode layer 133 in the second device region II can fill the remaining opening to prepare for the subsequent planarization process.

The planarization process may be a chemical mechanical polishing process or a dry etching process. In this embodiment, the planarization process is performed by a dry etching process. The dry etching process has good process controllability and profile controllability, which is conducive to accurately controlling the etching amount of the first protective material layer 111 and also helps to improve the etching efficiency.

In this embodiment, the first protective layer 112 is used as an example to fill the remaining opening exposed by the gate electrode layer 133. In other embodiments, according to the actual process, the first protective layer may not fill the remaining opening, but only needs to expose the top of the initial work function layer and the initial gate dielectric layer, and cover the side wall of the initial work function layer exposed by the gate electrode layer.

In some other embodiments, after etching a portion of the height of the initial work function layer and the initial gate dielectric layer on the sidewalls of the opening, a first protection layer may be formed on top of the gate electrode layer.

Referring to Figure 8, after the gate electrode layer 133 is formed, the initial work function layer 122 and the initial gate dielectric layer 121 are etched to a partial height on the side wall of the opening, and the remaining initial work function layer 122 serves as the work function layer 132, and the remaining initial gate dielectric layer 121 serves as the gate dielectric layer 131.

The work function layer 132 is used to adjust the work function value of the device, and further adjust the threshold voltage of the device; the gate dielectric layer 131 is used to isolate the gate structure and the substrate 100.

The gate dielectric layer 131 , the work function layer 132 and the gate electrode layer 133 form a gate structure 130 , and the gate structure 130 is used to control the opening or closing of the conductive channel when the device is working.

By performing two etching processes to respectively etch the initial work function layer 122 and the initial gate dielectric layer 121, and the initial gate electrode layer 123, the process step of etching the initial gate electrode layer 123 is prevented from affecting the process of etching the initial work function layer 122 and the initial gate electrode layer 121, which is beneficial to improving the uniformity of the etching rate of the initial work function layer 122 and the initial gate dielectric layer 121, thereby improving the height uniformity of the work function layer 132 and the gate dielectric layer 131, and is beneficial to accurately control the etching amount of the initial work function layer 122 and the initial gate dielectric layer 121, preventing the problem of the work function layer 132 and the gate dielectric layer 131 being too small, thereby reducing the probability of leakage current, breakdown and other problems caused by the top of the work function layer 132 and the gate dielectric layer 131 being too close to the substrate 100, thereby improving the performance of the semiconductor structure.

In this embodiment, the substrate 100 includes a first device region I and a second device region II. Along the direction perpendicular to the side wall of the opening, the width of the initial gate electrode layer 123 of the second device region II is greater than the width of the initial gate electrode layer 123 of the first device region II. Therefore, this embodiment can significantly improve the uniformity of the etching rate of the initial work function layer 122 and the initial gate dielectric layer 121, thereby significantly improving the height uniformity of the work function layer 132 and the gate dielectric layer 131 of different devices.

Specifically, the first protective layer 112 exposes the top of the initial work function layer 122 and the initial gate dielectric layer 121, and covers the side walls of the initial work function layer 122 exposed by the gate electrode layer 133. Therefore, in the step of etching the initial work function layer 122 and the initial gate dielectric layer 121 at a partial height of the upper side walls of the opening, the exposed areas of the initial work function layer 122 and the initial gate dielectric layer 121 are the same, thereby ensuring that the etching rates of the initial work function layer 122 and the initial gate dielectric layer 121 are uniform.

In this embodiment, after the first protection layer 112 is formed on the top of the gate electrode layer 133 , the initial work function layer 122 and the initial gate dielectric layer 121 on the sidewalls of the opening are etched.

Therefore, the initial work function layer 122 and the initial gate dielectric layer 121 are etched to a certain height of the upper sidewall of the opening using the first protection layer 112 as a mask.

Correspondingly, after the gate structure 130 is formed, the gate structure 130 , the first protection layer 112 , and the interlayer dielectric layer 110 form a groove 200 .

In this embodiment, a dry etching process is used to etch the initial work function layer 122 and the initial gate dielectric layer 121. The dry etching process has good process controllability and profile controllability, which is conducive to accurately controlling the etching amount of the initial work function layer 122 and the initial gate dielectric layer 121, so that the height of the work function layer 132 and the gate dielectric layer 131 meets the process requirements, and is also conducive to improving the etching efficiency.

Specifically, a dry etching process is used to etch the initial work function layer 122 and the initial gate dielectric layer 121. The main etching gas of the dry etching process includes CF ₄ and Cl ₂ .

The dry etching process is easy to achieve anisotropic etching, thereby reducing the probability of consuming other film layer structures (for example, the gate electrode layer 133) during the process of etching the initial work function layer 122 and the initial gate dielectric layer 121 of a partial height. Moreover, in the dry etching process, it is also easy to increase the etching selectivity of the initial work function layer 122 and the initial gate dielectric layer 121 to the gate electrode layer 133 by adjusting process parameters such as the proportion of etching gas, process pressure, and process temperature. In addition, the use of the dry etching process is also conducive to accurately controlling the etching amount of the initial work function layer 122 and the initial gate dielectric layer 121, and improving the etching efficiency, so that the height of the work function layer 132 and the gate dielectric layer 131 meets the process requirements.

In this embodiment, the top of the work function layer 132 and the gate dielectric layer 131 is taken as an example to be lower than the top of the gate electrode layer 133. In other embodiments, according to process requirements, the top of the work function layer and the gate dielectric layer may also be flush with the top of the gate electrode layer.

9 , a second protection layer 113 is formed on top of the work function layer 132 and the gate dielectric layer 131 .

The second protective layer 113 is used to protect the work function layer 132 and the top of the gate dielectric layer 131. In the subsequent self-aligned etching process for forming contact holes to expose the source and drain doped regions 125, the second protective layer 113 and the first protective layer 112 jointly define the stop position of the self-aligned etching process, thereby preventing the etching process from causing damage to the gate structure 130, and preventing the contact hole plug from bridging the gate structure 130 after the subsequent formation of the contact hole plug.

In this embodiment, the material of the second protection layer 113 is silicon nitride.

In this embodiment, the gate structure 130 and the first protective layer 112 and the interlayer dielectric layer 110 form a groove 200 (as shown in Figure 8), so the groove 200 is filled to form a second protective layer 113 located on top of the work function layer 132 and the gate dielectric layer 131.

Specifically, the step of forming the second protective layer 113 includes: forming a second protective material layer (not shown) in the groove 200, and the second protective material layer also covers the first protective layer 112; using a planarization process to remove the second protective material layer above the top of the first protective layer 112, and the remaining second protective material layer serves as the second protective layer 113.

In this embodiment, the second protective material layer is formed by an atomic layer deposition process. The atomic layer deposition process has good gap filling performance and step coverage, thereby improving the coverage of the second protective material layer at the bottom and sidewall of the groove 200. Moreover, the atomic layer deposition process includes performing multiple atomic layer deposition cycles to form a film layer of the desired thickness, which is beneficial to improving the thickness uniformity and density of the second protective material layer, and at the same time enables the thickness of the second protective material layer to be accurately controlled, which is correspondingly beneficial to improving the formation quality of the second protective layer 113 and accurately controlling the thickness of the second protective layer 113.

The opening width of the groove 200 is small. In the step of depositing the second protective material layer, as the thickness of the deposited material increases, the second protective material layer on the side wall of the groove 200 gradually contacts, so that the second protective material layer fills the groove 200.

In this embodiment, the planarization process is performed using a chemical mechanical polishing process, which is beneficial to improving the flatness of the top surface of the second protective layer 113. Specifically, an endpoint detection (EPD) method is used, with the top of the second protective layer 113 as the polishing stop position.

In other embodiments, a dry etching process may also be used to perform the planarization process.

In this embodiment, after forming the first protective layer 112 , etching a portion of the height of the initial work function layer 122 and the initial gate dielectric layer 121 on the sidewall of the opening is taken as an example. Therefore, after forming the first protective layer 112 , the second protective layer 113 is formed.

10 to 13 , schematic structural diagrams corresponding to the steps in another embodiment of the method for forming a semiconductor structure of the present invention are shown.

The similarities between the embodiment of the present invention and the previous embodiment are not repeated here. The difference between the present invention and the previous embodiment is that after etching the initial work function layer and the initial gate dielectric layer of a partial height on the side wall of the opening, a first protective layer is formed on the top of the gate electrode layer.

By forming the first protective layer after etching the initial work function layer and the initial gate dielectric layer of a partial height on the side wall of the opening, it is beneficial to prevent the first protective layer from being damaged during the step of etching the initial work function layer and the initial gate dielectric layer, thereby improving the formation quality of the first protective layer, and further ensuring the protective effect of the first protective layer on the gate electrode layer in the subsequent self-aligned contact etching process.

Referring to Figure 10, after the gate electrode layer 233 is formed, before etching the initial work function layer 222 and the initial gate dielectric layer 221 at a partial height on the side wall of the opening, it also includes: forming a sacrificial layer 215 on the top of the gate electrode layer 233, the sacrificial layer 215 exposing the top of the initial work function layer 222 and the initial gate dielectric layer 221, and the sacrificial layer 215 covers the side wall of the initial work function layer 222 exposed by the gate electrode layer 233.

The sacrificial layer 215 is used as an etching mask for subsequently etching a portion of the height of the initial work function layer 222 and the initial gate dielectric layer 221 on the sidewall of the opening. The sacrificial layer 215 also protects the gate electrode layer 233 .

The material of the sacrificial layer 215 includes polysilicon. Polysilicon is a commonly used material in semiconductor processes, and has high process compatibility. In addition, by selecting polysilicon material, in the subsequent process of removing the sacrificial layer 215, it is easy to make the etching selectivity of the sacrificial layer 215 and the interlayer dielectric layer 210, and the sacrificial layer 215 and the gate structure 230 larger, thereby reducing the process difficulty of removing the sacrificial layer 215 and reducing the damage to other film structures.

In this embodiment, the process steps for forming the sacrificial layer 215 may refer to the related description of the process steps for forming the first protective layer in the above-mentioned embodiment, which will not be repeated here.

Referring to Figure 11, after the gate electrode layer 233 is formed, the initial work function layer 222 and the initial gate dielectric layer 221 are etched to a partial height on the side wall of the opening, and the remaining initial work function layer 222 serves as the work function layer 232, and the remaining initial gate dielectric layer 221 serves as the gate dielectric layer 231.

In this embodiment, the sacrificial layer 215 is formed on the top of the gate electrode layer 233 , and therefore, the sacrificial layer 215 is used as a mask to etch a portion of the height of the initial work function layer 222 and the initial gate dielectric layer 221 on the sidewall of the opening.

The process of etching the initial work function layer 222 and the initial gate dielectric layer 221 is the same as that in the above embodiment, and will not be described again.

12 , after etching the initial work function layer 222 and the initial gate dielectric layer 221 , the work function layer 232 , the gate dielectric layer 231 and the gate electrode layer 233 constitute a gate structure 230 , and the formation method further includes: removing the sacrificial layer 215 to form a groove 400 surrounded by the gate structure 230 and the interlayer dielectric layer 210 .

The sacrificial layer 215 is removed to expose the top of the gate electrode layer 233 , in preparation for subsequently forming a first protection layer on the top of the gate electrode layer 233 and a second protection layer on the top of the work function layer 232 and the gate dielectric layer 231 .

In this embodiment, a wet etching process is used to remove the sacrificial layer 215. Specifically, the etching solution of the wet etching process can be a hot phosphoric acid solution.

13 , a first protection layer 220 is formed on top of the gate electrode layer 233 .

Continuing to refer to FIG. 13 , a second protection layer 225 is formed on top of the work function layer 232 and the gate dielectric layer 231 .

In this embodiment, the first protective layer 220 and the second protective layer 225 are formed in the same step. The formation quality of the first protective layer 220 and the second protective layer 225 is good, which is conducive to simplifying the process steps and improving the process integration.

Specifically, the steps of forming the first protective layer 220 and the second protective layer 225 include: filling the groove 400 (as shown in Figure 12), forming the first protective layer 220 located on the top of the gate electrode layer 233, and the second protective layer 225 located on the top of the gate dielectric layer 231 and the work function layer 232.

In this embodiment, the process of forming the first protective layer 220 and the second protective layer 225 is the same as the process steps of forming the second protective layer in the above-mentioned embodiment, and will not be repeated here.

Correspondingly, the present invention further provides a semiconductor structure. Referring to FIG14 , a schematic diagram of the structure of an embodiment of the semiconductor structure of the present invention is shown.

The semiconductor structure includes: a substrate 400; an interlayer dielectric layer 410, which is located on the substrate 400, and an opening (not marked) is formed in the interlayer dielectric layer 410 to expose the substrate 400; an initial gate dielectric layer 421, which is located on the bottom and side walls of the opening; an initial work function layer 422, which conformally covers the initial gate dielectric layer 421; and a gate electrode layer 433, which is located in the remaining opening exposed by the initial work function layer 422, and the top of the gate electrode layer 433 is lower than the tops of the initial gate dielectric layer 421 and the initial work function layer 422.

The gate electrode layer 433 is formed by etching the initial gate electrode layer. In the process of etching the initial gate electrode layer in this embodiment, the initial work function layer 422 and the initial gate dielectric layer 421 of the upper part of the height of the opening side wall are not etched, so that two etching processes can be performed to etch the initial work function layer 422 and the initial gate dielectric layer 421, and the initial gate electrode layer respectively, so as to prevent the process of etching the initial gate electrode layer from affecting the process of etching the initial work function layer 422 and the initial gate electrode layer 421, which is beneficial to improve the uniformity of the etching rate of the initial work function layer 422 and the initial gate dielectric layer 421, thereby improving the height uniformity of the work function layer and the gate dielectric layer, and is beneficial to accurately control the etching amount of the initial work function layer 422 and the initial gate dielectric layer 421, preventing the problem of the height of the work function layer and the gate dielectric layer being too small, thereby reducing the probability of leakage current, breakdown and other problems caused by the top of the work function layer and the gate dielectric layer being too close to the substrate 400, thereby improving the performance of the semiconductor structure.

The substrate 400 is used to provide a process platform for forming a semiconductor structure.

In this embodiment, the semiconductor structure formed is a planar transistor as an example, and the base 400 accordingly only includes a substrate (not shown). In other embodiments, when the semiconductor structure formed is a fin field effect transistor, the base should include a substrate and a fin protruding from the substrate.

In this embodiment, the material of the substrate is silicon. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be a silicon on insulator substrate or a germanium on insulator substrate.

In this embodiment, the substrate 400 includes a first device region I for forming a first device and a second device region I for forming a second device, and along a direction perpendicular to the sidewall of the gate electrode layer 433, the width of the gate electrode layer 433 in the second device region II is greater than the width of the gate electrode layer 433 in the first device region I. In other words, the critical dimension of the second device is greater than the critical dimension of the first device.

The gate electrode layer 433 is formed by etching the initial gate electrode layer. Compared with the first device area I, the initial gate electrode layer of the second device area II is exposed in a larger area. In the step of etching the initial gate electrode layer to form the gate electrode layer 433, the etching rate of the initial gate electrode layer of the second device area II is faster. In this embodiment, the initial work function layer 422, the initial gate dielectric layer 421, and the initial gate electrode layer are respectively etched by performing two etching processes, which is conducive to preventing the problem of different areas of the side walls of the initial work function layer 422 and the initial gate dielectric layer 421 exposed by the remaining initial gate electrode layer due to different etching rates of the gate electrode layers in different device areas, thereby avoiding the problem of different etching rates of the initial work function layer 422 and the initial gate dielectric layer 421 in different device areas; therefore, the embodiment has a more significant effect on improving the uniformity of the etching rates of the initial work function layer 422 and the initial gate dielectric layer 421, thereby significantly improving the height uniformity of the work function layer and the gate dielectric layer of different devices.

In this embodiment, the substrate 400 further includes an isolation region (not shown) located between the first device region I and the second device region II, and the isolation region is used to achieve isolation between adjacent device regions.

Therefore, in this embodiment, the semiconductor structure further includes: an isolation structure 403, located in the substrate 400 of the isolation region. The material of the isolation structure 403 is a dielectric material. Specifically, the material of the isolation structure 403 includes one or more of silicon nitride, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride. In this embodiment, the material of the isolation structure 403 includes silicon oxide.

In this embodiment, the isolation structure 403 is a shallow trench isolation structure.

The interlayer dielectric layer 410 is used to isolate adjacent devices. Therefore, the material of the interlayer dielectric layer 410 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon nitride oxide. In this embodiment, the material of the interlayer dielectric layer 410 is silicon oxide.

The opening provides a space for forming the initial gate dielectric layer 421 , the initial work function layer 422 , and the gate electrode layer 433 .

The initial gate dielectric layer 421 is used to form a gate dielectric layer after a subsequent etching process; the initial work function layer 422 is used to form a work function layer after a subsequent etching process.

The gate electrode layer 433 and the subsequent work function layer and gate dielectric layer form a gate structure, thereby controlling the opening or closing of the conductive channel when the device is working.

In this embodiment, the material of the initial gate dielectric layer 421 is a high-k dielectric material; wherein the high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the initial gate dielectric layer 421 is HfO ₂ . In other embodiments, the material of the initial gate dielectric layer may also be selected from ZrO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al ₂ O ₃ , etc.

In some other embodiments, the initial gate dielectric layer may include a gate oxide layer located at the bottom of the opening and an initial high-k dielectric layer located on the gate oxide layer and on the sidewalls of the opening. The gate oxide layer may be made of silicon oxide or silicon oxynitride.

When an NMOS transistor is formed, the material of the initial work function layer 422 includes one or more of titanium aluminide, tantalum carbide, aluminum or titanium carbide; when a PMOS transistor is formed, the material of the initial work function layer 422 includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride and tantalum carbide.

The gate electrode layer 433 is used to electrically lead out the gate structure, thereby realizing electrical connection between the gate structure and an external circuit or other interconnection structures;

In this embodiment, the material of the gate electrode layer 433 is tungsten. In other embodiments, the material of the gate electrode layer may also be magnesium-tungsten alloy, Al, Cu, Ag, Au, Pt, Ni or Ti.

In this embodiment, the semiconductor structure also includes: a protective layer 412, located on the top of the gate electrode layer 433, the protective layer 412 exposes the top of the initial work function layer 422 and the initial gate dielectric layer 421, and covers the side wall of the initial work function layer 422 exposed by the gate electrode layer 433.

The protective layer 412 is used to protect the top of the gate electrode layer 433. In the subsequent self-aligned etching process for forming contact holes to expose the source and drain doping regions 425, the protective layer 412 is also used to define the stop position of the self-aligned etching process, thereby preventing the etching process from causing damage to the gate electrode layer 433, and further preventing the contact hole plug from bridging the gate electrode layer 433 after the subsequent formation of the contact hole plug.

In this embodiment, the protective layer 412 also exposes the top of the initial work function layer 422 and the initial gate dielectric layer 421, so that the initial work function layer 422 and the initial gate dielectric layer 421 can be etched to a partial height of the upper side wall of the opening using the protective layer 412 as a mask, which is beneficial to simplifying the process flow and improving process integration.

Moreover, the areas of the initial work function layer 422 and the initial gate dielectric layer 421 exposed by the protective layer 412 of the first device region I and the second device region II are the same, thereby significantly improving the uniformity of the subsequent etching rates of the initial work function layer 422 and the initial gate dielectric layer 421 of different device regions.

In this embodiment, the material of the protective layer 412 is silicon nitride. Silicon nitride has relatively high hardness and density, which is beneficial to improving the protective effect of the protective layer 412 on the gate electrode layer 433.

In other embodiments, the material of the protection layer may also be silicon oxide or polysilicon.

In this embodiment, a sidewall 401 is formed on the sidewall of the initial gate dielectric layer 421. The sidewall 401 is used to protect the sidewall of the gate structure, and is also used to define the formation area of the source and drain doping region 425.

The material of the sidewall 401 can be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride oxide, silicon oxycarbide, boron nitride and boron carbonitride, and the sidewall 401 can be a single-layer structure or a stacked structure. In this embodiment, the sidewall 401 is a single-layer structure, and the material of the sidewall 401 is silicon nitride.

In this embodiment, the semiconductor structure further includes: source-drain doped regions 425 located in the substrate 400 at both sides of the opening. Accordingly, the interlayer dielectric layer 410 also covers the source-drain doped regions 425 .

When an NMOS transistor is formed, the source-drain doped region 425 includes a stress layer doped with N-type ions, the material of the stress layer is Si or SiC, and the stress layer provides tensile stress for the channel region of the NMOS transistor, thereby facilitating the improvement of the carrier mobility of the NMOS transistor, wherein the N-type ions are P ions, As ions or Sb ions; when a PMOS transistor is formed, the source-drain doped region 425 includes a stress layer doped with P-type ions, the material of the stress layer is Si or SiGe, and the stress layer provides compressive stress for the channel region of the PMOS transistor, thereby facilitating the improvement of the carrier mobility of the PMOS transistor, wherein the P-type ions are B ions, Ga ions or In ions.

In this embodiment, the semiconductor structure further includes: a contact hole etching stop layer 402 conformally covering the source and drain doping regions 425 , the isolation structure 403 , and the sidewalls of the spacer 401 . The interlayer dielectric layer 410 covers the contact hole etching stop layer 402 .

The contact hole etching barrier layer 402 is used to define an etching stop position in a subsequent contact hole etching process, thereby reducing damage to the source-drain doped region 425 caused by the contact hole etching process.

In this embodiment, the material of the contact hole etching stop layer 402 is silicon nitride. Silicon nitride has a high density and hardness, thereby ensuring that the contact hole etching stop layer 402 can play a role in defining the etching stop position in the subsequent contact hole etching process.

The semiconductor structure can be formed by the formation method described in the above embodiment, or by other formation methods. For the specific description of the semiconductor structure described in this embodiment, reference can be made to the corresponding description in the above embodiment, and this embodiment will not be repeated here.

Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims (13)

1. A method of forming a semiconductor structure, comprising:

Providing a substrate, wherein an interlayer dielectric layer is formed on the substrate, an opening exposing the substrate is formed in the interlayer dielectric layer, an initial gate structure is formed in the opening, and the initial gate structure comprises an initial gate dielectric layer positioned on the bottom and the side wall of the opening, an initial work function layer covering the initial gate dielectric layer in a conformal manner, and an initial gate electrode layer positioned in the rest of the opening exposed by the initial work function layer;

Etching part of the initial gate electrode layer with the thickness, and taking the rest of the initial gate electrode layer as a gate electrode layer;

forming a first protection layer on the top of the gate electrode layer, wherein the first protection layer plays a role in defining a stop position of the self-aligned etching process in the self-aligned etching process of subsequently forming a contact hole exposing the source-drain doped region;

After forming the first protective layer on the top of the gate electrode layer, etching the initial work function layer and the initial gate dielectric layer with partial heights on the side wall of the opening, wherein the rest of the initial work function layer is used as a work function layer, and the rest of the initial gate dielectric layer is used as a gate dielectric layer;

and forming a second protective layer on top of the work function layer and the gate dielectric layer.

2. The method of forming a semiconductor structure of claim 1, wherein in the step of forming a first protective layer on top of the gate electrode layer, the first protective layer exposes the initial work function layer and a top of an initial gate dielectric layer, and the first protective layer covers sidewalls of the initial work function layer exposed by the gate electrode layer;

and etching the initial work function layer and the initial gate dielectric layer on the side wall of the opening by taking the first protective layer as a mask.

3. The method of forming a semiconductor structure of claim 2, wherein the gate dielectric layer, work function layer and gate electrode layer form a gate structure, and the gate structure, the first protective layer and the interlayer dielectric layer enclose a recess;

the step of forming the second protective layer includes: and filling the groove to form a second protective layer positioned on the tops of the work function layer and the gate dielectric layer.

4. The method of forming a semiconductor structure of claim 1, wherein the substrate comprises a first device region for forming a first device and a second device region for forming a second device, the second device region having an initial gate electrode layer width greater than an initial gate electrode layer width of the first device region in a direction perpendicular to the initial gate structure sidewall.

5. The method of forming a semiconductor structure of claim 1, wherein a dry etching process is used to etch a portion of the thickness of the initial gate electrode layer.

6. The method of claim 5, wherein the dry etching process etching gas comprises CF ₄ and Cl ₂.

7. The method of forming a semiconductor structure of claim 1, wherein the step of forming the first protective layer comprises: forming a first protective material layer covering the gate electrode layer, the initial work function layer and the initial gate dielectric layer; and removing the first protective material layer higher than the initial work function layer and the top of the initial gate dielectric layer by adopting a planarization process, and taking the rest of the first protective material layer positioned on the top of the gate electrode layer as the first protective layer.

8. The method of forming a semiconductor structure of claim 7, wherein the process of forming the first protective material layer comprises an atomic layer deposition process.

9. The method of forming a semiconductor structure of claim 1, wherein the initial work function layer and the initial gate dielectric layer are etched using a dry etching process.

10. The method of claim 9, wherein the dry etching process etching gas comprises CF ₄ and Cl ₂.

11. The method of forming a semiconductor structure of claim 3, wherein the step of forming the second protective layer comprises: forming a second protective material layer in the groove, wherein the second protective material layer also covers the first protective layer; and removing the second protective material layer higher than the top of the first protective layer by adopting a planarization process, and taking the rest of the second protective material layer as the second protective layer.

12. The method of forming a semiconductor structure of claim 11, wherein forming the second protective material layer comprises an atomic layer deposition process.

13. The method of forming a semiconductor structure according to claim 7 or 11, wherein the planarization process is performed using a chemical mechanical polishing process or a dry etching process.