CN112131037B - memory device - Google Patents

Abstract

The invention provides a memory device. The data read-write circuit is used for accessing the data of the memory cell array. The correction data read-write circuit is used for accessing correction data of the correction data storage unit array. The syndrome arithmetic circuit generates an error decoding signal based on the data received from the data read/write circuit and the correction data received from the correction data read/write circuit. In the same reading period of the read data, the data read-write circuit corrects the error bit in the data according to the error decoding signal and outputs the correct data and the correction bit signal. The syndrome arithmetic circuit also outputs a correction data write signal to the correction data read/write circuit according to the correction bit signal to update the correction data in the correction data memory cell array. The data read-write circuit also writes the corrected data back to the memory cell array.

Description

memory device

Technical field

The present invention relates to a memory device, and in particular to a memory device with error checking and error correction functions.

Background technique

With the advancement of technology, consumer demand for storage media has also increased rapidly. Dynamic Random Access Memory (DRAM) has the advantages of simple structure, high density, and low cost, so it is widely used in various applications. kind of electronic device. In order to improve the data reliability of DRAM, some DRAMs are equipped with error-correcting code memory (ECC memory) to detect error bits in stored data and correct the error bits. At present, DRAM mainly uses single error correction (Single Error Correcting) technology, but single error correction technology can only correct one bit of error at a time. If the stored data has more than 2 bit errors at the same time, the error correction function of the ECC circuit will fail. However, soft errors (Softerror) may occur during DRAM operation due to factors such as high temperature and refresh, resulting in erroneous bits. If the error bits cannot be corrected in time, the stored data may accumulate two error bits and reduce the data reliability of the memory. Therefore, how to correct the stored data in time to avoid accumulating more than two error bits and maintain the data accuracy of DRAM has become a problem to be overcome.

Contents of the invention

The present invention provides a memory device that can instantly correct erroneous bits and update stored data and correction data for error checking and correction during a data reading cycle.

A memory device of the present invention includes: a data reading and writing circuit, a correction data reading and writing circuit and a syndrome operation circuit. The data reading and writing circuit is coupled to the memory cell array and used to access data in the memory cell array. The correction data reading and writing circuit is coupled to the correction data storage unit array and used to access the correction data of the correction data storage unit array. The syndrome operation circuit generates an error decoding signal based on the data received from the data reading and writing circuit and the correction data received from the correction data reading and writing circuit, wherein in the same reading cycle of reading the data, the data reading and writing circuit generates an error decoding signal according to the error The decoded signal corrects the erroneous bits in the data and outputs correct data and correction bit signals. The data read and write circuit writes the corrected data back to the memory cell array. The syndrome operation circuit also outputs correction data and writes it according to the correction bit signal. The signal is sent to the correction data read-write circuit to update the correction data in the correction data storage cell array.

Based on the above, the memory device of the present invention can read data from the memory cell array and complete checking and correction in one read cycle. When an erroneous bit is found in the data, the memory device of the present invention can immediately correct the error to output correct data in the same read cycle, and correspondingly write the corrected data back to the storage unit in a continuous period array and writes the updated correction data back to the correction data storage cell array. Thereby, the memory device of the present invention can improve data reliability.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, embodiments are given below and described in detail with reference to the accompanying drawings.

Description of the drawings

Figure 1 is a block diagram of a memory device according to an embodiment of the present invention;

Figure 2 is a circuit block diagram of a data reading and writing circuit according to an embodiment of the present invention;

Figure 3A is a circuit schematic diagram of a data reading circuit according to an embodiment of the present invention;

3B is a schematic waveform diagram of a read operation of a memory device according to an embodiment of the present invention;

Figure 4 is a circuit schematic diagram of a data correction circuit according to an embodiment of the present invention;

Figure 5A is a circuit schematic diagram of a data writing circuit according to an embodiment of the present invention;

5B is a circuit schematic diagram of a control signal generating circuit of a data writing circuit according to an embodiment of the present invention;

FIG. 6A is a schematic waveform diagram of a write operation of a memory device according to an embodiment of the present invention when no error bits are found;

6B is a schematic waveform diagram of a write operation of a memory device in correcting erroneous bits according to an embodiment of the present invention;

Figure 7A is a circuit schematic diagram of a syndrome generation circuit according to an embodiment of the present invention;

7B is a circuit schematic diagram of the internal operation circuit of the syndrome generation circuit according to an embodiment of the present invention;

7C is a circuit schematic diagram of the syndrome control signal generation circuit of the syndrome generation circuit according to an embodiment of the present invention;

Figure 8 is a circuit schematic diagram of a correction data reading and writing circuit according to an embodiment of the present invention;

FIG. 9 is a circuit schematic diagram of a correction data writing circuit according to an embodiment of the present invention.

Explanation of reference signs

100: Memory device

110: Storage cell array

120: Correction data storage unit array

130: Data reading and writing circuit

140: Correction data reading and writing circuit

150: syndrome generation circuit

160: syndrome decoding circuit

170: syndrome operation circuit

210: Data reading circuit

220: Data correction circuit

230: Data writing circuit

310: Read switch

320: Precharge circuit

330: Amplification circuit

332: amplifier

410: Correction switch

420: Read bit latch

430: Correction circuit

440, 540: Output circuit

442: Latch

510, 520: Write switch

530: Write bit latch

550: Control signal generation circuit

610: Signal generation circuit

710: Internal computing circuit

720: Input circuit

730: Syndrome control signal generation circuit

810: Correction data reading circuit

820: Correction data writing circuit

AD, ADi: read data

ADiT: Read data signal

ADiN: inverted read data signal

BL: bit line

BLN: complementary bit line

CS: Correction bit signal

DE: Read enable signal

DM: Write mask signal

DWm: write mask selection signal

DWmB: Inverted write mask select signal

EiT: positive latched bit signal

EiN: Anti-latch bit signal

GND: ground voltage

LAR: read latch signal

LAWIN: Initial write latch signal

LAWm: first write latch signal

LAWmB: Inverted first write latch signal

LDWm: Second write latch signal

LDWmB: Inverted second write latch signal

LAWPT: Verify write latch signal

LAWPB: Inverted check write latch signal

MD: data

MDiT: data signal

MDiN: Inverted data signal

NAND1～NAND5: anti-AND gate

NOR1～NOR3: reverse OR gate

NS: Correction data write signal

INV, INV1～INV21: inverter

OE: output enable signal

PB: Precharge signal

PM: Correction data

PS: Correct reading signal

RWB, RWBi: data output signal

RD, RDi: read bit signal

SY: syndrome signal

SD, SDi: error decoding signal

SDE: decode control signal

TG, TG1～TG9: transmission gate

T31, T32, TP1~TP10: P-type transistors

T33, T34, T35, TN1～TN3: N-type transistors

VDD: Voltage power supply

VSS: low voltage

WE: write enable signal

WED: Write data control signal

WEDB: Inverted write data control signal

WEm: Write data selection signal

WEmB: Inverted write data selection signal

Detailed ways

FIG. 1 is a block diagram of a memory device according to an embodiment of the present invention. Referring to FIG. 1 , the memory device 100 includes a memory cell array 110 , a correction data storage cell array 120 , a data read and write circuit 130 , a correction data read and write circuit 140 and a syndrome operation circuit 170 . The syndrome operation circuit 170 includes a syndrome operation circuit 170 . A syndrome generation circuit 150 and a syndrome decoding circuit 160 . The data read and write circuit 130 is coupled to the memory cell array 110 to access the data MD of the memory cell array 110 . The correction data read-write circuit 140 is coupled to the correction data storage cell array 120 to access the correction data PM of the correction data storage cell array 120 . The correction data PM is an error checking and correction code used to check and correct the data MD, for example, it is generated by performing an ECC encoding process such as Hamming code on the data MD. The number of bits of correction data PM depends on the number of bits of data MD. In this embodiment, the size of the data MD is 64 bits, and the size of the correction data PM is set to 7 bits. However, the present invention does not limit the sizes of the data MD and the correction data PM.

The syndrome arithmetic circuit 170 operates based on the data MD received from the data read-write circuit 130 (the data read-write circuit 130 reads the data MD and then outputs the read bit signal RD) and the correction data PM (correction data PM) received from the correction data read-write circuit 140. The data read and write circuit 140 reads the correction data PM and then outputs a correction read signal PS) to generate an error decoding signal SD. In the same read cycle of reading the data MD, the data read and write circuit 130 corrects the error signal SD according to the error decoding signal. Error bits in the data MD and output correct data (ie, data output signal RWB) and correction bit signal CS. The data read and write circuit 130 will write the corrected data back to the memory cell array 110, and the syndrome operation circuit 170 also outputs the correction data write signal NS to the correction data read and write circuit 140 according to the correction bit signal CS to update the correction data storage. Correction data PM in cell array 120 .

In other words, in this embodiment, after reading the data MD and the correction data PM, the data can be checked through the syndrome encoding (Syndrome encoding) and syndrome decoding (Syndrome decoding) of the syndrome operation circuit 170 Are there any erroneous bits in the MD? If there are erroneous bits, the data read and write circuit 130 can immediately correct the erroneous bits according to the error decoding signal SD to output the correct data output signal RWB in the same read cycle, and can also output the correction bit signal CS to the syndrome. The arithmetic circuit 170 causes the correction data reading and writing circuit 140 to update the correction data PM. In particular, between reading the data MD and outputting the correct data output signal RWB, the memory device 100 does not need to select the memory cells of the memory cell array 110 again, and can complete the above actions in the same read cycle, and Correction data PM can also be updated.

The circuit structure and implementation of this embodiment will be further described below. FIG. 2 is a circuit block diagram of a data reading and writing circuit according to an embodiment of the present invention. Referring to FIG. 2 , the data reading and writing circuit 130 includes a data reading circuit 210 , a data correction circuit 220 and a data writing circuit 230 . The data reading circuit 210 is coupled to the memory cell array 110 and used to read the data MD from the memory cell array 110 to generate the read data AD and the corresponding read bit signal RD. The data correction circuit 220 is coupled to the syndrome decoding circuit 160 of the data reading circuit 210 and the syndrome operation circuit 170 for latching the read data AD in the read cycle and correcting the read data according to the error decoding signal SD. The erroneous bits of AD are used to generate correct data output signal RWB and correction bit signal CS, where the data output signal RWB is the output result after the data read and write circuit 130 reads and corrects the data MD. The data writing circuit 230 is coupled to the data correction circuit 220 and the memory cell array 110, and is used to use the correction bit signal CS to replace the data output signal RWB corresponding to the error bit to write the correct data MD back to the memory cell array 110.

Referring again to FIG. 1 , the syndrome operation circuit 170 includes a syndrome generation circuit 150 and a syndrome decoding circuit 160 . The syndrome generation circuit 150 is coupled to the data reading and writing circuit 130 and the correction data reading and writing circuit 140, and selectively receives the output signal of the data reading circuit 210 or the data correction circuit 220 according to the reading operation or the writing operation to generate correction data writing. Signal NS. More specifically, when the data read-write circuit 130 performs a read operation, the syndrome generation circuit 150 generates a correction data write signal NS according to the read bit signal RD, and when the data read-write circuit 130 performs a write operation, the syndrome generation circuit 150 generates the correction data write signal NS. The syndrome generation circuit 150 generates the correction data write signal NS based on the correction bit signal CS or the data output signal RWB.

The syndrome generation circuit 150 compares the correction data writing signal NS with the corresponding correction data PM (the correction data reading and writing circuit 140 reads the correction data PM to provide the correction reading signal PS to the syndrome generation circuit 150) to generate the syndrome. Sub-signal SY. The syndrome decoding circuit 160 is coupled to the syndrome generation circuit 150 to decode the syndrome signal SY to generate an error decoding signal SD. The data reading and writing circuit 130 corrects the error bits in the data MD according to the error decoding signal SD.

Next, the specific implementation of the data reading and writing circuit 130 will be described. FIG. 3A is a circuit schematic diagram of a data reading circuit according to an embodiment of the present invention. FIG. 3B is a waveform schematic diagram of a read operation of a memory device according to an embodiment of the present invention. FIG. 4 is a circuit schematic diagram of a data correction circuit according to an embodiment of the present invention. FIG. 5A is a circuit schematic diagram of a data writing circuit according to an embodiment of the present invention. FIG. 5B is a data writing circuit according to an embodiment of the present invention. The circuit schematic diagram of the control signal generating circuit that enters the circuit. Please refer to FIGS. 3A to 5B in conjunction with FIGS. 1 and 2 to specifically describe the implementation details of the data read and write circuit 130 .

In FIG. 3A , the data reading circuit 210 includes a reading switch 310 , a precharge circuit 320 and an amplifying circuit 330 . The input terminal of the read switch 310 receives the data MD from the memory cell array 110 and is controlled to be turned on or off according to the read enable signal DE. The precharge circuit 320 is coupled to the input terminal of the read switch 310 and is controlled by the precharge signal PB to perform a precharge operation on the input terminal of the read switch 310 . The input terminal of the amplifier circuit 330 is coupled to the output terminal of the read switch 310 and is controlled by the read enable signal DE to generate read data AD and generate a corresponding read bit signal RD.

Specifically, the sense amplifier in the memory cell array 110 outputs the data MD stored in the memory cells in the form of a differential signal. Therefore, the data MD will include a differential signal of the data signal MDiT and the inverted data signal MDiN. , where the data MD takes 64 bits as an example. In this specification, MDi represents one of the bits of the data MD, and i is an integer from 0 to 63 (i=0,1,2,...,63), such as MD0, MD1, …, MD63. Similarly, the read data AD also includes a differential signal of the read data signal ADiT and the inverted read data signal ADiN. i in this specification refers to the corresponding bit. For example, the read bit signal RDi, the data output signal RWBi, and the correction bit signal CSi represent the corresponding bits in the read bit signal RD, the data output signal RWB, and the correction bit signal CS. Please use this analogy.

In the read switch 310, the transfer gate TG1 is coupled to the bit line BL to receive the data signal MDiT, the transfer gate TG2 is coupled to the complementary bit line BLN to receive the inverted data signal MDiN, and both the transfer gate TG1 and the transfer gate TG2 are controlled by Read the enable signal DE. The input terminal of the inverter INV1 in FIG. 3A receives the read enable signal DE, and its output terminal is commonly coupled to one of the control terminals of the transmission gate TG1 and the transmission gate TG2 (for example, the N-type of the transmission gate TG1 and the transmission gate TG2 control terminal of the transistor). The input terminal of the inverter INV2 is coupled to the output terminal of the inverter INV1, and its output terminal is commonly coupled to the other control terminal of the transmission gate TG1 and the transmission gate TG2 (for example, the P-type transistor in the transmission gate TG1 and the transmission gate TG2 Control terminal).

In the precharge circuit 320, the inverter INV3 receives the precharge signal PB. The P-type transistor TP1 has a first terminal coupled to the power supply voltage VDD, a control terminal coupled to the output terminal of the inverter INV3, and a second terminal coupled to the bit line BL. The P-type transistor TP2 has a first terminal coupled to the power supply voltage VDD, a control terminal coupled to the output terminal of the inverter INV3, and a second terminal coupled to the complementary bit line BLN. The P-type transistor TP3 is coupled between the second terminal of the P-type transistor TP1 and the second terminal of the P-type transistor TP2, and its control terminal is coupled to the output terminal of the inverter INV3.

In the amplifier circuit 330, the amplifier 332 is coupled to the read switch 310 to receive the data signal MDiT and the inverted data signal MDiN, and correspondingly output the read data signal ADiT and the inverted read data signal ADiN. The inverter INV4 receives the inverted read data signal ADiN to output the read bit signal RDi.

In this embodiment, the amplifier 332 includes P-type transistors T31 to T32 and N-type transistors T33 to T35. The P-type transistor T31 and the N-type transistor T33 are connected in series between the voltage power supply VDD and the first terminal of the N-type transistor T35. The P-type transistor T32 and the N-type transistor T34 are also connected in series between the voltage power supply VDD and the first terminal of the N-type transistor T35. Between one end, the control terminals of the P-type transistor T31 and the N-type transistor T33 are commonly coupled to the first terminal of the N-type transistor T34, and the control terminals of the P-type transistor T32 and the N-type transistor T34 are commonly coupled to the first terminal of the N-type transistor T33. First end. The second terminal of the N-type transistor T35 is coupled to the ground voltage GND, and its control terminal is coupled to the read enable signal DE.

In FIG. 3B , before the read operation, the precharge signal PB turns on the read switch 310 to perform a precharge operation on the bit line BL and the complementary bit line BLN. When the read operation is to be started, the precharge signal PB turns off the read switch 310 to end the precharge operation. At the same time, the selection signal CSL used to select the memory cells of the memory cell array 110 will change from a low logic level (Low) to a high logic level (High) to read the data MD of the selected memory cell. Then, the read enable signal DE is switched to a high logic level (High) to turn on the read switch 310 and the enable amplifier 332 to amplify the data signal MDiT and the inverted data signal MDiN to output the read data signal ADiT, the inverted read signal Get the data signal ADiN and the read bit signal RDi. The low voltage VSS in Figure 3B takes the ground voltage GND as an example.

Referring to FIG. 4 , the data correction circuit 220 includes a correction switch 410 , a read bit latch 420 , a correction circuit 430 and an output circuit 440 . The input end of the correction switch 410 receives the read data ADi from the data read circuit 210 and is controlled to be turned on or off by the read latch signal LAR. The read bit latch 420 is coupled to the correction switch 410 for latching the read data ADi. The correction circuit 430 is coupled to the read bit latch 420 and receives the corresponding error decoding signal SDi, so as to correct the bits stored in the read bit latch 420 according to the error decoding signal SDi. The output circuit 440 is coupled to the correction circuit 430 and the read bit latch 420, and is controlled by the output enable signal OE to output the bits stored in the read bit latch 420 as the data output signal RWBi.

In the correction switch 410 of FIG. 4 , the transmission gate TG3 receives the read data signal ADiT from the data reading circuit 210 , the transmission gate TG4 receives the inverted reading data signal ADiN from the data reading circuit 210 , and the transmission gate TG3 and the transmission gate TG4 is controlled by the read latch signal LAR. The input terminal of the inverter INV5 receives the read latch signal LAR, and its output terminal is commonly coupled to one of the control terminals of the transmission gate TG3 and the transmission gate TG4 to provide an inverted signal of the read latch signal LAR.

The read bit latch 420 includes an inverter INV6 and an inverter INV7. The input terminal of the inverter INV6 is coupled to the output terminal of the inverter INV7 and receives the read data signal ADiT through the transmission gate TG3. The input terminal of the inverter INV7 is coupled to the output terminal of the inverter INV6 and receives the inverted read data signal ADiN through the transmission gate TG4.

In the correction circuit 430, the inverter INV8 receives the error decoding signal SDi, and the inverter INV9 is coupled to the output terminal of the inverter INV6 to output the correction bit signal CSi. The first terminal of the P-type transistor TP4 is coupled to the power supply voltage VDD, the second terminal of the P-type transistor TP4 is coupled to the first terminal of the P-type transistor TP5, and the control terminal of the P-type transistor TP4 is coupled to the output terminal of the inverter INV8. The second terminal of the P-type transistor TP5 is coupled to the input terminal of the inverter INV6, and its control terminal receives the read data signal ADiT. The first terminal of the P-type transistor TP6 is also coupled to the power supply voltage VDD, the second terminal is coupled to the first terminal of the P-type transistor TP7, and the control terminal is coupled to the output terminal of the inverter INV8. The second terminal of the P-type transistor TP7 is coupled to the output terminal of the inverter INV6, and its control terminal receives the inverted read data signal ADiN.

In the output circuit 440, the input terminal of the inverter INV10 is coupled to the output enable signal OE. The first input terminal of the NAND gate NAND1 is coupled to the second terminal of the P-type transistor TP5, and its second input terminal receives the output enable signal OE. The first input terminal of the inverter NOR1 is coupled to the second terminal of the P-type transistor TP5, and the second input terminal is coupled to the output terminal of the inverter INV10. The first terminal of the P-type transistor TP8 is coupled to the power supply voltage VDD, the control terminal is coupled to the output terminal of the NAND gate NAND1, and the first terminal of the N-type transistor TN1 is coupled to the second terminal of the P-type transistor TP8 and provides the corrected The control terminal of the data output signal RWBi is coupled to the output terminal of the inverse-OR gate NOR1, and its second terminal is coupled to the ground voltage GND. The output circuit 440 may further include a latch 442 coupled to the first terminal of the N-type transistor TN1. The circuit structure of the latch 442 is the same as that of the read bit latch 420, and is formed by interconnecting two inverters INV.

Please refer to FIG. 3B again. When the read latch signal LAR switches to a high logic level, the read bit latch 420 receives the read data ADi to latch its bit value, and generates the corresponding positive latch bit signal EiT and the reverse latch. Store the bit signal EiN. In FIG. 3B , during the high logic level period of the read latch signal LAR, the positive latching bit signal EiT changes to a low logic level, and the inverse latching bit signal EiN changes to a high logic level. After the read latch signal LAR switches to a low logic level, if the i-th bit of the data MD is an error bit, the error decoding signal SDi from the syndrome decoding circuit 160 switches to a high logic level. In the same read cycle, the correction circuit 430 inverts the erroneous bit value latched by the read bit latch 420 according to the error decoding signal SDi, so the forward latched bit signal EiT and the inverse latched bit signal EiN are inverted. to correct the error. Finally, the output circuit 440 outputs the correct data output signal RWBi according to the output enable signal OE.

Referring to FIG. 5A , the data writing circuit 230 includes an inverter INV11, a writing switch 510, a writing switch 520, a writing bit latch 530 and an output circuit 540. The input terminal of the inverter INV11 receives the corresponding data output signal RWBi. The input terminal of the write switch 510 is coupled to the output terminal of the inverter INV11 and is controlled to be turned on or off by the first write latch signal LAWm. The input end of the write switch 520 receives the corresponding correction bit signal CSi and is controlled by the second write latch signal LDWm to be turned on or off. Here, m is an integer from 0 to 7, indicating the corresponding mask bit. The write bit latch 530 is coupled to the output terminal of the write switch 510 and the write switch 520 , and the output circuit 540 is coupled to the output terminal of the write switch 520 and the write bit latch 530 . The output circuit 540 is controlled by the write enable signal WE and writes the data output signal RWBi or the correction bit signal CSi into the memory cell array 110 .

Here, the data signal MDiT and the inverted data signal MDiN output by the output circuit 540 can be respectively transmitted back to the bit line and the complementary bit line of the memory cell array 110 to rewrite the data MDi.

In FIG. 5A , the write switch 510 is implemented as a transfer gate TG5 , and the write switch 520 is implemented as a transfer gate TG6 . The two control terminals of the transfer gate TG5 respectively receive the corresponding first write latch signal LAWm and the inverted signal of the first write latch signal LAWm (referred to as the inverted first write latch signal) LAWmB. The transfer gate TG6 The two control terminals respectively receive the second write latch signal LDWm and the inverted signal of the second write latch signal LDWm (referred to as the inverted second write latch signal) LDWmB.

The write bit latch 530 includes an inverter INV12 and an inverter INV13. The input terminal of the inverter INV12 is coupled to the output terminal of the inverter INV13. The input terminal of the inverter INV13 is coupled to the output terminal of the inverter INV12. The input terminal of the inverter INV12 is jointly coupled to the transmission gate TG5 and the transmission gate. Gate the output of TG6.

In the output circuit 540, the inverter INV14 is connected in series with the inverter INV15, and the inverter INV14 receives the write enable signal WE. The first input terminal of the NAND gate NAND2 is coupled to the output terminal of the inverter INV12, the second input terminal of the NAND gate NAND2 is coupled to the output terminal of the inverter INV15, and the first input terminal of the NOR gate NOR2 is coupled to the output terminal of the inverter INV12. The output terminal has a second input terminal coupled to the output terminal of the inverter INV14. The first terminal of the P-type transistor TP9 is coupled to the power supply voltage VDD, the control terminal is coupled to the output terminal of the NAND gate NAND2, and the first terminal of the N-type transistor TN2 is coupled to the second terminal of the P-type transistor TP9 and provides the corresponding The control terminal of the data signal MDiT is coupled to the output terminal of the inverse-OR gate NOR2, and its second terminal is coupled to the ground voltage GND. The first input terminal of the NAND gate NAND3 is coupled to the output terminal of the inverter INV13, and the second input terminal of the NAND gate NAND3 is coupled to the output terminal of the inverter INV15. The first input terminal of the NOR gate NOR3 is coupled to the output terminal of the inverter INV13, and the second input terminal of the NOR gate NOR3 is coupled to the output terminal of the inverter INV14. The first terminal of the P-type transistor TP10 is coupled to the power supply voltage VDD, the control terminal is coupled to the output terminal of the NAND gate NAND3, and the first terminal of the N-type transistor TN3 is coupled to the second terminal of the P-type transistor TP10 and provides the corresponding The control terminal of the inverted data signal MDiN is coupled to the output terminal of the inverse-OR gate NOR3, and its second terminal is coupled to the ground voltage GND.

Referring to FIG. 5B, the data writing circuit 230 also includes a control signal generating circuit 550. The control signal generating circuit 550 generates a first write latch signal LAWm and a second write latch signal LAWm according to the initial write latch signal LAW and the write mask signal DM. Write latch signal LDWm. In this embodiment, the write mask signal DM is an 8-bit signal, so the write mask signal DMm represents a signal corresponding to the m-th bit, and m is an integer from 0 to 7. The control signal generation circuit 550 provides the verification write latch signal LAWPT and the inverted verification write latch signal LAWPB to the correction data read and write circuit 140, and provides the corresponding first write latch signal LAWm and the second write The latch signal LDWm and its inverted signal are sent to the data writing circuit 230 .

The control signal generating circuit 550 includes an inverter INV16, an inverter INV17, an inverter INV18 and a signal generating circuit 610. The inverter INV16 and the inverter INV17 are connected in series and the input end of the inverter INV16 receives the initial write latch signal LAW, and the inverter INV17 outputs the verification write latch signal LAWPT to the correction data read and write circuit 140, where The inverter INV18 receives the initial write latch signal LAW to output the inverted verification write latch signal LAWPB.

It should be added that when performing a read operation, the write enable signal WE and the initial write latch signal LAW will remain at a low logic level.

In the signal generation circuit 610 of FIG. 5B , the output terminal of the inverter INV19 receives the corresponding write mask signal DMm. The first input terminal of the NAND gate NAND4 receives the initial write latch signal LAW, its second input terminal is coupled to the output terminal of the inverter INV19, and its output terminal outputs the corresponding inverted first write latch signal LAWmB. The input terminal of the inverter INV20 is coupled to the output terminal of the inverter NAND4 to output the corresponding first write latch signal LAWm. The first input terminal of the NAND gate NAND5 receives the initial write latch signal LAW, the second input terminal receives the corresponding write mask signal DMm, and the output terminal outputs the corresponding inverted second write latch signal LDWmB. The input terminal of the inverter INV21 is coupled to the output terminal of the inverter NAND5 to output the corresponding second write latch signal LDWm.

6A is a schematic waveform diagram of a write operation of a memory device according to an embodiment of the present invention when no error bits are found. FIG. 6B is a schematic diagram of a write operation of a memory device according to an embodiment of the present invention when error bits are corrected. Waveform diagram. Please refer to FIG. 6A and FIG. 6B together with the above embodiment.

In FIG. 6A , when the memory device 100 is to write data MD and the bits to be written do not need to be corrected, the enabling time (eg, the time remaining at a high logic level) of the selection signal CSL used to select the memory cell is called is the normal writing time. During the normal writing time, the correction bit signal CS and the writing mask signal DM will always maintain a low logic level, the writing switch 510 is turned on and the writing switch 520 is turned off, and the data writing circuit 230 selects to output the data signal. RWBi is written to the memory cell array 110 .

In FIG. 6B , after the memory device 100 finds an erroneous bit in the data MD and the data writing circuit 230 wants to write back correct data, the enabling time of the selection signal CSL is called the correction writing time. During the correction writing time, after the read latch signal LAR is switched to a low logic level, the logic level of the error decoding signal SDi corresponding to the error bit position transitions to a high level. Correspondingly, the data correction circuit 220 outputs The correction bit signal CSi also switches to a high logic level. It should be added that the syndrome generation circuit 150 will also correspondingly output the correction data writing signal NS to the correction data reading and writing circuit 140 to update the correction data PM.

Then the data writing circuit 230 performs a writing operation, the corresponding first writing latch signal LAWm will turn off the writing switch 510 and the corresponding second writing latch signal LDWm will turn on the writing switch 520 to allow the correction bit signal CSi is input to the output circuit 540 instead of the data output signal RWBi to write the correct bit value during the enable time of the write enable signal WE.

In short, when the bit to be written is originally correct, the data writing circuit 230 writes the data output signal RWBi into the memory cell array 110; when the bit to be written is an erroneous bit position, the data writing circuit 230 The correction bit signal CSi is written into the memory cell array 110 .

Specifically, in this embodiment, the enabling time of the selection signal CSL can be changed, and the correction writing time will be greater than the normal writing time. When the memory device 100 detects an erroneous bit, by extending the enabling time of the selection signal CSL, the data read and write circuit 130 and the correction data read and write circuit 140 can write the correct data back to the memory unit within the same period of correction. array 110 and update correction data PM. In other words, the selection signal CSL only needs to be enabled once to complete the checking, correction and updating actions.

Next, the details of the circuit architecture of the syndrome generation circuit 150 will be described. FIG. 7A is a schematic circuit diagram of a syndrome generating circuit according to an embodiment of the present invention. FIG. 7B is a circuit schematic diagram of an internal operation circuit of the syndrome generating circuit according to an embodiment of the present invention. FIG. 7C is a schematic circuit diagram of a syndrome generating circuit according to an embodiment of the present invention. A circuit schematic diagram of a syndrome control signal generation circuit of a syndrome generation circuit according to an embodiment of the invention.

Please refer to FIG. 7A first. The syndrome generation circuit 150 includes an internal operation circuit 710 and a plurality of exclusive OR gates XOR2. The internal operation circuit 710 includes a plurality of transmission gates TG (transmission gates TG7 to TG9 in FIG. 7B) and Multiple mutually exclusive OR gates XOR1.

In FIG. 7B , the internal operation circuit 710 controls a plurality of transfer gates TG to selectively provide a data output signal RWB, a correction bit signal CS, or a read bit signal RD to a plurality of mutually exclusive OR gates XOR1 to output a correction data write signal NS. Specifically, the internal operation circuit 710 has a plurality of input circuits 720 . In addition to receiving the corresponding data output signal RWBi, each input circuit 720 may also receive the corresponding read bit signal RDi from the data reading circuit 210 and the corresponding correction bit signal CSi from the data correction circuit 220 . The internal operation circuit 710 controls a plurality of transfer gates TG7 to TG9 in the input circuit 720 to selectively input one of the read bit signal RD, the data output signal RWB, and the correction bit signal CS to the corresponding mutually exclusive OR gate XOR1.

Specifically, the transfer gate TG7 receives the corresponding read bit signal RDi and is controlled by the write data control signal WED and the inverted signal WEDB of the write data control signal WED. The transfer gate TG8 receives the data output signal RWBi and is controlled by The transmission gate TG9 receives the correction bit signal CSi and is controlled by the write mask selection signal DWm and the inversion signal of the write mask selection signal DWm. DWmB.

When the memory device 100 performs a read operation, the input circuit 720 selects to receive the read bit signal RDi, turns on the transmission gate TG7 and closes the transmission gate TG8 and TG9; when the memory device 100 performs a write operation, the input circuit 720 closes Transmission gate TG7, and turns on transmission gate TG8 or transmission gate TG9 according to the write mask signal DM to select to receive the data output signal RWBi or the correction bit signal CSi.

After multi-stage mutually exclusive OR gate The input signal NSj represents the signal corresponding to the j-th bit in the correction data write signal NS.

In FIG. 7A , a plurality of mutually exclusive OR gates XOR2 receive corresponding correction data writing signals NSj from the internal operation circuit 710 and corresponding correction reading signals PSj from the correction data reading and writing circuit 140 . The syndrome generation circuit 150 compares the correction read signal PS and the correction data write signal NS to output a syndrome signal SY. The syndrome decoding circuit 160 receives the syndrome signal SY and the decoding control signal SDE and performs a decoding operation on the syndrome signal SY to output an error decoding signal SD to the data correction circuit 220 of the data reading and writing circuit 130 .

The syndrome generation circuit 150 also includes a syndrome control signal generation circuit 730 for generating the control signal of the transmission gate TG. The circuit structure of the syndrome control signal generation circuit 730 in FIG. 7C is similar to the control signal generation circuit 550 in FIG. 5B , so the details of the operation of the syndrome control signal generation circuit 730 will not be described again.

Next, the specific circuit structure of the correction data reading and writing circuit 140 will be described. FIG. 8 is a circuit schematic diagram of a correction data reading and writing circuit according to an embodiment of the present invention. FIG. 9 is a circuit schematic diagram of a correction data writing circuit according to an embodiment of the present invention.

Referring to FIG. 8 , the correction data reading and writing circuit 140 includes a correction data reading circuit 810 and a correction data writing circuit 820 . The correction data reading circuit 810 is coupled to the correction data storage cell array 120 and the syndrome operation circuit 170, and is used to read the correction data PM from the correction data storage cell array 120 to output the correction read signal PS to the syndrome operation circuit 170. The syndrome generating circuit 150. The correction data writing circuit 820 is coupled to the correction data storage cell array 120 and the syndrome generation circuit 150 of the syndrome operation circuit 170 , and is used to write the corrected correction data PM into the correction data storage cell array 120 .

When the memory device 100 performs a read operation, the correction data read circuit 810 may read the correction data PM from the correction data storage cell array 120 to output the correction read signal PS to the syndrome generation circuit 150 . The syndrome generation circuit 150 checks whether the read bit signal RD has an erroneous bit based on the corrected read signal PS. If there is an error bit, the corresponding error decoding signal SDi will change the logic level. In this embodiment, if the i-th bit of the data MD is incorrect, the error decoding signal SDi will change to a high logic level, as shown in FIG. 3B.

The circuit details of the correction data reading circuit 810 can be referred to FIG. 3A. Those skilled in the art can obtain sufficient suggestions, teachings and implementation methods from the data reading circuit 210, and will not be described again here.

Figure 9 shows the circuit details of the correction data writing circuit 820. Its circuit architecture is similar to the data writing circuit 230 of Figure 5A. Those skilled in the art can obtain sufficient suggestions, teachings and implementation methods from the data writing circuit 230. This will not be described again.

Please refer to FIG. 6B again. When the syndrome generation circuit 150 detects that the read bit signal RD has an erroneous bit, the data writing circuit 230 performs error correction on the read bit signal RD. The syndrome generation circuit 150 will correct the error according to the recorded error. The correction bit signal CS of the bit position outputs a new correction data write signal NS. The correction data writing circuit 820 writes the new correction data writing signal NS to the correction data storage cell array 120 to update the correction data PM. The correction data PM in FIG. 9 includes a differential signal composed of the correction data signal PMjT and the inverted correction data signal PMjN. j is an integer from 0 to 6, representing the corresponding check bit.

In summary, the memory device of the present invention can read data from the memory cell array and check it in one read cycle. When an erroneous bit is found in the data, the memory device of the present invention can read data in the same read cycle. Errors are corrected instantly during the cycle and correct data is output. In addition, the memory device of the present invention can also output correction bit signals to the data writing circuit and the syndrome generating circuit at the same time. By extending the enable period of the selection signal, the data writing circuit can write the corrected data back to the memory cell array and the syndrome generating circuit can provide a new correction data writing signal to the correction data writing circuit to update the correction data. In this way, the selection signal only needs to provide an enabling period to the memory unit to be written to complete the correction and update of the data, achieving the effect of instant checking and correcting errors.

Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Any person skilled in the art can make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the claims.

Claims (15)

1. A memory device, characterized in that it includes: A data read and write circuit, coupled to the memory cell array, for accessing data in the memory cell array; A correction data reading and writing circuit is coupled to the correction data storage unit array and used to access the correction data of the correction data storage unit array; and a syndrome operation circuit configured to generate an error decoding signal based on the data received from the data read-write circuit and the correction data received from the correction data read-write circuit, Wherein, in the same reading cycle of reading the data, the data reading and writing circuit corrects the error bits in the data according to the error decoding signal and outputs the correct data and correction bit signal, wherein the The data read-write circuit writes the corrected data back to the memory cell array, wherein the syndrome operation circuit also outputs a correction data write signal to the correction data read-write circuit according to the correction bit signal to updating the correction data in the correction data storage unit array, The data reading and writing circuit includes: A data reading circuit, coupled to the memory cell array, is used to read the data from the memory cell array to generate read data and corresponding read bit signals; a data correction circuit, coupled to the data reading circuit and the syndrome operation circuit, for latching the read data in the read cycle and correcting the read according to the error decoding signal Error bits of data to generate a data output signal and the correction bit signal, wherein the data output signal is the output result of the data read and write circuit after reading and correcting the data; and a data writing circuit, coupled to the data correction circuit and the memory cell array, for replacing the data output signal corresponding to the error bit with the correction bit signal to write the correct data back to the memory cell array, The data correction circuit includes: A correction switch, the input end of which receives the read data from the data read circuit and is controlled to be turned on or off by a read latch signal; a read bit latch, coupled to the correction switch, for latching the read data; a correction circuit coupled to the read bit latch and receiving the error decoding signal, for correcting the bits stored in the read bit latch according to the error decoding signal; and A first output circuit, coupled to the correction circuit and the read bit latch, is controlled by an output enable signal to output the bits stored in the read bit latch as the data output signal. 2. The memory device according to claim 1, wherein when the corrected data is to be written into the memory cell array, the enable time of the selection signal used to select the memory cell is called correction writing. input time, and when the data of the error bit is not found to be written into the memory cell array, the enable time of the selection signal is called the normal write time, wherein the correction write time is greater than The normal writing time. 3. The memory device of claim 1, wherein the data read circuit includes: A read switch, the input end of which receives the data from the memory cell array and is controlled to be turned on or off by a read enable signal; A precharge circuit, coupled to the input end of the read switch, is controlled by a precharge signal to perform a precharge action on the input end of the read switch; and An amplification circuit, whose input terminal is coupled to the output terminal of the read switch, is controlled by the read enable signal to generate the read data and generate the corresponding read bit signal. 4. The memory device of claim 3, wherein The read switch includes: A first transmission gate and a second transmission gate, wherein the first transmission gate is coupled to a bit line to receive a data signal, the second transmission gate is coupled to a complementary bit line to receive an inverted data signal, and the first transmission gate Both the gate and the second transmission gate are controlled by the read enable signal, wherein the data is a differential signal including the data signal and the inverted data signal; and A first inverter and a second inverter, wherein an input terminal of the first inverter receives the read enable signal, and an output terminal thereof is commonly coupled to the first transmission gate and the second transmission gate. One of the control terminals of the gate, the input terminal of the second inverter is coupled to the output terminal of the first inverter, and its output terminal is jointly coupled to the first transmission gate and the second transmission gate. the other control end; The precharge circuit includes: A third inverter receives the precharge signal; A first P-type transistor has a first terminal coupled to the power supply voltage, a control terminal coupled to the output terminal of the third inverter, and a second terminal coupled to the bit line; A second P-type transistor has a first terminal coupled to the power supply voltage, a control terminal coupled to the output terminal of the third inverter, and a second terminal coupled to the complementary bit line; and A third P-type transistor is coupled between the second terminal of the first P-type transistor and the second terminal of the second P-type transistor, and its control terminal is coupled to the output terminal of the third inverter. ;as well as The amplification circuit includes: An amplifier coupled to the read switch to receive the data signal and the inverted data signal, and correspondingly output the read data signal and the inverted read data signal, wherein the read data includes the read data signal. Obtain the differential signal between the data signal and the inverted read data signal; and A fourth inverter receives the inverted read data signal to output the read bit signal. 5. The memory device of claim 1, wherein The correction switch includes: A third transmission gate and a fourth transmission gate, wherein the third transmission gate receives a read data signal from the data reading circuit, and the fourth transmission gate receives an inverted read data signal from the data reading circuit. , and both the third transmission gate and the fourth transmission gate are controlled by the read latch signal, wherein the read data includes the read data signal and the inverted read data signal. differential signal; and a fifth inverter, an input end of which receives the read latch signal, and an output end of which is commonly coupled to one of the control ends of the third transmission gate and the fourth transmission gate; and The read bit latch includes: A sixth inverter and a seventh inverter, wherein the input terminal of the sixth inverter is coupled to the output terminal of the seventh inverter and receives the read data signal through the third transmission gate , and the input terminal of the seventh inverter is coupled to the output terminal of the sixth inverter and receives the inverted read data signal through the fourth transmission gate. 6. The memory device of claim 5, wherein the correction circuit includes: An eighth inverter receives the error decoding signal; a ninth inverter, coupled to the output end of the sixth inverter to output the correction bit signal; The fourth P-type transistor and the fifth P-type transistor, wherein the first terminal of the fourth P-type transistor is coupled to the power supply voltage, the second terminal of the fourth P-type transistor is coupled to the first terminal of the fifth P-type transistor, and the control terminal of the fourth P-type transistor is coupled to the power supply voltage. The output terminal is coupled to the eighth inverter, and the second terminal of the fifth P-type transistor is coupled to the input terminal of the sixth inverter, and its control terminal receives the read data signal; and The sixth P-type transistor and the seventh P-type transistor, wherein the first terminal of the sixth P-type transistor is coupled to the power supply voltage, and the second terminal thereof is coupled to the first terminal of the seventh P-type transistor. The control terminal is coupled to the output terminal of the eighth inverter, and the second terminal of the seventh P-type transistor is coupled to the output terminal of the sixth inverter, and its control terminal receives the inverted reading data signal. 7. The memory device of claim 6, wherein the first output circuit includes: A tenth inverter, the input end of which is coupled to the output enable signal; A first NAND gate, the first input terminal of which is coupled to the second terminal of the fifth P-type transistor, and the second input terminal of which receives the output enable signal; A first NOR gate, the first input terminal of which is coupled to the second terminal of the fifth P-type transistor, and the second input terminal of which is coupled to the output terminal of the tenth inverter; The eighth P-type transistor has a first terminal coupled to the power supply voltage and a control terminal coupled to the output terminal of the first NAND gate; and A first N-type transistor has a first terminal coupled to the second terminal of the eighth P-type transistor and provides the corrected data output signal, and a control terminal thereof is coupled to the output terminal of the first inverter gate, The second end is coupled to a ground voltage. 8. The memory device of claim 1, wherein the data writing circuit includes: An eleventh inverter, the input end of which receives the corresponding data output signal; A first write switch, the input terminal of which is coupled to the output terminal of the eleventh inverter, and is controlled to be turned on or off by the first write latch signal; a second write switch, the input end of which receives the corresponding correction bit signal and is controlled by the second write latch signal to be turned on or off; a write bit latch coupled to the output end of the first write switch and the output end of the second write switch; and A second output circuit, coupled to the output end of the second write switch and the write bit latch, is controlled by a write enable signal and writes the data output signal or the correction bit signal. the memory cell array. 9. The memory device of claim 8, wherein The first write switch is a fifth transfer gate, and the second write switch is a sixth transfer gate; and The write bit latch includes: The twelfth inverter and the thirteenth inverter, wherein the input terminal of the twelfth inverter is coupled to the output terminal of the thirteenth inverter, and the input terminal of the thirteenth inverter The terminal is coupled to the output terminal of the twelfth inverter, wherein the input terminal of the twelfth inverter is commonly coupled to the output terminals of the fifth transmission gate and the sixth transmission gate. 10. The memory device of claim 9, wherein the second output circuit includes: A fourteenth inverter and a fifteenth inverter, the fourteenth inverter is connected in series with the fifteenth inverter, and the fourteenth inverter receives the write enable signal ; a second NAND gate, a first input terminal of which is coupled to the output terminal of the twelfth inverter, and a second input terminal of which is coupled to the output terminal of the fifteenth inverter; a second NOR gate, the first input terminal of which is coupled to the output terminal of the twelfth inverter, and the second input terminal of which is coupled to the output terminal of the fourteenth inverter; The ninth P-type transistor has a first terminal coupled to the power supply voltage and a control terminal coupled to the output terminal of the second NAND gate; The second N-type transistor has a first terminal coupled to the second terminal of the ninth P-type transistor and provides a corresponding data signal, a control terminal coupled to the output terminal of the second inverter gate, and a second terminal Coupled to ground voltage; A third NAND gate has a first input terminal coupled to the output terminal of the thirteenth inverter and a second input terminal coupled to the output terminal of the fifteenth inverter; A third NOR gate has a first input terminal coupled to the output terminal of the thirteenth inverter and a second input terminal coupled to the output terminal of the fourteenth inverter; The tenth P-type transistor has a first terminal coupled to the power supply voltage and a control terminal coupled to the output terminal of the third NAND gate; and The first terminal of the third N-type transistor is coupled to the second terminal of the tenth P-type transistor and provides a corresponding inverted data signal. The control terminal is coupled to the output terminal of the third inverse-OR gate, and its first terminal is coupled to the second terminal of the tenth P-type transistor. Two ends are coupled to the ground voltage, wherein the data is a differential signal including the data signal and the inverted data signal. 11. The memory device according to claim 10, wherein the data writing circuit further comprises a control signal generating circuit, the control signal generating circuit generates the control signal according to the initial writing latch signal and the writing mask signal. The first write latch signal and the second write latch signal include: The sixteenth inverter, the seventeenth inverter and the eighteenth inverter, wherein the sixteenth inverter and the seventeenth inverter are connected in series and the sixteenth inverter The input terminal receives the initial write latch signal, the seventeenth inverter outputs the verification write latch signal to the correction data read and write circuit, wherein the eighteenth inverter receives the Initial write latch signal to output an inverted verification write latch signal to the correction data read and write circuit; and Signal generation circuit, including: A nineteenth inverter, the output end of which receives the corresponding write mask signal; The fourth NAND gate has a first input terminal that receives the initial write latch signal, a second input terminal that is coupled to the output terminal of the nineteenth inverter, and an output terminal that outputs the corresponding first Write the inverted signal of the latch signal; A twentieth inverter, the input terminal of which is coupled to the output terminal of the fourth NAND gate to output the corresponding first write latch signal; The fifth NAND gate has a first input terminal that receives the initial write latch signal, a second input terminal that receives the corresponding write mask signal, and an output terminal that outputs the corresponding second write latch signal. the inverted signal of the stored signal; and The input terminal of the twenty-first inverter is coupled to the output terminal of the fifth NAND gate to output the corresponding second write latch signal. 12. The memory device according to claim 1, wherein the syndrome operation circuit includes: A syndrome generation circuit is coupled to the data reading and writing circuit and the correction data reading and writing circuit, and selectively receives the output signal of the data reading circuit or the data correction circuit according to the reading operation or the writing operation to thereby Generate the correction data write signal, and compare the correction data write signal with the corresponding correction data to generate a syndrome signal; and A syndrome decoding circuit is coupled to the syndrome generation circuit and decodes the syndrome signal to generate the error decoding signal. 13. The memory device according to claim 12, wherein when the data reading and writing circuit performs the reading operation, the syndrome generating circuit generates the correction data according to the read bit signal. write signal, and when the data read-write circuit performs the write operation, the syndrome generation circuit generates the correction data write signal according to the correction bit signal or the data output signal. 14. The memory device according to claim 12, wherein the correction data read and write circuit reads the correction data to output a correction read signal to the syndrome generation circuit, and the syndrome The generating circuit includes: The internal operation circuit includes a plurality of transmission gates and a plurality of first mutually exclusive OR gates, and controls the plurality of transmission gates to selectively provide the data output signal, the correction bit signal or the read bit data to the the plurality of first mutually exclusive OR gates to output the correction data write signal; and A plurality of second mutually exclusive OR gates receive the correction data write signal from the internal operation circuit and receive the corresponding correction read signal from the correction data read and write circuit to output the syndrome signal. 15. The memory device according to claim 1, wherein the correction data reading and writing circuit includes: A correction data reading circuit, coupled to the correction data storage unit array and the syndrome operation circuit, is used to read the correction data from the correction data storage unit array to output a correction read signal to the correction data storage unit array. a hypothesis arithmetic circuit; and A correction data writing circuit is coupled to the correction data storage unit array and the syndrome operation circuit, and is used to write the corrected correction data into the correction data storage unit array.