CN112131037A - memory device - Google Patents

Abstract

The invention provides a memory device. The data read-write circuit is used for accessing data of the memory cell array. The correction data read-write circuit is used for accessing the correction data of the correction data memory cell array. The syndrome arithmetic circuit generates an error decoding signal based on the data received from the data read-write circuit and the correction data received from the correction data read-write circuit. In the same reading period of reading data, the data reading and writing circuit corrects the error bit in the data according to the error decoding signal and outputs correct data and a correction bit signal. The syndrome arithmetic circuit also outputs a correction data writing signal to the correction data read-write circuit according to the correction bit signal to update the correction data in the correction data memory cell array. The data read-write circuit also writes the corrected data back to the memory cell array.

Description

memory device

technical field

The present invention relates to a memory device, and more particularly, to a memory device with error checking and error correction functions.

Background technique

With the advancement of technology, consumers' demand for storage media has also increased rapidly. Among them, Dynamic Random Access Memory (DRAM) has the advantages of simple structure, high density and low cost, so it is widely used in various electronic device. In order to improve the data reliability of the DRAM, some DRAMs are equipped with an error-correcting code memory (ECC memory) to detect erroneous bits in the stored data and correct the erroneous bits. At present, DRAM mainly adopts the single error correction (Single Error Correcting) technology, but the single error correction technology can only correct one bit error at a time. If the stored data has more than 2-bit errors at the same time, the error correction function of the ECC circuit will fail. However, during DRAM operation, soft errors (Softerror) may occur due to high temperature, refresh and other factors, resulting in error bits. If the erroneous bits cannot be corrected in time, the stored data may accumulate two erroneous bits and reduce the data reliability of the memory. Therefore, how to correct the stored data in time to avoid accumulating more than two erroneous bits and maintain the data correctness of the DRAM becomes a problem to be overcome.

SUMMARY OF THE INVENTION

The present invention provides a memory device that can instantly correct erroneous bits and update stored data and correction data for error checking and correction in a data read cycle.

A memory device of the present invention includes a data read and write circuit, a correction data read and write circuit and a syndrome arithmetic circuit. The data read-write circuit is coupled to the memory cell array for accessing data of the memory cell array. The calibration data read-write circuit is coupled to the calibration data storage unit array for accessing calibration data of the calibration data storage unit array. The syndrome arithmetic circuit generates an error decoding signal according to the data received from the data reading and writing circuit and the correction data received from the correction data reading and writing circuit, wherein, in the same reading cycle of reading the data, the data reading and writing circuit according to the error The decoded signal corrects the erroneous bits in the data and outputs the correct data and the corrected bit signal, wherein the data read-write circuit writes the corrected data back to the memory cell array, wherein the syndrome arithmetic circuit also outputs the corrected data according to the corrected bit signal and writes The signal is sent to the calibration data read and write circuit to update the calibration data in the calibration data storage cell array.

Based on the above, the memory device of the present invention can read data from the memory cell array and complete inspection and correction in one read cycle. When an erroneous bit in the data is found, the memory device of the present invention can instantly correct the error in the same read cycle to output correct data, and correspondingly write the corrected data back to the memory cell in a continuous period array and writing the updated correction data back to the array of correction data storage cells. Thereby, the memory device of the present invention can improve the reliability of data.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

Description of drawings

1 is a block diagram of a memory device according to an embodiment of the present invention;

2 is a schematic block diagram of a data read/write circuit according to an embodiment of the present invention;

3A is a schematic circuit diagram of a data reading circuit according to an embodiment of the present invention;

3B is a schematic waveform diagram of a read operation of a memory device according to an embodiment of the present invention;

4 is a schematic circuit diagram of a data correction circuit according to an embodiment of the present invention;

5A is a schematic circuit diagram of a data writing circuit according to an embodiment of the present invention;

5B is a schematic circuit diagram of a control signal generating circuit of a data writing circuit according to an embodiment of the present invention;

6A is a schematic waveform diagram of a write operation of a memory device according to an embodiment of the present invention when no erroneous bits are found;

6B is a schematic waveform diagram of a write operation of the memory device in the case of correcting erroneous bits according to an embodiment of the present invention;

7A is a schematic circuit diagram of a syndrome generating circuit according to an embodiment of the present invention;

7B is a schematic circuit diagram of an internal operation circuit of a syndrome generating circuit according to an embodiment of the present invention;

7C is a schematic circuit diagram of a syndrome control signal generating circuit of the syndrome generating circuit according to an embodiment of the present invention;

8 is a schematic circuit diagram of a calibration data read-write circuit according to an embodiment of the present invention;

FIG. 9 is a schematic circuit diagram of a correction data writing circuit according to an embodiment of the present invention.

Description of reference numerals

100: memory device

110: memory cell array

120: Correction data storage cell array

130: Data read and write circuit

140: Correction data read and write circuit

150: Syndrome generation circuit

160: Syndrome decoding circuit

170: Syndrome operation circuit

210: Data read circuit

220: Data correction circuit

230: Data write circuit

310: Read switch

320: Precharge circuit

330: Amplifier circuit

332: Amplifier

410: Calibration switch

420: read bit latch

430: Correction Circuit

440, 540: output circuit

442: Latch

510, 520: write switch

530: write bit latch

550: Control signal generation circuit

610: Signal generation circuit

710: Internal operation circuit

720: Input circuit

730: Syndrome control signal generation circuit

810: Correction data read circuit

820: Correction data write circuit

AD, ADi: read data

ADiT: read data signal

ADiN: Inverted read data signal

BL: bit line

BLN: Complementary Bit Line

CS: Correction Bit Signal

DE: read enable signal

DM: write mask signal

DWm: Write mask selection signal

DWmB: Inverted write mask select signal

EiT: Positive latch bit signal

EiN: Anti-latch bit signal

GND: ground voltage

LAR: read latch signal

LAWIN: Initial write latch signal

LAWm: first write latch signal

LAWmB: Invert the first write latch signal

LDWm: Second write latch signal

LDWmB: Invert the second write latch signal

LAWPT: Verify write latch signal

LAWPB: Inverted check write latch signal

MD: data

MDiT: data signal

MDiN: inverted data signal

NAND1～NAND5: Invert and gate

NOR1～NOR3: Inverse OR gate

NS: Correction data write signal

INV, INV1～INV21: Inverter

OE: output enable signal

PB: Precharge signal

PM: Correction data

PS: Correct read signal

RWB, RWBi: Data output signal

RD, RDi: read bit signal

SY: syndrome signal

SD, SDi: Error decoded signal

SDE: Decode Control Signal

TG, TG1~TG9: transmission gate

T31, T32, TP1~TP10: P-type transistors

T33, T34, T35, TN1～TN3: N-type transistor

VDD: voltage supply

VSS: low voltage

WE: write enable signal

WED: write data control signal

WEDB: Inverted write data control signal

WEm: Write data selection signal

WEmB: Inverted write data selection signal

Detailed ways

FIG. 1 is a block diagram of a memory device according to an embodiment of the present invention. 1, the memory device 100 includes a memory cell array 110, a calibration data memory cell array 120, a data reading and writing circuit 130, a calibration data reading and writing circuit 140, and a syndrome arithmetic circuit 170, wherein the syndrome arithmetic circuit 170 includes a calibration The syndrome generating circuit 150 and the syndrome decoding circuit 160 . The data read/write circuit 130 is coupled to the memory cell array 110 to access the data MD of the memory cell array 110 . The calibration data read-write circuit 140 is coupled to the calibration data storage unit array 120 to access the calibration data PM of the calibration data storage unit array 120 . The correction data PM is an error check and correction code for checking and correcting the data MD, for example, it is generated by performing an ECC encoding process such as Hamming code on the data MD. The number of bits of the correction data PM depends on the number of bits of the data MD. In this embodiment, the size of the data MD is 64 bits as an example, and the size of the correction data PM is correspondingly set to 7 bits, but the present invention does not limit the sizes of the data MD and the correction data PM.

The syndrome operation circuit 170 is based on the data MD received from the data read/write circuit 130 (the data read/write circuit 130 reads the data MD and then outputs the read bit signal RD) and the correction data PM received from the correction data read/write circuit 140 (correction). The data read-write circuit 140 reads the corrected data PM and outputs the corrected read signal PS) to generate an error decoding signal SD, wherein, in the same read cycle of reading the data MD, the data read-write circuit 130 corrects according to the error decoding signal SD Error bits in data MD and correct data (ie, data output signal RWB) and correction bit signal CS are output. The data read/write circuit 130 will write the corrected data back to the memory cell array 110, and the syndrome arithmetic circuit 170 also outputs the corrected data write signal NS to the corrected data read/write circuit 140 according to the corrected bit signal CS to update the corrected data storage Correction data PM in the cell array 120 .

In other words, in this embodiment, after reading the data MD and the correction data PM, the data can be checked through the syndrome encoding and the syndrome decoding of the syndrome operation circuit 170 . Is there an error bit in the MD. If there are erroneous bits, the data read/write circuit 130 can immediately correct the erroneous bits according to the erroneous decoding signal SD in the same reading cycle to output the correct data output signal RWB, and can also output the corrected bit signal CS to the syndrome. The arithmetic circuit 170 causes the correction data read/write circuit 140 to update the correction data PM. It is particularly mentioned that, between reading the data MD and outputting the correct data output signal RWB, the memory device 100 does not need to select the memory cells of the memory cell array 110 again, and the above actions can be completed in the same read cycle, and The correction data PM can also be updated.

The circuit structure and implementation of this embodiment are further described below. FIG. 2 is a circuit block diagram of a data read/write circuit according to an embodiment of the present invention. Please refer to FIG. 2 , the data read/write circuit 130 includes a data read circuit 210 , a data correction circuit 220 and a data write circuit 230 . The data reading circuit 210 is coupled to the memory cell array 110 for reading data MD from the memory cell array 110 to generate read data AD and corresponding read bit signals RD. The data correction circuit 220 is coupled to the data read circuit 210 and the syndrome decoding circuit 160 of the syndrome arithmetic circuit 170, and is used for latching the read data AD in the read cycle and correcting the read data according to the error decoding signal SD The error bits of AD are used to generate correct data output signal RWB and correction bit signal CS, wherein the data output signal RWB is the output result after the data read and write circuit 130 reads and corrects the data MD. The data writing circuit 230 is coupled to the data correcting circuit 220 and the memory cell array 110 , and uses the correcting bit signal CS to replace the data output signal RWB corresponding to the error bit to write the correct data MD back to the memory cell array 110 .

Referring to FIG. 1 again, the syndrome arithmetic circuit 170 includes a syndrome generating circuit 150 and a syndrome decoding circuit 160 . The syndrome generation circuit 150 is coupled to the data read/write circuit 130 and the correction data read/write circuit 140, and selects to receive the output signal of the data read circuit 210 or the data correction circuit 220 according to the read operation or the write operation to generate correction data for writing Signal NS. More specifically, when the data read/write circuit 130 performs the read operation, the syndrome generation circuit 150 generates the correction data write signal NS according to the read bit signal RD, and when the data read/write circuit 130 performs the write operation, the correction data write signal NS is generated. The test generation circuit 150 generates the correction data write signal NS according to the correction bit signal CS or the data output signal RWB.

The syndrome generation circuit 150 compares the correction data write signal NS with the corresponding correction data PM (the correction data read-write circuit 140 reads the correction data PM to provide the correction read signal PS to the syndrome generation circuit 150) to generate a checksum Sub-signal SY. The syndrome decoding circuit 160 is coupled to the syndrome generating circuit 150 to decode the syndrome signal SY to generate an error decoded signal SD. The data read/write circuit 130 corrects erroneous bits in the data MD according to the erroneous decoding signal SD.

Next, specific embodiments of the data read/write circuit 130 will be described. 3A is a schematic circuit diagram of a data read circuit according to an embodiment of the present invention, and FIG. 3B is a schematic waveform diagram of a read operation of a memory device according to an embodiment of the present invention. 4 is a schematic circuit diagram of a data correction circuit according to an embodiment of the present invention, FIG. 5A is a schematic circuit diagram of a data writing circuit according to an embodiment of the present invention, and FIG. 5B is a data writing circuit according to an embodiment of the present invention The circuit schematic diagram of the control signal generation circuit into the circuit. Please refer to FIGS. 3A to 5B in conjunction with FIGS. 1 and 2 to describe the implementation details of the data read/write circuit 130 in detail.

In FIG. 3A , the data reading circuit 210 includes a reading switch 310 , a precharging circuit 320 and an amplifying circuit 330 . The input terminal of the read switch 310 receives the data MD from the memory cell array 110 and is turned on or off under the control of the read enable signal DE. The precharge circuit 320 is coupled to the input terminal of the read switch 310 , and is controlled by the precharge signal PB to perform a precharge operation on the input terminal of the read switch 310 . The input end of the amplifying circuit 330 is coupled to the output end of the read switch 310 , and is controlled by the read enable signal DE to generate read data AD and corresponding read bit signal RD.

Specifically, the sense amplifiers in the memory cell array 110 output the data MD stored in the memory cells in the form of differential signals, so the data MD includes a differential signal between the data signal MDiT and the inverted data signal MDiN , where the data MD is 64 bits as an example, in this specification, MDi is used to represent one of the bits of the data MD, i is an integer from 0 to 63 (i=0, 1, 2, ..., 63), such as MD0, MD1, ..., MD63. Similarly, the read data AD is also a differential signal including the read data signal ADiT and the inverted read data signal ADiN. i in this specification refers to the corresponding bit, for example, the read bit signal RDi, the data output signal RWBi and the correction bit signal CSi represent the corresponding bits in the read bit signal RD, the data output signal RWB and the correction bit signal CS, Please do so.

In the read switch 310, the transfer gate TG1 is coupled to the bit line BL to receive the data signal MDiT, the transfer gate TG2 is coupled to the complementary bit line BLN to receive the inverted data signal MDiN, and the transfer gate TG1 and the transfer gate TG2 are both controlled by Read enable signal DE. The input terminal of the inverter INV1 in FIG. 3A receives the read enable signal DE, and the output terminal thereof is commonly coupled to one of the control terminals of the transmission gate TG1 and the transmission gate TG2 (for example, the N type of the transmission gate TG1 and the transmission gate TG2 ) control terminal of the transistor). The input end of the inverter INV2 is coupled to the output end of the inverter INV1, and the output end thereof is commonly coupled to the transmission gate TG1 and the other control end of the transmission gate TG2 (for example, the transmission gate TG1 and the transmission gate TG2 in the P-type transistors in the transmission gate TG1 and the transmission gate TG2. Control terminal).

In the precharge circuit 320, the inverter INV3 receives the precharge signal PB. The first end of the P-type transistor TP1 is coupled to the power supply voltage VDD, the control end thereof is coupled to the output end of the inverter INV3, and the second end thereof is coupled to the bit line BL. The first end of the P-type transistor TP2 is coupled to the power supply voltage VDD, the control end thereof is coupled to the output end of the inverter INV3, and the second end thereof is coupled to the complementary bit line BLN. The P-type transistor TP3 is coupled between the second end of the P-type transistor TP1 and the second end of the P-type transistor TP2, and the control end thereof is coupled to the output end of the inverter INV3.

In the amplifier circuit 330, the amplifier 332 is coupled to the read switch 310 to receive the data signal MDiT and the inverted data signal MDiN, and output the read data signal ADiT and the inverted read data signal ADiN correspondingly. The inverter INV4 receives the inverted read data signal ADiN to output the read bit signal RDi.

In this embodiment, the amplifier 332 includes P-type transistors T31-T32 and N-type transistors T33-T35. The P-type transistor T31 and the N-type transistor T33 are connected in series between the voltage power supply VDD and the first end of the N-type transistor T35. The P-type transistor T32 and the N-type transistor T34 are also connected in series between the voltage power supply VDD and the first end of the N-type transistor T35. between one end, wherein the control ends of the P-type transistor T31 and the N-type transistor T33 are commonly coupled to the first end of the N-type transistor T34, and the control ends of the P-type transistor T32 and the N-type transistor T34 are commonly coupled to the control end of the N-type transistor T33. first end. The second terminal of the N-type transistor T35 is coupled to the ground voltage GND, and the control terminal thereof is coupled to the read enable signal DE.

In FIG. 3B , before the read operation, the precharge signal PB turns on the read switch 310 to precharge the bit line BL and the complementary bit line BLN. When the read operation is to be started, the precharge signal PB will turn off the read switch 310 to end the precharge operation. At the same time, the selection signal CSL for selecting the memory cells of the memory cell array 110 changes from a low logic level (Low) to a high logic level (High) to read the data MD of the selected memory cells. Next, the read enable signal DE is switched to a high logic level (High) to turn on the read switch 310 and the start-up amplifier 332 to amplify the data signal MDiT and the inverted data signal MDiN to output the read data signal ADiT, the inverted read Take the data signal ADiN and the read bit signal RDi. The low voltage VSS in FIG. 3B is taken as an example of the ground voltage GND here.

Referring to FIG. 4 , the data correction circuit 220 includes a correction switch 410 , a read bit latch 420 , a correction circuit 430 and an output circuit 440 . The input terminal of the correction switch 410 receives the read data ADi from the data read circuit 210 and is turned on or off under the control of the read latch signal LAR. The read bit latch 420 is coupled to the calibration switch 410 for latching the read data ADi. The correction circuit 430 is coupled to the read bit latch 420 and receives the corresponding error decoding signal SDi, and is used for correcting the bits stored in the read bit latch 420 according to the error decoding signal SDi. The output circuit 440 is coupled to the correction circuit 430 and the read bit latch 420, and is controlled by the output enable signal OE to output the bit stored in the read bit latch 420 as the data output signal RWBi.

In the calibration switch 410 of FIG. 4 , the transfer gate TG3 receives the read data signal ADiT from the data read circuit 210 , the transfer gate TG4 receives the inverted read data signal ADiN from the data read circuit 210 , and the transfer gate TG3 and the transfer gate TG4 are all controlled by the read latch signal LAR. The input terminal of the inverter INV5 receives the read latch signal LAR, and the output terminal of the inverter INV5 is commonly coupled to one of the control terminals of the transmission gate TG3 and the transmission gate TG4 to provide an inverted signal of the read latch signal LAR.

The read bit latch 420 includes an inverter INV6 and an inverter INV7. The input terminal of the inverter INV6 is coupled to the output terminal of the inverter INV7 and receives the read data signal ADiT through the transmission gate TG3. The input terminal of the inverter INV7 is coupled to the output terminal of the inverter INV6 and receives the inverted read data signal ADiN through the transmission gate TG4.

In the correction circuit 430, the inverter INV8 receives the erroneous decoding signal SDi, and the inverter INV9 is coupled to the output terminal of the inverter INV6 to output the correction bit signal CSi. The first terminal of the P-type transistor TP4 is coupled to the power supply voltage VDD, the second terminal of the P-type transistor TP4 is coupled to the first terminal of the P-type transistor TP5, and the control terminal thereof is coupled to the output terminal of the inverter INV8. The second terminal of the P-type transistor TP5 is coupled to the input terminal of the inverter INV6, and the control terminal thereof receives the read data signal ADiT. The first terminal of the P-type transistor TP6 is also coupled to the power supply voltage VDD, the second terminal of the P-type transistor TP6 is coupled to the first terminal of the P-type transistor TP7, and the control terminal thereof is coupled to the output terminal of the inverter INV8. The second end of the P-type transistor TP7 is coupled to the output end of the inverter INV6, and the control end thereof receives the inverted read data signal ADiN.

In the output circuit 440, the input terminal of the inverter INV10 is coupled to the output enable signal OE. The first input terminal of the inversion gate NAND1 is coupled to the second terminal of the P-type transistor TP5, and the second input terminal thereof receives the output enable signal OE. The first input terminal of the inversion gate NOR1 is coupled to the second terminal of the P-type transistor TP5, and the second input terminal thereof is coupled to the output terminal of the inverter INV10. The first terminal of the P-type transistor TP8 is coupled to the power supply voltage VDD, its control terminal is coupled to the output terminal of the reverse gate NAND1, and the first terminal of the N-type transistor TN1 is coupled to the second terminal of the P-type transistor TP8 and provides a calibrated The control end of the data output signal RWBi is coupled to the output end of the inverting OR gate NOR1, and the second end thereof is coupled to the ground voltage GND. The output circuit 440 may also include a latch 442 coupled to the first terminal of the N-type transistor TN1. The circuit structure of the latch 442 is the same as that of the read bit latch 420, and is formed by interconnecting two inverters INV.

Referring to FIG. 3B again, when the read latch signal LAR switches to a high logic level, the read bit latch 420 receives the read data ADi to latch its bit value, and generates a corresponding positive latch bit signal EiT and an anti-latch Store the bit signal EiN. In FIG. 3B, during the high logic level period of the read latch signal LAR, the positive latch bit signal EiT changes to the low logic level, and the anti-latch bit signal EiN changes to the high logic level. After the read latch signal LAR is switched to a low logic level, if the i-th bit of the data MD is an error bit, the error decoding signal SDi from the syndrome decoding circuit 160 is switched to a high logic level. In the same read cycle, the correction circuit 430 inverts the erroneous bit value latched by the read bit latch 420 according to the erroneous decoding signal SDi, so the positive latched bit signal EiT and the anti-latched bit signal EiN are inverted. turn to correct mistakes. Finally, the output circuit 440 outputs the correct data output signal RWBi according to the output enable signal OE.

Referring to FIG. 5A , the data writing circuit 230 includes an inverter INV11 , a writing switch 510 , a writing switch 520 , a writing bit latch 530 and an output circuit 540 . The input terminal of the inverter INV11 receives the corresponding data output signal RWBi. The input terminal of the write switch 510 is coupled to the output terminal of the inverter INV11 and is controlled by the first write latch signal LAWm to be turned on or off. The input terminal of the write switch 520 receives the corresponding correction bit signal CSi and is controlled by the second write latch signal LDWm to be turned on or off. Here, m is an integer from 0 to 7, and represents the corresponding mask bit. The write bit latch 530 is coupled to the output terminal of the write switch 510 and the output terminal of the write switch 520 , and the output circuit 540 is coupled to the output terminal of the write switch 520 and the write bit latch 530 . The output circuit 540 is controlled by the write enable signal WE and writes the data output signal RWBi or the correction bit signal CSi into the memory cell array 110 .

Here, the data signal MDiT and the inverted data signal MDiN output by the output circuit 540 can be respectively transmitted back to the bit line and the complementary bit line of the memory cell array 110 to rewrite the data MDi.

In FIG. 5A , the write switch 510 is implemented as a transfer gate TG5, and the write switch 520 is implemented as a transfer gate TG6. The two control terminals of the transmission gate TG5 respectively receive the corresponding first write latch signal LAWm and the inversion signal of the first write latch signal LAWm (referred to as the inverted first write latch signal) LAWmB, and the transmission gate TG6 The two control terminals of the device respectively receive the second write latch signal LDWm and the inverted signal of the second write latch signal LDWm (referred to as the inverted second write latch signal) LDWmB.

The write bit latch 530 includes an inverter INV12 and an inverter INV13. The input end of the inverter INV12 is coupled to the output end of the inverter INV13, the input end of the inverter INV13 is coupled to the output end of the inverter INV12, wherein the input end of the inverter INV12 is commonly coupled to the transmission gate TG5 and the transmission The output of gate TG6.

In the output circuit 540, the inverter INV14 is connected in series with the inverter INV15, and the inverter INV14 receives the write enable signal WE. The first input end of the inversion gate NAND2 is coupled to the output end of the inverter INV12, the second input end thereof is coupled to the output end of the inverter INV15, and the first input end of the inversion gate NOR2 is coupled to the output end of the inverter INV12 The output terminal, the second input terminal of which is coupled to the output terminal of the inverter INV14. The first terminal of the P-type transistor TP9 is coupled to the power supply voltage VDD, its control terminal is coupled to the output terminal of the reverse gate NAND2, and the first terminal of the N-type transistor TN2 is coupled to the second terminal of the P-type transistor TP9 and provides a corresponding The control terminal of the data signal MDiT is coupled to the output terminal of the inverting OR gate NOR2, and the second terminal of the data signal MDiT is coupled to the ground voltage GND. The first input terminal of the inversion gate NAND3 is coupled to the output terminal of the inverter INV13, and the second input terminal thereof is coupled to the output terminal of the inverter INV15. The first input terminal of the inverting OR gate NOR3 is coupled to the output terminal of the inverter INV13 , and the second input terminal thereof is coupled to the output terminal of the inverter INV14 . The first terminal of the P-type transistor TP10 is coupled to the power supply voltage VDD, its control terminal is coupled to the output terminal of the reverse gate NAND3, and the first terminal of the N-type transistor TN3 is coupled to the second terminal of the P-type transistor TP10 and provides a corresponding The control end of the inverted data signal MDiN is coupled to the output end of the inverted OR gate NOR3, and the second end thereof is coupled to the ground voltage GND.

5B , the data writing circuit 230 further includes a control signal generating circuit 550, and the control signal generating circuit 550 generates a first writing latch signal LAWm and a second writing latch signal LAWm according to the initial writing latch signal LAW and the writing mask signal DM Write latch signal LDWm. In this embodiment, the write mask signal DM is an 8-bit signal, so the write mask signal DMm is a signal corresponding to the m-th bit, where m is an integer from 0 to 7. The control signal generation circuit 550 provides the verify write latch signal LAWPT and the inverse verify write latch signal LAWPB to the correction data read/write circuit 140, and provides the corresponding first write latch signal LAWm and the second write latch signal LAWm The latch signal LDWm and its inverted signal are sent to the data writing circuit 230 .

The control signal generating circuit 550 includes an inverter INV16 , an inverter INV17 , an inverter INV18 and a signal generating circuit 610 . The inverter INV16 and the inverter INV17 are connected in series, the input terminal of the inverter INV16 receives the initial write latch signal LAW, and the inverter INV17 outputs the verification write latch signal LAWPT to the correction data read-write circuit 140 , wherein The inverter INV18 receives the initial write latch signal LAW to output an inverted verify write latch signal LAWPB.

It is added that during the read operation, the write enable signal WE and the initial write latch signal LAW are kept at a low logic level.

In the signal generating circuit 610 of FIG. 5B , the output terminal of the inverter INV19 receives the corresponding write mask signal DMm. The first input terminal of the inversion gate NAND4 receives the initial write latch signal LAW, the second input terminal thereof is coupled to the output terminal of the inverter INV19, and the output terminal outputs the corresponding inverted first write latch signal LAWmB. The input terminal of the inverter INV20 is coupled to the output terminal of the inversion gate NAND4 to output the corresponding first write latch signal LAWm. The first input terminal of the inversion gate NAND5 receives the initial write latch signal LAW, its second input terminal receives the corresponding write mask signal DMm, and its output terminal outputs the corresponding inverted second write latch signal LDWmB. The input terminal of the inverter INV21 is coupled to the output terminal of the inversion gate NAND5 to output the corresponding second write latch signal LDWm.

FIG. 6A is a schematic waveform diagram of a write operation of the memory device according to an embodiment of the present invention when no erroneous bits are found, and FIG. 6B is a schematic diagram of a write operation of the memory device according to an embodiment of the present invention when the erroneous bits are corrected Waveform diagram. Please refer to FIG. 6A and FIG. 6B together with the above-mentioned embodiment.

In FIG. 6A , when the memory device 100 is to write data MD and the bits to be written do not need to be corrected, the enable time of the select signal CSL used to select the memory cell (eg, the time to maintain a high logic level) is called is the normal write time. During the normal write time, the correction bit signal CS and the write mask signal DM will always maintain a low logic level, the write switch 510 is turned on and the write switch 520 is turned off, and the data write circuit 230 selects the data output signal RWBi is written to the memory cell array 110 .

In FIG. 6B , after the memory device 100 finds an error bit in the data MD and the data writing circuit 230 wants to write back the correct data, the enabling time of the selection signal CSL is called the correction writing time. During the correction writing time, after the read latch signal LAR is switched to a low logic level, the logic level of the error decoding signal SDi corresponding to the wrong bit position is changed to a high level. Correspondingly, the output of the data correction circuit 220 The correction bit signal CSi also switches to a high logic level. It is added that the syndrome generation circuit 150 also outputs the correction data writing signal NS to the correction data reading and writing circuit 140 correspondingly to update the correction data PM.

Then the data writing circuit 230 performs a writing operation, the corresponding first write latch signal LAWm will turn off the write switch 510 and the corresponding second write latch signal LDWm will turn on the write switch 520, allowing the correction bit signal CSi is input to the output circuit 540 in place of the data output signal RWBi to write the correct bit value during the enable time of the write enable signal WE.

In short, when the bit to be written is originally correct, the data writing circuit 230 writes the data output signal RWBi into the memory cell array 110, and when the bit to be written is the position of the wrong bit, the data writing circuit 230 writes the data output signal RWBi into the memory cell array 110. The correction bit signal CSi is written into the memory cell array 110 .

It is particularly noted that, in this embodiment, the enabling time of the selection signal CSL can be changed, and the correction writing time will be longer than the normal writing time. When the memory device 100 finds an erroneous bit, by extending the enable time of the selection signal CSL, the data read-write circuit 130 and the correction data read-write circuit 140 can write the correct data back to the memory cell during the same period of correction. Array 110 and update correction data PM. That is to say, the selection signal CSL only needs to be enabled once to complete the actions of checking, correcting and updating.

Next, the details of the circuit structure of the syndrome generating circuit 150 will be described. 7A is a schematic circuit diagram of a syndrome generating circuit according to an embodiment of the present invention, FIG. 7B is a schematic circuit diagram of an internal operation circuit of the syndrome generating circuit according to an embodiment of the present invention, and FIG. 7C is a circuit schematic diagram according to the present invention A circuit schematic diagram of a syndrome control signal generating circuit of the syndrome generating circuit according to an embodiment of the present invention.

Referring first to FIG. 7A , the syndrome generation circuit 150 includes an internal operation circuit 710 and a plurality of mutually exclusive OR gates XOR2 , wherein the internal operation circuit 710 includes a plurality of transmission gates TG (such as transmission gates TG7 to TG9 in FIG. 7B ) and Multiple mutually exclusive OR gates to XOR1.

In FIG. 7B , the internal operation circuit 710 selectively provides the data output signal RWB, the correction bit signal CS or the read bit signal RD to the multiple exclusive OR gates XOR1 to output the correction data write signal NS by controlling the plurality of transfer gates TG. Specifically, the internal arithmetic circuit 710 has a plurality of input circuits 720 . In addition to receiving the corresponding data output signal RWBi, each input circuit 720 can also receive the corresponding read bit signal RDi from the data read circuit 210 and the corresponding correction bit signal CSi from the data correction circuit 220 . The internal operation circuit 710 selects and inputs one of the read bit signal RD, the data output signal RWB and the correction bit signal CS to the corresponding mutually exclusive OR gate XOR1 by controlling the plurality of transmission gates TG7 - TG9 in the input circuit 720 .

In detail, the transmission gate TG7 receives the corresponding read bit signal RDi and is controlled by the write data control signal WED and the inverted signal WEDB of the write data control signal WED, and the transmission gate TG8 receives the data output signal RWBi and is controlled by The write data selection signal WEm and the inversion signal WEmB of the write data selection signal WEm, the transfer gate TG9 receives the correction bit signal CSi and is controlled by the write mask selection signal DWm and the inversion signal of the write mask selection signal DWm DWmB.

When the memory device 100 performs a read operation, the input circuit 720 selects to receive the read bit signal RDi, turns on the transfer gate TG7 and turns off the transfer gates TG8 and TG9; when the memory device 100 performs a write operation, the input circuit 720 is turned off The transmission gate TG7 is turned on according to the write mask signal DM to turn on the transmission gate TG8 or the transmission gate TG9 to select the received data output signal RWBi or the correction bit signal CSi.

After multiple stages of mutually exclusive OR gate XOR1 operations, the internal operation circuit 710 finally outputs the correction data write signal NSj, wherein since the check bit in this embodiment is 7 bits, j is an integer from 0 to 6, and the correction data write signal NSj The input signal NSj represents the signal corresponding to the jth bit in the correction data write signal NS.

In FIG. 7A , a plurality of mutually exclusive OR gates XOR2 receive the corresponding correction data write signal NSj from the internal arithmetic circuit 710 and the corresponding correction read signal PSj from the correction data read and write circuit 140 . The syndrome generation circuit 150 compares the corrected read signal PS with the corrected data write signal NS to output a syndrome signal SY. The syndrome decoding circuit 160 receives the syndrome signal SY and the decoding control signal SDE and performs a decoding operation on the syndrome signal SY to output an error decoding signal SD to the data correction circuit 220 of the data reading and writing circuit 130 .

The syndrome generating circuit 150 further includes a syndrome control signal generating circuit 730 for generating the above-mentioned control signal of the transmission gate TG. The circuit structure of the syndrome control signal generating circuit 730 in FIG. 7C is similar to that of the control signal generating circuit 550 in FIG. 5B , so the details of the operation of the syndrome control signal generating circuit 730 are not repeated here.

Next, the specific circuit structure of the calibration data read/write circuit 140 will be described. FIG. 8 is a schematic circuit diagram of a calibration data read/write circuit according to an embodiment of the present invention, and FIG. 9 is a circuit schematic diagram of a calibration data writing circuit according to an embodiment of the present invention.

Referring to FIG. 8 , the calibration data reading and writing circuit 140 includes a calibration data reading circuit 810 and a calibration data writing circuit 820 . The calibration data reading circuit 810 is coupled to the calibration data storage unit array 120 and the syndrome arithmetic circuit 170 for reading calibration data PM from the calibration data storage unit array 120 to output a calibration reading signal PS to the syndrome arithmetic circuit 170 The syndrome generation circuit 150 of the . The correction data writing circuit 820 is coupled to the correction data storage unit array 120 and the syndrome generating circuit 150 of the syndrome arithmetic circuit 170 , and is used for writing the corrected correction data PM into the correction data storage unit array 120 .

When the memory device 100 performs a read operation, the correction data reading circuit 810 may read the correction data PM from the correction data storage cell array 120 to output the correction read signal PS to the syndrome generating circuit 150 . The syndrome generation circuit 150 checks whether the read bit signal RD has an error bit according to the corrected read signal PS. If there is an erroneous bit, the corresponding erroneous decoding signal SDi changes logic level. In this embodiment, if the i-th bit of the data MD is wrong, the error decoding signal SDi changes to a high logic level, as shown in FIG. 3B .

The circuit details of the calibration data reading circuit 810 can be referred to FIG. 3A . Those skilled in the art can obtain sufficient suggestions, teachings and implementations from the data reading circuit 210 , which are not repeated here.

FIG. 9 shows the circuit details of the correction data writing circuit 820, and its circuit structure is similar to the data writing circuit 230 of FIG. 5A. Those skilled in the art can obtain sufficient suggestions, teachings and implementations from the data writing circuit 230. This will not be repeated here.

Referring to FIG. 6B again, when the syndrome generation circuit 150 detects that the read bit signal RD has an error bit, the data writing circuit 230 performs error correction on the read bit signal RD, and the syndrome generation circuit 150 records the error according to the error. The corrected bit signal CS of the bit position outputs a new corrected data write signal NS. The correction data write circuit 820 writes the new correction data write signal NS to the correction data storage cell array 120 to update the correction data PM. The correction data PM in FIG. 9 is a differential signal including a correction data signal PMjT and an inversion correction data signal PMjN, and j is an integer from 0 to 6, representing a corresponding check bit.

To sum up, the memory device of the present invention can read data from the memory cell array and check it in one read cycle, wherein when an erroneous bit is found in the data, the memory device of the present invention can read data in the same read cycle. Immediately correct errors and output correct data during the cycle. In addition, the memory device of the present invention can simultaneously output correction bit signals to the data writing circuit and the syndrome generating circuit. By extending the enable period of the select signal, the data writing circuit can write the corrected data back to the memory cell array and the syndrome generating circuit can provide a new correction data writing signal to the correction data writing circuit to update the correction data. In this way, the selection signal only needs to provide an enable period to the memory cell to be written to complete the correction and update of the data, so as to achieve the effect of checking and correcting errors in real time.

Although the present invention has been disclosed above with examples, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be subject to what is defined in the claims.

Claims (17)

1. A memory device, comprising:

the data read-write circuit is coupled with the memory cell array and used for accessing the data of the memory cell array;

a correction data read-write circuit coupled to the correction data memory cell array for accessing the correction data of the correction data memory cell array; and

a syndrome arithmetic circuit for generating an error decoding signal based on the data received from the data read-write circuit and the correction data received from the correction data read-write circuit,

in the same reading period of reading the data, the data read-write circuit corrects an error bit in the data according to the error decoding signal and outputs correct data and a corrected bit signal, wherein the data read-write circuit writes the corrected data back to the memory cell array, and the syndrome arithmetic circuit further outputs a corrected data write signal to the corrected data read-write circuit according to the corrected bit signal to update the corrected data in the corrected data memory cell array.

2. The memory device according to claim 1, wherein an enabling time of a selection signal for selecting a memory cell when the corrected data is to be written into the memory cell array is referred to as a corrected writing time, and an enabling time of the selection signal when the data for which the erroneous bit is not found is to be written into the memory cell array is referred to as a normal writing time, wherein the corrected writing time is greater than the normal writing time.

3. The memory device according to claim 1, wherein the data read/write circuit comprises:

a data reading circuit, coupled to the memory cell array, for reading the data from the memory cell array to generate read data and a corresponding read bit signal;

a data correction circuit, coupled to the data reading circuit and the syndrome operation circuit, for latching the read data in the read cycle and correcting an error bit of the read data according to the error decoding signal to generate a data output signal and the corrected bit signal, wherein the data output signal is an output result of the data reading and writing circuit after the data is read and corrected; and

a data write circuit coupled to the data correction circuit and the memory cell array for replacing the data output signal corresponding to the error bit with the corrected bit signal to write the correct data back to the memory cell array.

4. The memory device according to claim 3, wherein the data reading circuit comprises:

a read switch, an input terminal of which receives the data from the memory cell array and is controlled by a read enable signal to be turned on or off;

the pre-charging circuit is coupled with the input end of the reading switch and is controlled by a pre-charging signal to execute a pre-charging action on the input end of the reading switch; and

an amplifying circuit, an input end of which is coupled to the output end of the reading switch, is controlled by the reading enabling signal to generate the reading data and generate the corresponding reading bit signal.

5. The memory device of claim 4,

the read switch includes:

a first transmission gate and a second transmission gate, wherein the first transmission gate is coupled to a bit line for receiving a data signal, the second transmission gate is coupled to a complementary bit line for receiving an inverted data signal, and both the first transmission gate and the second transmission gate are controlled by the read enable signal, wherein the data is a differential signal including the data signal and the inverted data signal; and

a first inverter and a second inverter, wherein an input terminal of the first inverter receives the read enable signal, an output terminal of the first inverter is coupled to one of the control terminals of the first transmission gate and the second transmission gate, an input terminal of the second inverter is coupled to an output terminal of the first inverter, and an output terminal of the second inverter is coupled to the other of the control terminals of the first transmission gate and the second transmission gate;

the pre-charge circuit includes:

a third inverter receiving the precharge signal;

a first P-type transistor having a first terminal coupled to a power voltage, a control terminal coupled to the output terminal of the third inverter, and a second terminal coupled to the bit line;

a second P-type transistor having a first terminal coupled to the power voltage, a control terminal coupled to the output terminal of the third inverter, and a second terminal coupled to the complementary bit line; and

a third P-type transistor coupled between the second terminal of the first P-type transistor and the second terminal of the second P-type transistor, and having a control terminal coupled to the output terminal of the third inverter; and

the amplification circuit includes:

an amplifier coupled to the read switch to receive the data signal and the inverted data signal and correspondingly output a read data signal and an inverted read data signal, wherein the read data is a differential signal including the read data signal and the inverted read data signal; and

a fourth inverter receiving the inverted read data signal to output the read bit signal.

6. The memory device according to claim 3, wherein the data correction circuit comprises:

a correction switch, an input end of which receives the read data from the data reading circuit and is controlled by a read latch signal to be turned on or off;

a read bit latch coupled to the calibration switch for latching the read data;

a correction circuit, coupled to the read bit latch and receiving the error decoding signal, for correcting the bit stored in the read bit latch according to the error decoding signal; and

the first output circuit is coupled to the correction circuit and the read bit latch, and is controlled by an output enable signal to output the bit stored in the read bit latch as the data output signal.

7. The memory device of claim 6,

the correction switch includes:

a third transmission gate and a fourth transmission gate, wherein the third transmission gate receives a read data signal from the data reading circuit, the fourth transmission gate receives an inverted read data signal from the data reading circuit, and the third transmission gate and the fourth transmission gate are both controlled by the read latch signal, wherein the read data is a differential signal including the read data signal and the inverted read data signal; and

a fifth inverter, an input terminal of which receives the read latch signal and an output terminal of which is commonly coupled to one of the control terminals of the third transmission gate and the fourth transmission gate; and

the read bit latch includes:

a sixth inverter and a seventh inverter, wherein an input of the sixth inverter is coupled to the output of the seventh inverter and receives the read data signal through the third transmission gate, and an input of the seventh inverter is coupled to the output of the sixth inverter and receives the inverted read data signal through the fourth transmission gate.

8. The memory device of claim 7, wherein the correction circuit comprises:

an eighth inverter receiving the error decoding signal;

a ninth inverter coupled to an output terminal of the sixth inverter to output the correction bit signal;

a fourth P-type transistor and a fifth P-type transistor, wherein a first terminal of the fourth P-type transistor is coupled to the power voltage, a second terminal of the fourth P-type transistor is coupled to the first terminal of the fifth P-type transistor, a control terminal of the fourth P-type transistor is coupled to the output terminal of the eighth inverter, and a second terminal of the fifth P-type transistor is coupled to the input terminal of the sixth inverter, and a control terminal of the fifth P-type transistor receives the read data signal; and

a sixth P-type transistor and a seventh P-type transistor, wherein a first terminal of the sixth P-type transistor is coupled to the power voltage, a second terminal of the sixth P-type transistor is coupled to the first terminal of the seventh P-type transistor, a control terminal of the sixth P-type transistor is coupled to the output terminal of the eighth inverter, and a second terminal of the seventh P-type transistor is coupled to the output terminal of the sixth inverter, and a control terminal of the seventh P-type transistor receives the inverted read data signal.

9. The memory device according to claim 8, wherein the first output circuit comprises:

a tenth inverter, an input terminal of which is coupled to the output enable signal;

a first nand gate having a first input terminal coupled to the second terminal of the fifth P-type transistor and a second input terminal receiving the output enable signal;

a first inverter, wherein a first input terminal of the first inverter is coupled to the second terminal of the fifth P-type transistor, and a second input terminal of the first inverter is coupled to the output terminal of the tenth inverter;

an eighth P-type transistor having a first terminal coupled to the power voltage and a control terminal coupled to the output terminal of the first NAND gate; and

a first N-type transistor having a first terminal coupled to the second terminal of the eighth P-type transistor for providing the corrected data output signal, a control terminal coupled to the output terminal of the first nor gate, and a second terminal coupled to a ground voltage.

10. The memory device according to claim 3, wherein the data writing circuit comprises:

an eleventh inverter whose input receives the corresponding data output signal;

a first write switch, an input end of which is coupled to the output end of the eleventh inverter and is controlled by a first write latch signal to be turned on or off;

a second write switch, the input end of which receives the corresponding correction bit signal and is controlled by a second write latch signal to be switched on or off;

a write bit latch coupled to an output of the first write switch and an output of the second write switch; and

and a second output circuit coupled to the output terminal of the second write switch and the write bit latch, and controlled by a write enable signal to write the data output signal or the correction bit signal into the memory cell array.

11. The memory device of claim 10,

the first write-in switch is a fifth transmission gate, and the second write-in switch is a sixth transmission gate; and

the write bit latch includes:

a twelfth inverter and a thirteenth inverter, wherein an input of the twelfth inverter is coupled to the output of the thirteenth inverter, an input of the thirteenth inverter is coupled to the output of the twelfth inverter, and inputs of the twelfth inverter are commonly coupled to the outputs of the fifth transmission gate and the sixth transmission gate.

12. The memory device according to claim 11, wherein the second output circuit comprises:

a fourteenth inverter and a fifteenth inverter, wherein the fourteenth inverter is connected in series with the fifteenth inverter, and the fourteenth inverter receives the write enable signal;

a second nand gate having a first input terminal coupled to the output terminal of the twelfth inverter and a second input terminal coupled to the output terminal of the fifteenth inverter;

a second inverter, wherein a first input terminal of the second inverter is coupled to the output terminal of the fifth inverter, and a second input terminal of the second inverter is coupled to the output terminal of the sixth inverter;

a ninth P-type transistor, having a first terminal coupled to the power voltage and a control terminal coupled to the output terminal of the second NAND gate;

a second N-type transistor having a first terminal coupled to the second terminal of the ninth P-type transistor for providing a corresponding data signal, a control terminal coupled to the output terminal of the second nor gate, and a second terminal coupled to a ground voltage;

a third nand gate having a first input terminal coupled to the output terminal of the thirteenth inverter and a second input terminal coupled to the output terminal of the fifteenth inverter;

a third inverter, wherein a first input terminal of the third inverter is coupled to the output terminal of the thirteenth inverter, and a second input terminal of the third inverter is coupled to the output terminal of the fourteenth inverter;

a tenth P-type transistor having a first terminal coupled to the power voltage and a control terminal coupled to the output terminal of the third NAND gate; and

a third N-type transistor, having a first terminal coupled to the second terminal of the tenth P-type transistor and providing a corresponding inverted data signal, a control terminal coupled to the output terminal of the third nor gate, and a second terminal coupled to the ground voltage, wherein the data is a differential signal including the data signal and the inverted data signal.

13. The memory device according to claim 12, wherein the data write circuit further comprises a control signal generation circuit that generates the first write latch signal and the second write latch signal according to an initial write latch signal and a write mask signal, comprising:

a sixteenth inverter, a seventeenth inverter and an eighteenth inverter, wherein the sixteenth inverter and the seventeenth inverter are connected in series, an input end of the sixteenth inverter receives the initial write latch signal, the seventeenth inverter outputs a verify write latch signal to the correction data read/write circuit, and the eighteenth inverter receives the initial write latch signal to output an inverted verify write latch signal to the correction data read/write circuit; and

a signal generating circuit comprising:

a nineteenth inverter, an output terminal of which receives the corresponding write mask signal;

a fourth nand gate, a first input end of which receives the initial write latch signal, a second input end of which is coupled to the output end of the nineteenth inverter, and an output end of which outputs an inverted signal of the corresponding first write latch signal;

a twentieth inverter, an input terminal of which is coupled to the output terminal of the fourth nand gate to output the corresponding first write latch signal;

a fifth nand gate, a first input terminal of which receives the initial write latch signal, a second input terminal of which receives the corresponding write mask signal, and an output terminal of which outputs an inverted signal of the corresponding second write latch signal; and

a twenty-first inverter, an input end of which is coupled to the output end of the fifth nand gate to output the corresponding second write latch signal.

14. The memory device according to claim 3, wherein the syndrome arithmetic circuit comprises:

a syndrome generating circuit, coupled to the data read/write circuit and the correction data read/write circuit, for selectively receiving an output signal of the data read/write circuit or the data correction circuit according to a read operation or a write operation to generate the correction data write signal, and comparing the correction data write signal with the corresponding correction data to generate a syndrome signal; and

the syndrome decoding circuit is coupled with the syndrome generating circuit and used for decoding the syndrome signal to generate the error decoding signal.

15. The memory device according to claim 14, wherein the syndrome generating circuit generates the correction data write signal based on the read bit signal when the data read/write circuit performs the read operation, and generates the correction data write signal based on the correction bit signal or the data output signal when the data read/write circuit performs the write operation.

16. The memory device according to claim 14, wherein the correction data read/write circuit reads the correction data to output a correction read signal to the syndrome generation circuit, and the syndrome generation circuit includes:

an internal operation circuit including a plurality of transmission gates and a plurality of first exclusive-or gates, the internal operation circuit selectively providing the data output signal, the calibration bit signal or the read bit data to the plurality of first exclusive-or gates by controlling the plurality of transmission gates to output the calibration data write signal; and

and a plurality of second exclusive-or gates receiving the correction data write signal from the internal operation circuit and receiving the corresponding correction read signal from the correction data read-write circuit to output the syndrome signal.

17. The memory device according to claim 1, wherein the correction data read/write circuit comprises:

a correction data reading circuit coupled to the correction data memory cell array and the syndrome computing circuit for reading the correction data from the correction data memory cell array to output a correction read signal to the syndrome computing circuit; and

and the correction data writing circuit is coupled with the correction data storage unit array and the syndrome operation circuit and is used for writing the corrected correction data into the correction data storage unit array.

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