CN112117330B - A device structure and process method for improving the withstand voltage of deep trench super junction MOSFET - Google Patents

Abstract

The invention discloses a device structure for improving withstand voltage of a deep-trench super-junction MOSFET and a process method thereof, wherein the N-type impurity concentration of the device from the bottom to the surface is changed through multiple injection in epitaxy, the N-type impurity concentration of the bottom of the device is reduced, the N-type impurity concentration of the surface of the device is increased, and the ratio of the N-type impurity to the P-type impurity at the bottom and the surface of the device is 1:1. the invention can solve the problems of unstable withstand voltage and low withstand voltage caused by the influence of the process of the traditional deep-groove super-junction MOSFET.

Description

A device structure and process method for improving the withstand voltage of deep trench super junction MOSFET

Technical Field

The invention belongs to the field of semiconductor device technology, and particularly relates to a deep trench super junction MOSFET device structure and a process method thereof.

Background technique

As shown in Figure 1, the cross-sectional view of an ordinary deep trench super junction MOS power tube has a certain inclination angle after deep trench etching due to the characteristics of its process method. As the pitch becomes smaller and smaller, the inclination angle will become larger and larger. This will cause the P at the bottom of the P-pillar area formed after the deep trench is backfilled with P-type epitaxy and the N at the epitaxy to be seriously unbalanced, resulting in electric field concentration and voltage drop.

Summary of the invention

In order to solve the technical problems mentioned in the above background technology, the present invention proposes a device structure and a process method for improving the withstand voltage of deep trench super junction MOSFET.

In order to achieve the above technical objectives, the technical solution of the present invention is:

A device structure for improving the withstand voltage of a deep trench super junction MOSFET. By multiple implantations in epitaxy, the N-type impurity concentration of the device from the bottom to the surface is changed, the N-type impurity concentration at the bottom of the device is reduced, and the N-type impurity concentration on the surface of the device is increased, so that the ratio of N-type impurities to P-type impurities at the bottom and surface of the device reaches 1:1.

A process method for improving the device structure of deep trench super junction MOSFET withstand voltage, comprising the following steps:

(1) Using an N-type (100) crystal orientation as the substrate of the epitaxial wafer, doping arsenic or antimony, and growing an initial epitaxial layer on the substrate;

(2) Grow an intermediate epitaxial layer on the initial epitaxial layer, and perform three N-type impurity P general injections. The energies of the three injections are 60, 150, and 300 KeV, respectively, and the injection dose is 1E12 to 3E12. This step is repeated multiple times according to the withstand voltage requirements;

(3) growing a surface epitaxial layer on the intermediate epitaxial layer;

(4) Grow an oxide layer on the epitaxial wafer as a masking layer for JFET implantation; then perform JFET lithography and JFET implantation, with an implantation energy of 60Kev to 80Kev, an implantation dose of 1E12 to 3E12, and the implanted element being phosphorus;

(5) Perform hard mask deposition, trench lithography and etching in sequence; then grow a sacrificial oxide layer and remove it to remove the surface defects or particles of the trench; then perform EPI backfill in the trench to form the device P/N structure;

(6) Body lithography, implantation and annealing are performed in the active area to form a P-body junction area; the implantation energy is 100Kev to 140Kev, the implantation dose is 4E13 to 6E13, the implanted element is boron, the annealing temperature is 1100°C, and the annealing time is 30 to 180 minutes;

(7) growing a field oxide layer and performing photolithography, exposing and etching the active area, and removing all the oxide layers in the active area except the terminal area;

(8) growing a gate oxide layer, depositing polycrystalline and doping; then performing polycrystalline photolithography and etching;

(9) NP photolithography, NP implantation and NP well-pushing are performed in sequence to form the main MOS tube source region; the implantation energy is 60Kev to 120Kev, the implantation dose is 5E15 to 1E16, the implanted element is arsenic, the well-pushing temperature is 950°C, and the well-pushing time is 30 minutes;

(10) depositing a dielectric, then performing hole photolithography and etching to form hole contacts;

(11) Deposit metal, then photoetch the metal to form the gate and source regions of MOS;

(12) Thinning the back side of the substrate and then evaporating Ti-Ni-Ag alloy on the back side of the substrate.

Furthermore, in step (1), the resistivity of the initial epitaxy is 1 to 3 Ω.cm; in step (2), the resistivity of the intermediate epitaxy is 10 to 30 Ω.cm; and in step (3), the resistivity of the surface epitaxy is 1 to 3 Ω.cm.

Furthermore, in step (4), the thickness of the grown oxide layer is 300 to 500 angstroms; in step (7), the thickness of the grown field oxide layer is 8000 to 12000 angstroms; in step (8), the thickness of the grown gate oxide layer is 700 to 1200 angstroms, and the thickness of the grown polycrystalline is 6000-8000 angstroms.

Furthermore, in step (10), the medium is borophosphosilicate glass, and the thickness of the medium is 10,000 angstroms.

Furthermore, in step (11), the metal is aluminum, and the thickness of the metal is 4 um.

Furthermore, between step (11) and step (12), the opening regions of the MOS gate and source and the opening region of the sampling MOS tube source are formed by passivation layer deposition, photolithography, and etching.

Furthermore, the passivation layer is made of silicon nitride, and the thickness of the passivation layer is 7000-12000 angstroms.

The beneficial effects brought by adopting the above technical solution are:

The device structure and preparation process for improving the withstand voltage of deep trench super junction MOSFET designed in the present invention can change the N-type impurity concentration from the bottom to the surface through multiple injections in the epitaxy, thereby solving the problem of unstable and low withstand voltage of traditional deep trench super junction MOSFET caused by process influence. As the pitch becomes smaller and smaller, the advantages of this structure will become more and more obvious.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a cross-sectional view of a conventional deep trench super junction MOS power tube;

FIG2 is a cross-sectional view of a deep trench super junction MOS power tube designed by the present invention;

FIG3 is a schematic diagram of the preparation process of the present invention after step 1;

FIG4 is a schematic diagram of the preparation process of the present invention after step 2;

FIG5 is a schematic diagram of the preparation process of the present invention after step 3;

FIG6 is a schematic diagram of the preparation process of the present invention after step 4;

FIG7 is a schematic diagram of the preparation process of the present invention after step 5;

FIG8 is a schematic diagram of the preparation process of the present invention after step 6;

FIG9 is a schematic diagram of the preparation process of the present invention after step 7;

FIG10 is a schematic diagram of the preparation process of the present invention after step 8;

FIG11 is a schematic diagram of the preparation process of the present invention after step 9;

FIG12 is a schematic diagram of the preparation process of the present invention after step 10;

FIG. 13 is a schematic diagram of the preparation process of the present invention after step 11.

Detailed ways

The technical solution of the present invention will be described in detail below with reference to the accompanying drawings.

The present invention designs a device structure for improving the withstand voltage of deep trench super junction MOSFET, as shown in FIG2 , by multiple injections in the epitaxy, the N-type impurity concentration of the device from the bottom to the surface is changed, the N-type impurity concentration at the bottom of the device is reduced, and the N-type impurity concentration on the surface of the device is increased, so that the ratio of N-type impurities to P-type impurities at the bottom and surface of the device reaches 1:1, thereby obtaining a stable and higher withstand voltage.

The process flow of the device structure for improving the withstand voltage of deep trench super junction MOSFET is as follows:

1. Initial epitaxial preparation: The substrate of the epitaxial wafer adopts N-type (100) crystal orientation, arsenic or antimony doping, and the resistivity is usually 0.001~0.005Ω.cm. Different epitaxial resistivity and thickness can be selected to obtain different device withstand voltages. Usually the resistivity is 1~3Ω.cm, and a 7um epitaxial layer is grown first, as shown in Figure 3;

2. Intermediate epitaxial growth: The growth resistivity is 10-30Ω.cm, the thickness is 5-6um, and three N-type impurity P general injections are performed, with energies of 60, 150, and 300KeV, and doses of 1E12-3E12; this process is repeated 6-8 times according to different withstand voltage requirements; as shown in Figure 4;

3. Surface epitaxy preparation: The growth resistivity is 1-3Ω.cm, and the thickness is 5um epitaxy, as shown in Figure 5; the total thickness of the epitaxy reaches 45-60um, and the device withstand voltage can reach 500V-800V;

4. JFET lithography & imp: Grow a 300-500 angstrom oxide layer on the epitaxial wafer as a mask for JFET implantation. Then JFET lithography, then JFET implantation, implantation energy: 60Kev~80Kev, dose: 1E12~3E12, phosphorus element. The purpose of this step is to dope the JFET region in the CELL, as shown in Figure 6;

5. Trench photolithography and etching and P-type epitaxial backfill: Hard mask (oxide layer) deposition, Trench photolithography, etching, then growing a layer of sacrificial oxide and removing it to remove surface defects or particles on the Trench; then backfill the EPI in the Trench to form the P/N structure of the CoolMOS device, as shown in Figure 7;

6. Body lithography, implantation and annealing: implantation is performed after selective exposure in the active area, with an implantation dose of 4E13-6E13, an implantation energy of 100Kev-140Kev, and an implantation element of boron; then body annealing is performed at a temperature of 1100°C for 30-180 minutes to form a P-body junction region; as shown in FIG8 ;

7. Field oxygen growth, photolithography, and etching: grow an oxide layer of 8000 to 12000 angstroms, perform photolithography, expose and etch the active area, and remove all the oxide layers in the active area except the terminal area; as shown in FIG9 ;

8. Gate oxide, polycrystalline deposition and polycrystalline doping, photolithography, and etching: grow a gate oxide layer with a thickness of generally 700-1200 angstroms, deposit polycrystalline with a thickness of 6000-8000 angstroms and dope it; then perform polycrystalline photolithography and etching, as shown in FIG10 ;

9. NP lithography, NP implantation, NP push-up, forming the main MOS tube source region: NP implantation dose: 5E15 ~ 1E16, implantation energy: 60Kev-120Kev, implantation element: arsenic; NP push-well temperature: 950℃, time: 30 minutes; as shown in Figure 11;

10. Dielectric generation, hole lithography, hole etching: deposit dielectric BPSG (boron phospho-silicate glass) 10000 angstroms, then open a hole to form a hole contact, as shown in FIG12 ;

11. Sputtering metal, metal photolithography, etching: deposit 4um aluminum, then photolithography and etching aluminum to form the gate and source regions of MOS, as shown in Figure 13;

12. Passivation layer deposition, passivation layer photolithography, and etching: Deposit 7000-12000 angstroms of passivation layer silicon nitride, then perform photolithography and etching to form the opening areas of the Gate and Source; the passivation layer process is optional and may or may not be performed;

13. Back Ti-Ni-Ag: Thin the back of the substrate to 200um-300um, and then evaporate Ti-Ni-Ag (titanium-nickel-silver) alloy on the back of the substrate.

The embodiments are only for illustrating the technical idea of the present invention and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the present invention.

Claims (4)

1. A process for improving the device structure of deep trench super junction MOSFET withstand voltage, characterized in that it comprises the following steps: (1) Using an N-type [100] crystal orientation as the substrate of the epitaxial wafer, doping arsenic or antimony, and growing an initial epitaxial layer on the substrate; (2) growing an intermediate epitaxial layer on the initial epitaxial layer, and performing three N-type impurity general injections, the energies of the three injections are 60, 150, and 300 KeV, respectively, and the injection dose is 1E12 to 3E12; this step is repeated multiple times according to the withstand voltage requirements; through multiple injections in the epitaxial layer, the N-type impurity concentration of the device from the bottom to the surface is changed, the N-type impurity concentration at the bottom of the device is reduced, and the N-type impurity concentration on the surface of the device is increased, so that the ratio of N-type impurities to P-type impurities at the bottom and surface of the device reaches 1:1; (3) growing a surface epitaxial layer on the intermediate epitaxial layer; (4) Grow an oxide layer on the epitaxial wafer as a masking layer for JFET implantation; then perform JFET lithography and JFET implantation, with an implantation energy of 60Kev to 80Kev, an implantation dose of 1E12 to 3E12, and the implanted element being phosphorus; (5) Perform hard mask deposition, trench lithography and etching in sequence; then grow a sacrificial oxide layer and remove it to remove the surface defects or particles of the trench; then perform EPI backfill in the trench to form the device P/N structure; (6) Body lithography, implantation and annealing are performed in the active area to form a P-body junction area; the implantation energy is 100Kev to 140Kev, the implantation dose is 4E13 to 6E13, the implanted element is boron, the annealing temperature is 1100°C, and the annealing time is 30 to 180 minutes; (7) growing a field oxide layer and performing photolithography, exposing and etching the active area, and removing all the oxide layers in the active area except the terminal area; (8) growing a gate oxide layer, depositing polycrystalline and doping; then performing polycrystalline photolithography and etching; (9) NP photolithography, NP implantation and NP well-pushing are performed in sequence to form the main MOS tube source region; the implantation energy is 60Kev to 120Kev, the implantation dose is 5E15 to 1E16, the implanted element is arsenic, the well-pushing temperature is 950°C, and the well-pushing time is 30 minutes; (10) depositing a dielectric, then performing hole photolithography and etching to form hole contacts; (11) Deposit metal, then photoetch the metal to form the gate and source regions of MOS; (12) thinning the back side of the substrate and then evaporating a Ti-Ni-Ag alloy on the back side of the substrate; In step (1), the resistivity of the initial epitaxy is 1 to 3 Ω·cm; in step (2), the resistivity of the intermediate epitaxy is 10 to 30 Ω·cm; in step (3), the resistivity of the surface epitaxy is 1 to 3 Ω·cm; Between step (11) and step (12), the opening regions of the MOS gate and source and the opening region of the sampling MOS tube source are formed by passivation layer deposition, photolithography, and etching; The passivation layer is made of silicon nitride, and the thickness of the passivation layer is 7000-12000 angstroms. 2. The process method for improving the device structure of deep trench super junction MOSFET withstand voltage according to claim 1 is characterized in that: in step (4), the thickness of the grown oxide layer is 300 to 500 angstroms; in step (7), the thickness of the grown field oxide layer is 8000 to 12000 angstroms; in step (8), the thickness of the grown gate oxide layer is 700 to 1200 angstroms, and the thickness of the grown polycrystalline is 6000-8000 angstroms. 3. The process method for improving the device structure of deep trench super junction MOSFET voltage resistance according to claim 1 is characterized in that: in step (10), the medium is borophosphosilicate glass, and the thickness of the medium is 10,000 angstroms. 4. The process method for improving the device structure of deep trench super junction MOSFET voltage resistance according to claim 1 is characterized in that: in step (11), the metal is aluminum and the thickness of the metal is 4 um.