CN102479805A - Super junction semiconductor element and manufacture method thereof - Google Patents
Super junction semiconductor element and manufacture method thereof Download PDFInfo
- Publication number
- CN102479805A CN102479805A CN2010105649509A CN201010564950A CN102479805A CN 102479805 A CN102479805 A CN 102479805A CN 2010105649509 A CN2010105649509 A CN 2010105649509A CN 201010564950 A CN201010564950 A CN 201010564950A CN 102479805 A CN102479805 A CN 102479805A
- Authority
- CN
- China
- Prior art keywords
- conduction type
- epitaxial loayer
- type
- semiconductor element
- super
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 238000000034 method Methods 0.000 title abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 238000005530 etching Methods 0.000 claims abstract description 31
- 238000002347 injection Methods 0.000 claims abstract description 14
- 239000007924 injection Substances 0.000 claims abstract description 14
- 238000013459 approach Methods 0.000 claims description 19
- 238000000407 epitaxy Methods 0.000 claims description 18
- 239000000203 mixture Substances 0.000 claims description 11
- 230000008569 process Effects 0.000 abstract description 14
- 230000007547 defect Effects 0.000 abstract description 9
- 238000009792 diffusion process Methods 0.000 abstract description 9
- 238000001259 photo etching Methods 0.000 description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 14
- 229910052710 silicon Inorganic materials 0.000 description 14
- 239000010703 silicon Substances 0.000 description 14
- 239000012535 impurity Substances 0.000 description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 230000005684 electric field Effects 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000026267 regulation of growth Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Images
Landscapes
- Recrystallisation Techniques (AREA)
Abstract
The invention relates to a super junction semiconductor element and a manufacture method thereof. The super junction semiconductor element comprises a first conduction type substrate, at least one first conduction type first epitaxial layer and at least one first conduction type second epitaxial layer, wherein the first conduction type first epitaxial layer is arranged on the first conduction type substrate and comprises second conduction type doping, the first conduction type second epitaxial layer is arranged on the first conduction type first epitaxial layer and comprises second conduction type doping, and a device characteristic layer is arranged on the second epitaxial layer. The lattice defect problem caused by multi-time epitaxial growth, ion injection and diffusion can also be reduced to a certain degree, and high cost generated by too many epitaxial times is avoided. Simultaneously, the process difficulty of the etching and the groove filling is also greatly reduced along with grooves, and the stress and wafer curling problems caused by excessive depth of the grooves are also reduced.
Description
Technical field
The invention belongs to field of semiconductor manufacture, be specifically related to a kind of super-junction semiconductor element and manufacturing approach thereof.
Background technology
In common power device, the interval reverse voltage of decision N+ district and P+ is born by a lightly doped semiconductor, is Withstand voltage layer (Voltage Sustaining Layer) to call this layer in the following text.For high voltage power device, conducting resistance Ron (or conduction voltage drop) is also mainly decided by Withstand voltage layer, and this layer mixes light more, or thickness is big more, or the both is, then puncture voltage is high more, but conducting resistance (or conduction voltage drop) is also big more.One of sixty-four dollar question is to have high puncture voltage that low conducting resistance is arranged again in power device, and the relation between the two becomes the obstacle of making the high-performance power device.Modern common power semiconductor mainly contains two kinds of VDMOS and IGBT, but has Ron ∝ between these two kinds of break-over of device resistance and the puncture voltage
V B 2.5Approximation relation, become the bottleneck of power device development.And above-mentioned Ron is meant the conducting area in the Withstand voltage layer, and in fact in the Withstand voltage layer total some zone do not participate in conduction.For example, the zone under the source substrate zone of vertical-type (longitudinal type) MOSFET (mos field effect transistor).The appearance of super junction has solved the problems referred to above, and solution is in the P+ district and N+ is interval comes withstand voltage with a compound buffer layer (Composite Buffer Layer, or abbreviation CB layer).
The zone of containing two kinds of films of opposite conductivity in the CB layer of super junction, these two kinds of zones all are alternately from being parallel to the arbitrary section at CB layer and N+ layer (or P+ layer) interface.The compound buffer layer that has P district and N district alternate combinations to form between plane that promptly joins in the P+ district and the N+ regional boundary face; All there is the interface that intersects with above-mentioned two faces in each P district in the compound buffer layer and each N district; Except that these two abutted surfaces; Each P district of compound buffer layer is surrounded by adjacent N district, and each N district is surrounded by adjacent P district.And all Withstand voltage layers before this all are the semiconductors of single conduction type.Like this, when the CB layer exhausts, the material of two kinds of conduction types (P district and N district); Electrically opposite electric charge is provided; The electric field major part of its generation is cancelled each other, and this just makes the doping content in P district and N district can be higher than common withstand voltage zone, and its conducting resistance is lower than common withstand voltage zone.
The withstand voltage integration of electric field in depletion region that in fact be equivalent to of device; For common MOSFET; The electric field of its Withstand voltage layer is on a declining curve to substrate B from device feature layer A, and shown in figure one, the withstand voltage of Withstand voltage layer is a trapezoidal area for the integration of electric field; For the MOSFET with super junction, the electric field device feature layer A of its Withstand voltage layer evenly distributes to resilient coating C, and be as shown in Figure 2, and the withstand voltage of Withstand voltage layer adds a trapezoidal area for the integration of electric field promptly is approximately a rectangle.Having the MOSFET conducting resistance of super-junction structures and the relation between the puncture voltage is approximately
ROn ∝
V B 1.3, bottleneck between VDMOS break-over of device resistance and the puncture voltage breaks traditions
This shows and adopt the same resistivity extension, the withstand voltage of MOSFET with super-junction structures will be higher than the withstand voltage of common MOSFET.Promptly make identical withstand voltage MOSFET product, the MOSFET of super-junction structures can adopt more low-resistivity extension, and for high-voltage MOSFET, the reduction of epilayer resistance rate can reduce the conducting resistance of device greatly.
The manufacturing approach of super junction roughly is divided into two kinds at present: epitaxy and ditch channel process.
Epitaxy is the flow chart that the prior art epitaxy is made super junction like Fig. 2 to Fig. 3; First growth regulation one deck extension N on heavily doped N+ substrate injects the p type impurity of predetermined close in the precalculated position of this epitaxial loayer, make amount and p type impurity flux matched of the N type impurity in this epitaxial loayer.Owing to need in this one deck extension, form the P district with the method for injecting, so the thickness of every layer of extension can not be too thick, be generally 5-8um, general 50v is to a such epitaxial loayer of the withstand voltage needs of 100v.Therefore, for the transistor of a 600v, which floor N type extension that roughly need be shown in figure two, and after each extension, to do the injection of P type ion.P type ion implanted layer has formed that the more consistent air bubble-shaped of shape up and down shown in figure three links to each other and the P type column knot of concentration even diffused after through diffusion.Thus, formed P district and N district alternately.And then do the device feature layer, as shown in Figure 3.The device feature layer is by P well region, P+ district; The N+ source region that grid oxide layer and polycrystalline grid are formed by the ion injection etc. is formed, shown in 30 among the figure three.
P type shape column knot in the super junction of epitaxy manufacturing is through repeatedly extension, oxidation, photoetching and boron ion inject and form repeatedly; In the technical process, the boron ion that last time injected can spread drift along with back time extension, needs to calibrate through a large amount of experiments.So this process need is accurately controlled boron ion implantation dosage, window and propelling time, form that the more consistent air bubble-shaped of shape up and down links to each other and the column knot of concentration even diffused, to realize the charge compensation of super junction.The chip terminal design must be compatible with active area, realizes the charge compensation of chip terminal.And the avalanche capability of super junction MOSFET device can be low than conventional high-tension MOS, and repeatedly epitaxial growth, ion injection and diffusion can produce a large amount of lattice defects, also can influence the reliability of device.
The grooving method is the flow chart of prior art groove manufactured super junction like Fig. 4 to Fig. 6; Its process is first growth one deck N type extension on heavily doped N+ substrate, and this sentences the 600v transistor is that example approximately needs 40um, and at the presumptive area ditching groove of the epitaxial loayer of this N type doping type, the degree of depth of groove is approximately 40um, shown in figure four; In groove, form the epitaxial loayer with P type doping type then respectively, the content of the p type impurity of the outer Yanzhong of this P type is to require predefinedly according to charge balance, and the amount of the N type impurity in the epitaxial loayer equates with the amount of p type impurity.Thus, formed P district and N district alternately, shown in figure five; And then do the device feature layer, as shown in Figure 6.The device feature layer is by there being ion to inject the N+ source region that forms, P well region, P+ district; Compositions such as grid oxide layer and polycrystalline grid.Shown in 60 among the figure six.The deep plough groove etched warpage that causes stress and wafer, the yield of chip has much room for improvement.
Extension manufactured super junction needs a lot of layers of extension just can meet the demands in the prior art, and repeatedly epitaxial growth, ion inject and diffusion can produce a large amount of lattice defects, also can influence the reliability of device.The grooving method needs the darker groove of etching just can meet the demands, the deep plough groove etched warpage that causes stress and wafer, and the yield of chip has much room for improvement, and technology difficulty is high, cost is higher.
Summary of the invention
The technical problem that the present invention solves is that repeatedly epitaxy pure in the prior art causes lattice defect, influence the problem of device reliability, the pure deep plough groove etched warpage that causes stress and wafer, technology difficulty height, cost problem of higher.
For solving the problems of the technologies described above, the present invention provides following technical scheme:
A kind of super-junction semiconductor element comprises: first conductivity type substrate; Be arranged at first epitaxial loayer of first conduction type of one deck at least on first conductivity type substrate, comprise in said first epitaxial loayer that second conduction type mixes; Be arranged at least the first conduction type second epitaxial loayer on first epitaxial loayer of first conduction type; Said second epitaxial loayer comprises that second conduction type mixes; Second epitaxial loayer is provided with the device feature layer.
A kind of manufacturing approach of above-mentioned super-junction semiconductor element comprises: step 1: first conductivity type substrate is provided; Step 2: first epitaxial loayer of growth first conduction type on first conductivity type substrate, carry out the doping of second conduction type and inject on first epitaxial loayer; Step 3: growth has second epitaxial loayer of first conduction type on first epitaxial loayer that carries out second conduction type doping injection completion; Etching on second epitaxial loayer, and in the groove of etching, make second conduction type and mix; Step 4: on second epitaxial loayer, make the device characteristic layer.
A kind of manufacturing approach of above-mentioned super-junction semiconductor element comprises: step 1: first conductivity type substrate is provided; Step 2: the 3rd epitaxial loayer of growth first conduction type on first conductivity type substrate, etching on first epitaxial loayer, and in the groove of etching, make second conduction type and mix; Step 3: growth has the 4th epitaxial loayer of first conduction type on the 3rd epitaxial loayer; On the 4th epitaxial loayer, carrying out the doping of second conduction type injects; Step 4: on the 4th epitaxial loayer, make the device characteristic layer.
Compared with prior art the present invention has following beneficial effect: a kind of super-junction semiconductor element and manufacturing approach thereof that the embodiment of the invention provides; When grown epitaxial layer; It is so high that the accuracy of controlling the second conduction type doping implantation dosage, window and propelling time etc. is required not look like epitaxy; Also can alleviate the lattice defect problem that produces because of repeatedly epitaxial growth, ion injection and diffusion to a certain extent, avoid too much produce expensive of extension number of times.Simultaneously, the degree of depth of groove that needs etching in this technical process is dark during not as pure groove manufactured super junction, so the technology difficulty of etching and filling groove is along with groove reduces greatly; Also alleviated the problem of crossing the warpage of taking an advanced study into stress and wafer because of gash depth.
Description of drawings
Fig. 1 is commonplace components Withstand voltage layer and the distribution map of the electric field with Withstand voltage layer of super junction device.
Fig. 2 to Fig. 3 is the flow chart that the prior art epitaxy is made super junction.
Fig. 4 to Fig. 6 is the flow chart of prior art groove manufactured super junction.
Fig. 7 to Figure 12 is the flow chart that first embodiment of the invention is made super junction.
Figure 13 to Figure 18 is the flow chart that second embodiment of the invention is made super junction.
Embodiment
Clearer for technical problem, technical scheme and beneficial effect that the present invention is solved, below in conjunction with accompanying drawing and embodiment, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
The invention discloses a kind of super-junction semiconductor element, comprising: first conductivity type substrate; Be arranged at first epitaxial loayer of first conduction type of one deck at least on first conductivity type substrate, comprise in said first epitaxial loayer that second conduction type mixes; Be arranged at least the first conduction type second epitaxial loayer on first epitaxial loayer of first conduction type; Said second epitaxial loayer comprises that second conduction type mixes; Second epitaxial loayer is provided with the device feature layer.
The present invention provides two kinds of embodiment to explain the present technique scheme.
Embodiment one:
With reference to Figure 12, a kind of super-junction semiconductor element comprises: first conductivity type substrate 11; Be arranged at first epitaxial loayer 12 of first conduction type of one deck at least on first conductivity type substrate, comprise in said first epitaxial loayer that second conduction type mixes 122; Be arranged at first conduction type, second epitaxial loayer 13 on first epitaxial loayer of first conduction type; Said second epitaxial loayer comprises that second conduction type mixes 132; Second epitaxial loayer is provided with device feature layer 100.
A kind of manufacturing approach of above-mentioned super-junction semiconductor element, its flow chart such as Fig. 7 comprise: step 1: first conductivity type substrate is provided to shown in Figure 12; Step 2: first epitaxial loayer of growth first conduction type on first conductivity type substrate, carry out the doping of second conduction type and inject on first epitaxial loayer; Step 3: growth has second epitaxial loayer of first conduction type on first epitaxial loayer that carries out second conduction type doping injection completion; Etching on second epitaxial loayer, and in the groove of etching, make second conduction type and mix; Step 4: on second epitaxial loayer, make the device characteristic layer.When grown epitaxial layer; It is so high that the accuracy of controlling the second conduction type doping implantation dosage, window and propelling time etc. is required not look like epitaxy; Also can alleviate the lattice defect problem that produces because of repeatedly epitaxial growth, ion injection and diffusion to a certain extent, avoid too much produce expensive of extension number of times.Simultaneously, the degree of depth of groove that needs etching in this technical process is dark during not as pure groove manufactured super junction, so the technology difficulty of etching and filling groove is along with groove reduces greatly; Also alleviated the problem of crossing the warpage of taking an advanced study into stress and wafer because of gash depth.
The MOSFET device that has super-junction structures with 600v is that example specifies:
Step 1: first conductivity type substrate is provided; First conduction type is the N type here, specifically provides to have the heavily doped semi-conductor silicon chip 11 of N type;
Step 2: first epitaxial loayer of growth first conduction type on first conductivity type substrate; Carrying out second conduction type doping injection on first epitaxial loayer: N type first epitaxial loayer 121 that growth one deck approaches on the semi-conductor silicon chip 11 that the N type mixes; Thickness is 5-8um; Through photoetching, define the zone that P type ion 122 injects, and carry out P type ion and inject; Repeat above-mentioned steps, form structure as shown in Figure 7.
Step 3: growth has second epitaxial loayer of first conduction type on first epitaxial loayer that carries out second conduction type doping injection completion; Etching on second epitaxial loayer; And in the groove of etching, make second conduction type and mix: the second thicker epitaxial loayer of growth one deck on silicon chip; Thickness is about 20um, and shown in 131 among Fig. 8, the thickness of this second epitaxial loayer is greater than the thickness of first epitaxial loayer in the step; Define the zone of grooving with photoetching process, and etch groove, as shown in Figure 9; Utilize the epitaxy one deck P type extension 132 of on silicon chip, growing then, wherein the amount of the impurity of P type is that the amount of calculating in advance with N type impurity is complementary, and can reach charge balance, and is shown in figure 10; With chemical mechanical polishing method the thickness of this P type extension is milled to and being of uniform thickness of N type extension at last, shown in figure 11.
Step 4: on second epitaxial loayer, make device characteristic layer 100, after the annealed processing, form MOSFET structure with super junction, shown in figure 12.The detailed process of making the device characteristic layer is following:
1) oxide layer of on semi-conductor silicon chip, growing;
2) through photoetching, define active area, field oxide is carried out etching;
3) growth gate oxide is in gate oxide surface deposition conductive polycrystalline silicon;
4) through photoetching, define polysilicon region, carry out etching polysilicon
5) carry out the p type impurity ion with whole semi-conductor silicon chip surface and inject, the zone of the P trap that field oxide that previous process forms and polysilicon region can define formation, high annealing forms the P trap of array;
6) define the source region through photoetching, N type foreign ion injects, and pushes away trap formation N+ type source region;
7) with whole semi-conductor silicon chip surface deposition dielectric layer;
8), define the contact hole zone, and carry out the oxide layer etching through photoetching;
9) deposited metal through photoetching, defines etch areas, carries out metal etch.
The MOSFET that this method produces has alleviated the lattice defect problem that produces because of repeatedly epitaxial growth, ion injection and diffusion; Also alleviated the problem of crossing the warpage of taking an advanced study into stress and wafer because of gash depth.
Embodiment two:
With reference to Figure 18, a kind of super-junction semiconductor element comprises: first conductivity type substrate; Be arranged at the 3rd epitaxial loayer of first conduction type on first conductivity type substrate, comprise in said the 3rd epitaxial loayer that second conduction type mixes; Be arranged at first conduction type of one deck at least the 4th epitaxial loayer on first epitaxial loayer of first conduction type; Said the 4th epitaxial loayer comprises that second conduction type mixes; The 4th epitaxial loayer is provided with the device feature layer.
A kind of manufacturing approach of above-mentioned super-junction semiconductor element comprises: step 1: first conductivity type substrate is provided; Step 2: the 3rd epitaxial loayer of growth first conduction type on first conductivity type substrate, etching on first epitaxial loayer, and in the groove of etching, make second conduction type and mix; Step 3: growth has the 4th epitaxial loayer of first conduction type on the 3rd epitaxial loayer; On the 4th epitaxial loayer, carrying out the doping of second conduction type injects; Step 4: on the 4th epitaxial loayer, make the device characteristic layer.When grown epitaxial layer; It is so high that the accuracy of controlling the second conduction type doping implantation dosage, window and propelling time etc. is required not look like epitaxy, also can alleviate the lattice defect problem that produces because of repeatedly epitaxial growth, ion injection and diffusion to a certain extent.Simultaneously, the degree of depth of groove that needs etching in this technical process is dark during not as pure groove manufactured super junction, so the technology difficulty of etching and filling groove is along with groove reduces greatly; Also alleviated the problem of crossing the warpage of taking an advanced study into stress and wafer because of gash depth.
The MOSFET device that has super-junction structures with 600v is that example specifies:
Step 1: first conductivity type substrate is provided: first conduction type is the N type here, specifically provides to have the heavily doped semi-conductor silicon chip 21 of N type;
Step 2: the 3rd epitaxial loayer of growth first conduction type on first conductivity type substrate; Etching on first epitaxial loayer; And in the groove of etching, make second conduction type and mix: thicker N type the 3rd epitaxial loayer of growth one deck on the semi-conductor silicon chip 221 that the N type mixes; Thickness is about 20um, like Figure 13; Photoetching process defines the zone of grooving, and carries out silicon etching, like Figure 14; Utilize the epitaxy one deck P type extension 222 of on silicon chip, growing, shown in figure 15; Adopt chemical mechanical polishing method that the thickness of this P type extension is milled to and being of uniform thickness of N type extension, shown in figure 16.
Step 3: growth has the 4th epitaxial loayer of first conduction type on the 3rd epitaxial loayer; On the 4th epitaxial loayer, carrying out the doping of second conduction type injects; Thin N type the 4th epitaxial loayer 231 of growth one deck on the 3rd epitaxial loayer 22, thickness is 5-8um; Cross photoetching then, define the zone that P injects, and carry out the second conduction type P ion 232 and inject; Repeat this step 3, form structure shown in figure 17.
Step 4: on the 4th epitaxial loayer, make device characteristic layer 200.After the annealed processing, form MOSFET structure with super junction, shown in figure 18.The detailed process of making the device characteristic layer is following:
1) oxide layer of on semi-conductor silicon chip, growing;
2) through photoetching, define active area, field oxide is carried out etching;
3) growth gate oxide is in gate oxide surface deposition conductive polycrystalline silicon;
4) through photoetching, define polysilicon region, carry out etching polysilicon;
5) carry out the p type impurity ion with whole semi-conductor silicon chip surface and inject, the zone of the P trap that field oxide that previous process forms and polysilicon region can define formation, high annealing forms the P trap of array;
6) through photoetching, define the source region, N type foreign ion injects, and pushes away trap formation N+ type source region;
7) with whole semi-conductor silicon chip surface deposition dielectric layer;
8), define the contact hole zone, and carry out the oxide layer etching through photoetching;
Deposited metal through photoetching, defines etch areas, carries out metal etch.
The MOSFET that this method produces has alleviated the lattice defect problem that produces because of repeatedly epitaxial growth, ion injection and diffusion; Also alleviated the problem of crossing the warpage of taking an advanced study into stress and wafer because of gash depth.
The above is merely preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of within spirit of the present invention and principle, being done, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (13)
1. a super-junction semiconductor element is characterized in that, comprising:
First conductivity type substrate;
Be arranged at first epitaxial loayer of first conduction type of one deck at least on first conductivity type substrate, comprise in said first epitaxial loayer that second conduction type mixes;
Be arranged at least the first conduction type second epitaxial loayer on first epitaxial loayer of first conduction type; Said second epitaxial loayer comprises that second conduction type mixes;
Second epitaxial loayer is provided with the device feature layer.
2. super-junction semiconductor element according to claim 1 is characterized in that, said second epitaxy layer thickness is greater than first epitaxy layer thickness.
3. super-junction semiconductor element according to claim 1 is characterized in that, said first conduction type is the N type, and second conduction type is the P type.
4. the manufacturing approach of a super-junction semiconductor element as claimed in claim 1 is characterized in that, comprising:
Step 1: first conductivity type substrate is provided;
Step 2: first epitaxial loayer of growth first conduction type on first conductivity type substrate, carry out the doping of second conduction type and inject on first epitaxial loayer;
Step 3: growth has second epitaxial loayer of first conduction type on first epitaxial loayer that carries out second conduction type doping injection completion; Etching on second epitaxial loayer, and in the groove of etching, make second conduction type and mix;
Step 4: on second epitaxial loayer, make the device characteristic layer.
5. the manufacturing approach of super-junction semiconductor element according to claim 4 is characterized in that, between said step 2 and step 3, also comprises the step of repeated execution of steps two.
6. the manufacturing approach of super-junction semiconductor element according to claim 4 is characterized in that, said second epitaxy layer thickness is greater than first epitaxy layer thickness.
7. the manufacturing approach of super-junction semiconductor element according to claim 4 is characterized in that, said first conduction type is the N type, and second conduction type is the P type.
8. the manufacturing approach of super-junction semiconductor element according to claim 4 is characterized in that, said step 3 also comprise with second conduction type mix be ground to identical with second epitaxy layer thickness.
9. the manufacturing approach of a super-junction semiconductor element as claimed in claim 1 is characterized in that, comprising:
Step 1: first conductivity type substrate is provided;
Step 2: the 3rd epitaxial loayer of growth first conduction type on first conductivity type substrate, etching on first epitaxial loayer, and in the groove of etching, make second conduction type and mix;
Step 3: growth has the 4th epitaxial loayer of first conduction type on the 3rd epitaxial loayer; On the 4th epitaxial loayer, carrying out the doping of second conduction type injects;
Step 4: on the 4th epitaxial loayer, make the device characteristic layer.
10. the manufacturing approach of super-junction semiconductor element according to claim 9 is characterized in that, between said step 3 and step 4, also comprises the step of repeated execution of steps three.
11. the manufacturing approach of super-junction semiconductor element according to claim 9 is characterized in that, said the 3rd epitaxy layer thickness prolongs layer thickness all round greater than.
12. the manufacturing approach of super-junction semiconductor element according to claim 9 is characterized in that, said first conduction type is the N type, and second conduction type is the P type.
13. the manufacturing approach of super-junction semiconductor element according to claim 9 is characterized in that, said step 2 also comprise with second conduction type mix be ground to identical with the 3rd epitaxy layer thickness.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105649509A CN102479805A (en) | 2010-11-30 | 2010-11-30 | Super junction semiconductor element and manufacture method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105649509A CN102479805A (en) | 2010-11-30 | 2010-11-30 | Super junction semiconductor element and manufacture method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102479805A true CN102479805A (en) | 2012-05-30 |
Family
ID=46092364
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010105649509A Pending CN102479805A (en) | 2010-11-30 | 2010-11-30 | Super junction semiconductor element and manufacture method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102479805A (en) |
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102709191A (en) * | 2012-06-07 | 2012-10-03 | 无锡市晶源微电子有限公司 | Process for manufacturing series of intermediate-voltage N-type vertical conduction double-diffused metal oxide semiconductor transistors by using composite epitaxy |
| CN102789990A (en) * | 2012-08-17 | 2012-11-21 | 西安龙腾新能源科技发展有限公司 | Manufacturing technology for super-junction device with shallow slot source electrode structure |
| CN102931090A (en) * | 2012-08-17 | 2013-02-13 | 西安龙腾新能源科技发展有限公司 | Manufacturing method for super junction metal oxide semiconductor field effect transistor (MOSFET) |
| CN102983177A (en) * | 2012-12-07 | 2013-03-20 | 杭州士兰集成电路有限公司 | Schottky diode and fabrication method thereof |
| CN103730371A (en) * | 2013-12-27 | 2014-04-16 | 西安龙腾新能源科技发展有限公司 | Method for manufacturing super junction high-voltage device |
| CN103730372A (en) * | 2013-12-27 | 2014-04-16 | 西安龙腾新能源科技发展有限公司 | Super junction manufacturing method capable of improving withstand voltage of device |
| CN104103524A (en) * | 2014-08-11 | 2014-10-15 | 肖胜安 | Super-junction device manufacturing method |
| CN104201099A (en) * | 2014-09-17 | 2014-12-10 | 中航（重庆）微电子有限公司 | Production process of super-junction device |
| CN105633153A (en) * | 2014-11-06 | 2016-06-01 | 比亚迪股份有限公司 | Super junction semiconductor device and formation method thereof |
| CN106328488A (en) * | 2015-06-25 | 2017-01-11 | 北大方正集团有限公司 | Super-junction power device manufacturing method and super-junction power device |
| CN109065612A (en) * | 2018-09-12 | 2018-12-21 | 深圳尚阳通科技有限公司 | A kind of super junction MOSFET structure and its manufacturing method |
| CN110137245A (en) * | 2019-04-30 | 2019-08-16 | 上海功成半导体科技有限公司 | Super junction device structure and preparation method thereof |
| CN112117330A (en) * | 2020-09-21 | 2020-12-22 | 南京华瑞微集成电路有限公司 | A device structure and process method for improving the withstand voltage of deep trench superjunction MOSFET |
| CN112382560A (en) * | 2020-11-12 | 2021-02-19 | 重庆万国半导体科技有限公司 | Multilayer epitaxial reduced-pressure growth method |
| CN113054000A (en) * | 2021-03-15 | 2021-06-29 | 无锡新洁能股份有限公司 | Super junction type field effect transistor and manufacturing method thereof |
| CN113299739A (en) * | 2021-05-21 | 2021-08-24 | 江苏东海半导体科技有限公司 | Power device epitaxial structure and manufacturing method thereof |
| CN113540204A (en) * | 2020-04-13 | 2021-10-22 | 上海新微技术研发中心有限公司 | Preparation method of semiconductor device structure |
| WO2023216648A1 (en) * | 2022-05-09 | 2023-11-16 | 瑶芯微电子科技(上海)有限公司 | Method for improving epitaxial growth stability of super-junction structure and preparing semiconductor device |
| CN117894820A (en) * | 2024-03-15 | 2024-04-16 | 芯联越州集成电路制造（绍兴）有限公司 | Superjunction semiconductor device and method for manufacturing the same |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1420569A (en) * | 2001-11-21 | 2003-05-28 | 同济大学 | Voltage-withstanding layer consisting of high dielectric coefficient medium and semiconductor |
| US20060043481A1 (en) * | 2004-08-24 | 2006-03-02 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| US20070001194A1 (en) * | 2005-06-30 | 2007-01-04 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| US7462909B2 (en) * | 2005-06-20 | 2008-12-09 | Kabushiki Kaisha Toshiba | Semiconductor device and method of fabricating the same |
| CN101872724A (en) * | 2009-04-24 | 2010-10-27 | 上海华虹Nec电子有限公司 | Manufacturing method of super junction MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) |
-
2010
- 2010-11-30 CN CN2010105649509A patent/CN102479805A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1420569A (en) * | 2001-11-21 | 2003-05-28 | 同济大学 | Voltage-withstanding layer consisting of high dielectric coefficient medium and semiconductor |
| US20060043481A1 (en) * | 2004-08-24 | 2006-03-02 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| US7462909B2 (en) * | 2005-06-20 | 2008-12-09 | Kabushiki Kaisha Toshiba | Semiconductor device and method of fabricating the same |
| US20070001194A1 (en) * | 2005-06-30 | 2007-01-04 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| CN101872724A (en) * | 2009-04-24 | 2010-10-27 | 上海华虹Nec电子有限公司 | Manufacturing method of super junction MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) |
Cited By (29)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102709191A (en) * | 2012-06-07 | 2012-10-03 | 无锡市晶源微电子有限公司 | Process for manufacturing series of intermediate-voltage N-type vertical conduction double-diffused metal oxide semiconductor transistors by using composite epitaxy |
| CN102789990A (en) * | 2012-08-17 | 2012-11-21 | 西安龙腾新能源科技发展有限公司 | Manufacturing technology for super-junction device with shallow slot source electrode structure |
| CN102931090A (en) * | 2012-08-17 | 2013-02-13 | 西安龙腾新能源科技发展有限公司 | Manufacturing method for super junction metal oxide semiconductor field effect transistor (MOSFET) |
| CN102931090B (en) * | 2012-08-17 | 2015-06-03 | 西安龙腾新能源科技发展有限公司 | Manufacturing method for super junction metal oxide semiconductor field effect transistor (MOSFET) |
| CN102789990B (en) * | 2012-08-17 | 2015-10-28 | 西安龙腾新能源科技发展有限公司 | A kind of manufacture craft of shallow slot source electrode structure superjunction devices |
| CN102983177B (en) * | 2012-12-07 | 2016-12-21 | 杭州士兰集成电路有限公司 | Schottky diode and preparation method thereof |
| CN102983177A (en) * | 2012-12-07 | 2013-03-20 | 杭州士兰集成电路有限公司 | Schottky diode and fabrication method thereof |
| CN103730371A (en) * | 2013-12-27 | 2014-04-16 | 西安龙腾新能源科技发展有限公司 | Method for manufacturing super junction high-voltage device |
| CN103730372A (en) * | 2013-12-27 | 2014-04-16 | 西安龙腾新能源科技发展有限公司 | Super junction manufacturing method capable of improving withstand voltage of device |
| CN103730372B (en) * | 2013-12-27 | 2016-06-08 | 西安龙腾新能源科技发展有限公司 | A kind of superjunction manufacture method improving device withstand voltage |
| CN104103524A (en) * | 2014-08-11 | 2014-10-15 | 肖胜安 | Super-junction device manufacturing method |
| CN104103524B (en) * | 2014-08-11 | 2019-03-12 | 肖胜安 | A kind of super junction device fabrication method |
| CN104201099B (en) * | 2014-09-17 | 2018-05-29 | 中航（重庆）微电子有限公司 | Superjunction devices preparation process |
| CN104201099A (en) * | 2014-09-17 | 2014-12-10 | 中航（重庆）微电子有限公司 | Production process of super-junction device |
| CN105633153A (en) * | 2014-11-06 | 2016-06-01 | 比亚迪股份有限公司 | Super junction semiconductor device and formation method thereof |
| CN105633153B (en) * | 2014-11-06 | 2019-01-11 | 比亚迪股份有限公司 | Super junction-semiconductor device and forming method thereof |
| CN106328488B (en) * | 2015-06-25 | 2020-10-16 | 北大方正集团有限公司 | Preparation method of superjunction power device and superjunction power device |
| CN106328488A (en) * | 2015-06-25 | 2017-01-11 | 北大方正集团有限公司 | Super-junction power device manufacturing method and super-junction power device |
| CN109065612A (en) * | 2018-09-12 | 2018-12-21 | 深圳尚阳通科技有限公司 | A kind of super junction MOSFET structure and its manufacturing method |
| CN110137245A (en) * | 2019-04-30 | 2019-08-16 | 上海功成半导体科技有限公司 | Super junction device structure and preparation method thereof |
| CN113540204A (en) * | 2020-04-13 | 2021-10-22 | 上海新微技术研发中心有限公司 | Preparation method of semiconductor device structure |
| CN112117330A (en) * | 2020-09-21 | 2020-12-22 | 南京华瑞微集成电路有限公司 | A device structure and process method for improving the withstand voltage of deep trench superjunction MOSFET |
| CN112117330B (en) * | 2020-09-21 | 2024-05-07 | 南京华瑞微集成电路有限公司 | A device structure and process method for improving the withstand voltage of deep trench super junction MOSFET |
| CN112382560A (en) * | 2020-11-12 | 2021-02-19 | 重庆万国半导体科技有限公司 | Multilayer epitaxial reduced-pressure growth method |
| WO2022100408A1 (en) * | 2020-11-12 | 2022-05-19 | 重庆万国半导体科技有限公司 | Multilayer reduced pressure epitaxial growth method |
| CN113054000A (en) * | 2021-03-15 | 2021-06-29 | 无锡新洁能股份有限公司 | Super junction type field effect transistor and manufacturing method thereof |
| CN113299739A (en) * | 2021-05-21 | 2021-08-24 | 江苏东海半导体科技有限公司 | Power device epitaxial structure and manufacturing method thereof |
| WO2023216648A1 (en) * | 2022-05-09 | 2023-11-16 | 瑶芯微电子科技(上海)有限公司 | Method for improving epitaxial growth stability of super-junction structure and preparing semiconductor device |
| CN117894820A (en) * | 2024-03-15 | 2024-04-16 | 芯联越州集成电路制造（绍兴）有限公司 | Superjunction semiconductor device and method for manufacturing the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102479805A (en) | Super junction semiconductor element and manufacture method thereof | |
| US10319808B2 (en) | Semiconductor device | |
| CN107204372B (en) | A trench type semiconductor device with an optimized terminal structure and its manufacturing method | |
| US20120049902A1 (en) | Integrated electronic device and method for manufacturing thereof | |
| US8680608B2 (en) | Power semiconductor device with a low on resistence | |
| CN104051540B (en) | Superjunction device and method of making the same | |
| US7049658B2 (en) | Power semiconductor device | |
| KR20020041308A (en) | Semiconductor device | |
| US9960268B2 (en) | Semiconductor devices, power semiconductor devices, and methods for forming a semiconductor device | |
| KR101315699B1 (en) | Power mosfet having superjunction trench and fabrication method thereof | |
| CN107611167B (en) | Super-junction semiconductor device with multiple concentration centers and manufacturing method thereof | |
| JP2003101022A (en) | Power semiconductor device | |
| US10424637B2 (en) | Method of manufacturing semiconductor device | |
| US10170605B2 (en) | MOS-bipolar device | |
| US20210391418A1 (en) | Super junction power device and method of making the same | |
| CN118763119A (en) | A super junction power device and a method for manufacturing the same | |
| CN102347364B (en) | There is the semiconductor device of drift region and compensatory zone | |
| CN103199018A (en) | Manufacturing method of field blocking type semiconductor device and device structure | |
| US20240234567A1 (en) | Buried shield structures for power semiconductor devices including segmented support shield structures for reduced on-resistance and related fabrication methods | |
| CN115458604B (en) | MOSFET device and its manufacturing method | |
| CN118431285A (en) | Silicon carbide power MOSFET device with improved performance and process for making same | |
| CN211017082U (en) | Super junction type MOSFET device | |
| CN112635331A (en) | Preparation method of super junction power device | |
| CN113808943B (en) | Super junction power device and preparation method thereof | |
| US20240234507A1 (en) | Buried shield structures for power semiconductor devices and related fabrication methods |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20120530 |